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CN109216257A - The manufacturing method of the isolation structure of LDMOS - Google Patents

The manufacturing method of the isolation structure of LDMOS Download PDF

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Publication number
CN109216257A
CN109216257A CN201710534702.1A CN201710534702A CN109216257A CN 109216257 A CN109216257 A CN 109216257A CN 201710534702 A CN201710534702 A CN 201710534702A CN 109216257 A CN109216257 A CN 109216257A
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trench
silicon oxide
forming
groove
nitrogen
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CN109216257B (en
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祁树坤
孙贵鹏
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CSMC Technologies Corp
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CSMC Technologies Corp
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Priority to CN201710534702.1A priority Critical patent/CN109216257B/en
Priority to PCT/CN2018/094354 priority patent/WO2019007343A1/en
Priority to US16/481,576 priority patent/US11127840B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
    • H10D30/0289—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
    • H10P14/6322—
    • H10P14/6336—
    • H10P14/69215—
    • H10P14/69433—
    • H10P50/283—
    • H10P50/73—
    • H10P76/4085—
    • H10W10/0145—
    • H10W10/0147—
    • H10W10/17—

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  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明涉及一种LDMOS的隔离结构的制造方法，包括：在晶圆表面形成第一沟槽；向第一沟槽内填充氧化硅；通过刻蚀去除掉第一沟槽内的氧化硅表面的一部分；通过热氧化在第一沟槽顶部的拐角处形成氧化硅拐角结构；在晶圆表面淀积含氮化合物，覆盖第一沟槽内的氧化硅表面及氧化硅拐角结构表面；干法刻蚀含氮化合物，将第一沟槽内的氧化硅表面的含氮化合物去除，形成含氮化合物侧壁残留；以含氮化合物侧壁残留为掩膜，继续向下刻蚀形成第二沟槽；在第二沟槽的侧壁和底部形成氧化硅层；去除含氮化合物侧壁残留；向第一沟槽和第二沟槽内填充氧化硅。本发明可以提高击穿电压，节省了光刻版。

The invention relates to a manufacturing method of an LDMOS isolation structure, which comprises: forming a first trench on the surface of a wafer; filling the first trench with silicon oxide; removing the silicon oxide surface in the first trench by etching Part; forming a silicon oxide corner structure at the corner of the top of the first trench by thermal oxidation; depositing a nitrogen-containing compound on the wafer surface to cover the silicon oxide surface in the first trench and the surface of the silicon oxide corner structure; dry etching Etching the nitrogen-containing compound to remove the nitrogen-containing compound on the silicon oxide surface in the first trench to form a nitrogen-containing compound sidewall residue; using the nitrogen-containing compound sidewall residue as a mask, continue to etch down to form a second trench ; forming a silicon oxide layer on the sidewalls and bottom of the second trench; removing the residual nitrogen-containing compound sidewalls; filling the first trench and the second trench with silicon oxide. The invention can improve the breakdown voltage and save the photolithography plate.

Description

The manufacturing method of the isolation structure of LDMOS
Technical field
The present invention relates to field of semiconductor manufacture, and more particularly to a kind of LDMOS, (lateral double diffusion metal oxide is partly led Body field-effect tube) isolation structure manufacturing method.
Background technique
In the drift region of LDMOS (lateral double diffusion metal oxide semiconductor field-effect tube) device introduce shallow trench every From (Shallow-Trench-Isolation, STI) technique, longitudinally extends drift region length simultaneously to substrate, device can be reduced Length reduces area in turn, while STI reduces device grids/drain electrode electric field, reduces parasitic capacitance, significantly improves device The optimization window of part pressure resistance BVdss and conducting resistance Ron, sp.
The two sidewalls of general fleet plough groove isolation structure are parallel and are distributed vertically, will cause electric field and concentrate on shallow trench isolation The corner of source area is leaned in the bottom of structure, so that the non-uniform electric between source region and drain region, and will cause The corner of the bottom middle position of fleet plough groove isolation structure and separate source region generates new intensive electric field, in the new intensive electricity Lateral voltage breakdown is easy to happen at.
Summary of the invention
Based on this, it is necessary to provide a kind of manufacturing method of the isolation structure of LDMOS.
A kind of manufacturing method of the isolation structure of LDMOS, comprising: first groove wide at the top and narrow at the bottom is formed in crystal column surface； Silica is filled into the first groove by depositing；By one that etches the silicon oxide surface got rid of in first groove Point；Form silica corner structure by corner of the thermal oxide at the top of first groove, the silica corner structure be from The structure that silica of the corner down, inside first groove gradually thickens；Nitrogenous compound is deposited in crystal column surface, is covered Cover the silicon oxide surface in the first groove and silica corner structure surface；Nitrogenous compound described in dry etching, The nitrogenous compound of silicon oxide surface in first groove is removed, silica corner structure surface is formed prolongs into groove The nitrogenous compound side wall residual stretched；It is remained with the nitrogenous compound side wall as exposure mask, continues downward etching oxidation silicon and crystalline substance Circle forms second groove；Silicon oxide layer is formed in the side wall of the second groove and bottom；Remove the nitrogenous compound side wall Residual；Silica is filled into the first groove and second groove.
The depth of the first groove is 1 micron~2 microns in one of the embodiments,.
It is described in one of the embodiments, to be the step of the side wall of the second groove and bottom form silicon oxide layer Using thermal oxidation technology, the silicon oxide layer of formation is with a thickness of 1000 angstroms or more.
It is described in the step of crystal column surface forms first groove wide at the top and narrow at the bottom in one of the embodiments, it is formed First groove inclined-plane inclination angle be 60~70 degree.
In one of the embodiments, before described the step of filling silica into the first groove by deposit also Include the steps that carrying out sidewall oxidation to the first groove.
It is described in one of the embodiments, also to be wrapped before the step of crystal column surface forms first groove wide at the top and narrow at the bottom Include crystal column surface formed silicon nitride layer the step of, described the step of first groove wide at the top and narrow at the bottom is formed in crystal column surface be by The silicon nitride layer cuts through to form the first groove.
It is described the step of crystal column surface forms first groove wide at the top and narrow at the bottom and described in one of the embodiments, It is using CHCl described in dry etching the step of nitrogenous compound3And/or CH2Cl2As etching agent.
It is described the step of crystal column surface forms first groove wide at the top and narrow at the bottom in one of the embodiments, be using Fluoro-gas etches the first groove.
The corner by thermal oxide at the top of first groove forms silica turning in one of the embodiments, In the step of structure, oxidizing temperature is 800~950 degrees Celsius.
The nitrogenous compound is silicon nitride in one of the embodiments,.
The manufacturing method of the isolation structure of above-mentioned LDMOS, using first groove+second groove double-layer structure, upper layer is shallow The presence of groove isolation construction can widen the depleted region at the bottom corners of lower layer's fleet plough groove isolation structure, avoid generating New intensive electric field, the field distribution between source region and drain region tends to be flat, to improve breakdown voltage.Using nitrogenous chemical combination Object side wall remains the hard exposure mask as etching second trenches, saves reticle.
Detailed description of the invention
Fig. 1 is the flow chart of the manufacturing method of the isolation structure of LDMOS in an embodiment；
Fig. 2 to Fig. 6 is using the device of the manufacturing method manufacture of the isolation structure of LDMOS in an embodiment in manufacturing process In cross-sectional view.
Specific embodiment
To facilitate the understanding of the present invention, a more comprehensive description of the invention is given in the following sections with reference to the relevant attached drawings.In attached drawing Give preferred embodiment of the invention.But the invention can be realized in many different forms, however it is not limited to this paper institute The embodiment of description.On the contrary, purpose of providing these embodiments is make it is more thorough and comprehensive to the disclosure.
Unless otherwise defined, all technical and scientific terms used herein and belong to technical field of the invention The normally understood meaning of technical staff is identical.Term as used herein in the specification of the present invention is intended merely to description tool The purpose of the embodiment of body, it is not intended that in the limitation present invention.Term " and or " used herein includes one or more phases Any and all combinations of the listed item of pass.
Semiconductor field vocabulary used herein is the common technical words of those skilled in the art, such as p-type And P+ type is easily represented the p-type of heavy dopant concentration to distinguish doping concentration by N-type impurity, the P of doping concentration in p-type representative Type, P-type represent the p-type that concentration is lightly doped, and N+ type represents the N-type of heavy dopant concentration, the N-type of doping concentration, N- in N-type representative Type represents the N-type that concentration is lightly doped.
Fig. 1 is the flow chart of the manufacturing method of the isolation structure of LDMOS in an embodiment, including the following steps:
S110 forms first groove wide at the top and narrow at the bottom in crystal column surface.
The technique that this field can be used known goes out wide at the top and narrow at the bottom in wafer (for silicon wafer in the present embodiment) surface etch First groove (shallow slot).In the present embodiment, before etching forms first groove one layer of nitridation first can be formed in crystal column surface Silicon fiml dissolves etching window by photoetching agent pattern on silicon nitride film, then cuts through silicon nitride film by etching window and formed First groove, after the completion of etching at the top of first groove around be formed with silicon nitride layer.In the present embodiment, etch nitride silicon fiml It is using CHCl3And/or CH2Cl2Dry etching is carried out as etching agent, other abilities can also be used in other embodiments The known trench etch process in domain performs etching.Etching adds fluoro-gas into etching gas after wearing silicon nitride film, such as SF6, first groove is formed with etching silicon wafer.In the present embodiment, the inclination angle on the inclined-plane of the first groove etched is 60~70 Degree.
The wider width on the top of first groove, groove isolation construction finally formed in this way can be dropped relative to narrow groove Electric leakage possibility caused by high pressure cabling above low groove isolation construction.In one embodiment, the depth of first groove is 1 Micron~2 microns.
In one embodiment, the extension of low doping concentration is extended outside by epitaxy technique on the substrate of high-dopant concentration Layer, the groove that step S110 is etched are formed in epitaxial layer.
S120 fills silica into first groove by deposit.
Silica (SiO is formed by depositing technicsx) speed of layer passes through thermal oxide growth silica much larger than traditional The speed of layer.In the present embodiment, step S120 is carried out using high-density plasma chemical vapor deposition (HDPCVD) technique The deposit of silica can obtain preferable pattern.Other abilities can also be used according to actual needs in other embodiments The known depositing technics silicon oxide deposition layer in domain.
Extra silicon oxide layer can be removed by chemical mechanical grinding (CMP) after having deposited, i.e., will be exposed to groove The silicon oxide layer of outside removes.Go out the embodiment of first groove, CMP as hard mask etching using silicon nitride for step S110 It is that silicon oxide layer is ground to the silicon nitride layer.
In one embodiment, further include that sidewall oxidation is carried out to first groove before step S120, form sidewall oxidation The step of layer 204.Sidewall oxidation can play the silicon table for repairing the etching groove of step S110 in first groove inner wall and bottom Face generate defect (such as because reactive ion etching energetic particle hits generate defect) effect, eliminate the defect to grid The negative effect that oxygen generates.
S130 gets rid of a part of the silicon oxide surface in first groove by etching.
Dry etching can be used, obtains suitable pattern using its anisotropy.Fig. 2 is step S130 in the present embodiment The cross-sectional view of device after the completion.Step S130 selects the technique of high-density plasma etching to carry out in one of the embodiments, Etching.
S140 forms silica corner structure by aoxidizing the corner at the top of first groove.
Pattern needed for this programme can be formed for the residual of nitrogenous compound side wall obtained in subsequent step, after etching Special turning pattern is formed by oxidation, i.e., silicon oxide surface in the trench, which is formed, is similar to hemispheric concave surface.From turning At angle down, the silica that is located in the groove portion gradually thicken, to form round and smooth turning, as shown in Figure 3.In silicon in Fig. 3 The surface of piece is formed with first groove, fills silica 202 in first groove, at the top of first groove around be formed with nitridation Silicon layer 302.The silica corner structure is obtained by 800~950 degrees Celsius of low-temperature oxidation in the present embodiment.Using low Temperature oxidation is because inventor's discovery is according to higher temperature (such as 1000 degrees Celsius of sacrifice aoxidizes), then wafer is highly concentrated The Doped ions spent in substrate are easy anti-expansion into the epitaxial layer 102 of low concentration, have a negative impact to device performance.
S150 covers silicon oxide surface and silica corner structure in first groove in crystal column surface deposit silicon nitride Surface.
One layer of thin nitrogenous compound is formed in this embodiment by chemical vapor deposition, it is subsequent as the hard of etching Exposure mask.The nitrogenous compound can be silicon nitride, silicon oxynitride, boron nitride, titanium nitride etc., it is contemplated that universality can use Silicon nitride commonly used in the art.
S160, dry etching nitrogenous compound, silica corner structure surface formed extend into first groove it is nitrogenous Compound side wall residual.
The nitrogenous compound on 202 surface of silica in groove is gone using the anisotropy of dry etching referring to Fig. 3 It removes, while forming the nitrogenous compound side wall residual 304 extended into groove on silica corner structure surface.Nitrogenous compound Side wall residual 304 is with a part of silica 202 in groove collectively as the side wall construction of groove.
S170 is remained with nitrogenous compound side wall as exposure mask, continues downward etching oxidation silicon and wafer forms second groove.
Referring to fig. 4, nitrogenous compound side wall remains 304 a part that can cover first groove, therefore not by nitrogen The region for closing 304 covering of object side wall residual will be etched away downwards (i.e. partial oxidation silicon 202, sidewall oxide 204 and extension Layer 102 is etched removal) formation second groove 201 (deep trouth).The width of second groove 201 is remained by nitrogenous compound side wall 304 limitations, it is thus evident that the width of second groove 201 is less than the width on the top of first groove, the depth of second groove 201 Greater than the depth of first groove.Hard exposure mask using nitrogenous compound side wall residual 304 as second groove etching, can be not required to Reticle is wanted, cost can be saved.
In one embodiment, the depth of second groove 201 is 5 microns~10 microns, in other embodiments even can With deeper.
S180 forms silicon oxide layer in the side wall of second groove and bottom.
In the present embodiment, it is that silicon oxide layer 206 is formed by the technique of thermal oxide, is remained by nitrogenous compound side wall The position of 304 coverings not will form silicon oxide layer 206, referring to Fig. 5.
S190, removal nitrogenous compound side wall residual.
It is clean in order to remove nitrogenous compound, wet etching can be used, such as carved by etching agent of concentrated phosphoric acid Erosion.Silicon nitride layer 302 and nitrogenous compound side wall residual 304 are removed together by concentrated phosphoric acid in the present embodiment.
S200 fills silica into first groove and second groove.
It in the present embodiment, is the shallow lake that silica is carried out using high-density plasma chemical vapor deposition (HDPCVD) technique Product.Planarization process, ginseng can be carried out to the silica for exposing first groove by chemical mechanical grinding after the completion of step S210 Add Fig. 6.
The manufacturing method of the isolation structure of above-mentioned LDMOS uses first groove+second groove double-layer structure, upper layer shallow ridges The presence of recess isolating structure can widen the depleted region at the bottom corners of lower layer's fleet plough groove isolation structure, avoid generating new Intensive electric field, the field distribution between source region and drain region tends to be flat, to improve breakdown voltage.Using nitrogenous compound Side wall remains the hard exposure mask as etching second trenches, saves reticle.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneously It cannot therefore be construed as limiting the scope of the patent.It should be pointed out that coming for those of ordinary skill in the art It says, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to protection of the invention Range.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.

Claims (10)

1.一种LDMOS的隔离结构的制造方法，包括：1. A method for manufacturing an isolation structure of an LDMOS, comprising: 在晶圆表面形成上宽下窄的第一沟槽；forming a first trench with an upper width and a lower width on the surface of the wafer; 通过淀积向所述第一沟槽内填充氧化硅；Filling the first trench with silicon oxide by deposition; 通过刻蚀去除掉第一沟槽内的氧化硅表面的一部分；removing a part of the silicon oxide surface in the first trench by etching; 通过热氧化在第一沟槽顶部的拐角处形成氧化硅拐角结构，所述氧化硅拐角结构为从拐角处往下、位于第一沟槽内部的氧化硅逐渐变厚的结构；A silicon oxide corner structure is formed at the corner of the top of the first trench by thermal oxidation, and the silicon oxide corner structure is a structure in which the silicon oxide inside the first trench gradually thickens from the corner downward; 在晶圆表面淀积含氮化合物，覆盖所述第一沟槽内的氧化硅表面及所述氧化硅拐角结构表面；depositing a nitrogen-containing compound on the wafer surface to cover the silicon oxide surface in the first trench and the silicon oxide corner structure surface; 干法刻蚀所述含氮化合物，将第一沟槽内的氧化硅表面的含氮化合物去除，所述氧化硅拐角结构表面形成向沟槽内延伸的含氮化合物侧壁残留；dry etching the nitrogen-containing compound to remove the nitrogen-containing compound on the surface of the silicon oxide in the first trench, and forming a nitrogen-containing compound sidewall residue extending into the trench on the surface of the silicon oxide corner structure; 以所述含氮化合物侧壁残留为掩膜，继续向下刻蚀氧化硅和晶圆形成第二沟槽；Using the residual nitrogen-containing compound sidewall as a mask, continue to etch the silicon oxide and the wafer downward to form a second trench; 在所述第二沟槽的侧壁和底部形成氧化硅层；forming a silicon oxide layer on the sidewall and bottom of the second trench; 去除所述含氮化合物侧壁残留；removing the nitrogen-containing compound sidewall residue; 向所述第一沟槽和第二沟槽内填充氧化硅。Filling the first trench and the second trench with silicon oxide. 2.根据权利要求1所述的制造方法，其特征在于，所述第一沟槽的深度为1微米～2微米。2 . The manufacturing method according to claim 1 , wherein the depth of the first trench is 1 μm˜2 μm. 3 . 3.根据权利要求1所述的制造方法，其特征在于，所述在所述第二沟槽的侧壁和底部形成氧化硅层的步骤是采用热氧化工艺，形成的氧化硅层厚度为1000埃以上。3 . The manufacturing method according to claim 1 , wherein the step of forming a silicon oxide layer on the sidewall and bottom of the second trench is a thermal oxidation process, and the thickness of the formed silicon oxide layer is 1000 Å. 4 . above. 4.根据权利要求1所述的制造方法，其特征在于，所述在晶圆表面形成上宽下窄的第一沟槽的步骤中，形成的第一沟槽的斜面的倾角为60～70度。4 . The manufacturing method according to claim 1 , wherein, in the step of forming a first trench with an upper width and a lower width on the wafer surface, the inclination angle of the inclined surface of the first trench is 60˜70 . Spend. 5.根据权利要求1所述的制造方法，其特征在于，所述通过淀积向所述第一沟槽内填充氧化硅的步骤之前还包括对所述第一沟槽进行侧壁氧化的步骤。5 . The manufacturing method according to claim 1 , wherein the step of filling silicon oxide into the first trench by deposition further comprises the step of oxidizing the sidewall of the first trench. 6 . . 6.根据权利要求1所述的制造方法，其特征在于，所述在晶圆表面形成上宽下窄的第一沟槽的步骤之前还包括在晶圆表面形成氮化硅层的步骤，所述在晶圆表面形成上宽下窄的第一沟槽的步骤是将所述氮化硅层刻穿形成所述第一沟槽。6 . The manufacturing method according to claim 1 , wherein before the step of forming the first trench with upper width and lower narrow width on the surface of the wafer, the method further comprises the step of forming a silicon nitride layer on the surface of the wafer. 7 . The step of forming a first trench with an upper width and a lower width on the wafer surface is to etch through the silicon nitride layer to form the first trench. 7.根据权利要求6所述的制造方法，其特征在于，所述在晶圆表面形成上宽下窄的第一沟槽的步骤，和所述干法刻蚀所述含氮化合物的步骤，是采用CHCl3和/或CH2Cl2作为刻蚀剂。7. The manufacturing method according to claim 6, wherein the step of forming a first trench with an upper width and a lower width on the wafer surface, and the step of dry etching the nitrogen-containing compound, CHCl 3 and/or CH 2 Cl 2 are used as etchants. 8.根据权利要求1所述的制造方法，其特征在于，所述在晶圆表面形成上宽下窄的第一沟槽的步骤，是使用含氟气体刻蚀出所述第一沟槽。8 . The manufacturing method according to claim 1 , wherein the step of forming a first trench with an upper width and a lower width on the wafer surface is to use a fluorine-containing gas to etch the first trench. 9 . 9.根据权利要求1所述的制造方法，其特征在于，所述通过热氧化在第一沟槽顶部的拐角处形成氧化硅拐角结构的步骤中，氧化温度为800～950摄氏度。9 . The manufacturing method according to claim 1 , wherein, in the step of forming a silicon oxide corner structure at the corner of the top of the first trench by thermal oxidation, the oxidation temperature is 800-950 degrees Celsius. 10 . 10.根据权利要求1所述的制造方法，其特征在于，所述含氮化合物是氮化硅。10. The method of claim 1, wherein the nitrogen-containing compound is silicon nitride.
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* Cited by examiner, † Cited by third party
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CN111477546A (en) * 2020-03-16 2020-07-31 绍兴同芯成集成电路有限公司 A process for generating multi-step trench transistors using silicon nitride isolation layers
CN114334621A (en) * 2022-01-04 2022-04-12 广东芯粤能半导体有限公司 Semiconductor structure, semiconductor device and preparation method thereof

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Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH104136A (en) * 1996-04-15 1998-01-06 Samsung Electron Co Ltd Method for forming element isolation film of semiconductor device
US5940719A (en) * 1996-04-22 1999-08-17 Hyundai Electronics Industries Co., Ltd. Method for forming element isolating film of semiconductor device
JP2002076287A (en) * 2000-08-28 2002-03-15 Nec Kansai Ltd Semiconductor device and method of manufacturing the same
US6812120B1 (en) * 2004-02-26 2004-11-02 Powerchip Semiconductor Corp. Method of forming floating gate of memory device
US20060264003A1 (en) * 2005-05-18 2006-11-23 Hynix Semiconductor Inc. Trench isolation structure in a semiconductor device and method for fabricating the same
CN1913120A (en) * 2005-07-26 2007-02-14 尔必达存储器株式会社 Method of manufacturing a semiconductor device and the semiconductor device
CN101673702A (en) * 2009-09-22 2010-03-17 上海宏力半导体制造有限公司 Fabricating method of shallow trench isolation structure
CN102087989A (en) * 2009-12-02 2011-06-08 无锡华润上华半导体有限公司 Method for manufacturing shallow groove isolation structure
CN103258842A (en) * 2013-05-02 2013-08-21 上海华力微电子有限公司 Double-layer shallow groove isolation structure, manufacturing method and transverse diffusion metal oxide semiconductor (MOS) tube
CN103811323A (en) * 2012-11-13 2014-05-21 中芯国际集成电路制造(上海)有限公司 Fin portion manufacturing method and fin type field effect transistor and manufacturing method thereof
CN104517886A (en) * 2013-09-29 2015-04-15 无锡华润上华科技有限公司 Method for forming shallow trench isolation structure

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW407335B (en) * 1998-01-23 2000-10-01 United Microelectronics Corp Method of producing shallow trench isolation
US6417070B1 (en) * 2000-12-13 2002-07-09 International Business Machines Corporation Method for forming a liner in a trench
US7435661B2 (en) * 2006-01-27 2008-10-14 Atmel Corporation Polish stop and sealing layer for manufacture of semiconductor devices with deep trench isolation
KR20130087929A (en) 2012-01-30 2013-08-07 에스케이하이닉스 주식회사 Semiconductor device having trench isolation layer and method of fabricating the same

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH104136A (en) * 1996-04-15 1998-01-06 Samsung Electron Co Ltd Method for forming element isolation film of semiconductor device
US5940719A (en) * 1996-04-22 1999-08-17 Hyundai Electronics Industries Co., Ltd. Method for forming element isolating film of semiconductor device
JP2002076287A (en) * 2000-08-28 2002-03-15 Nec Kansai Ltd Semiconductor device and method of manufacturing the same
US6812120B1 (en) * 2004-02-26 2004-11-02 Powerchip Semiconductor Corp. Method of forming floating gate of memory device
US20060264003A1 (en) * 2005-05-18 2006-11-23 Hynix Semiconductor Inc. Trench isolation structure in a semiconductor device and method for fabricating the same
CN1913120A (en) * 2005-07-26 2007-02-14 尔必达存储器株式会社 Method of manufacturing a semiconductor device and the semiconductor device
CN101673702A (en) * 2009-09-22 2010-03-17 上海宏力半导体制造有限公司 Fabricating method of shallow trench isolation structure
CN102087989A (en) * 2009-12-02 2011-06-08 无锡华润上华半导体有限公司 Method for manufacturing shallow groove isolation structure
CN103811323A (en) * 2012-11-13 2014-05-21 中芯国际集成电路制造(上海)有限公司 Fin portion manufacturing method and fin type field effect transistor and manufacturing method thereof
CN103258842A (en) * 2013-05-02 2013-08-21 上海华力微电子有限公司 Double-layer shallow groove isolation structure, manufacturing method and transverse diffusion metal oxide semiconductor (MOS) tube
CN104517886A (en) * 2013-09-29 2015-04-15 无锡华润上华科技有限公司 Method for forming shallow trench isolation structure

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110854061A (en) * 2019-11-26 2020-02-28 上海华力微电子有限公司 Process method for improving isolation effect of ultra-shallow isolation groove
CN111446167A (en) * 2020-03-16 2020-07-24 绍兴同芯成集成电路有限公司 A process for generating multi-step trench transistors using polymer isolation layers
CN111477546A (en) * 2020-03-16 2020-07-31 绍兴同芯成集成电路有限公司 A process for generating multi-step trench transistors using silicon nitride isolation layers
CN111477546B (en) * 2020-03-16 2023-02-07 绍兴同芯成集成电路有限公司 A process for forming multi-step trench transistors using silicon nitride isolation layers
CN114334621A (en) * 2022-01-04 2022-04-12 广东芯粤能半导体有限公司 Semiconductor structure, semiconductor device and preparation method thereof
CN114334621B (en) * 2022-01-04 2023-08-11 广东芯粤能半导体有限公司 Semiconductor structure, semiconductor device and preparation method thereof

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