CN109216153A - Improve the method for silicon nitride corrosion resistance and the preparation method of semiconductor devices - Google Patents
Improve the method for silicon nitride corrosion resistance and the preparation method of semiconductor devices Download PDFInfo
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- CN109216153A CN109216153A CN201710534160.8A CN201710534160A CN109216153A CN 109216153 A CN109216153 A CN 109216153A CN 201710534160 A CN201710534160 A CN 201710534160A CN 109216153 A CN109216153 A CN 109216153A
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- 229910052581 Si3N4 Inorganic materials 0.000 title claims abstract description 158
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 title claims abstract description 158
- 238000000034 method Methods 0.000 title claims abstract description 49
- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 238000005260 corrosion Methods 0.000 title claims abstract description 35
- 230000007797 corrosion Effects 0.000 title claims abstract description 35
- 238000002360 preparation method Methods 0.000 title claims abstract description 14
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims abstract description 82
- 238000000137 annealing Methods 0.000 claims abstract description 77
- 229910021529 ammonia Inorganic materials 0.000 claims abstract description 41
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims abstract description 39
- 229910000077 silane Inorganic materials 0.000 claims abstract description 39
- 238000001039 wet etching Methods 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 24
- 239000000376 reactant Substances 0.000 claims abstract description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 21
- 239000003795 chemical substances by application Substances 0.000 claims description 18
- 238000001312 dry etching Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 8
- 238000005224 laser annealing Methods 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 18
- 229920005591 polysilicon Polymers 0.000 abstract description 18
- 230000002708 enhancing effect Effects 0.000 abstract description 8
- 239000007789 gas Substances 0.000 description 46
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 24
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 13
- 150000002500 ions Chemical class 0.000 description 12
- 229910052757 nitrogen Inorganic materials 0.000 description 12
- 238000010438 heat treatment Methods 0.000 description 10
- 239000012299 nitrogen atmosphere Substances 0.000 description 9
- 238000010792 warming Methods 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 239000002390 adhesive tape Substances 0.000 description 6
- 239000010453 quartz Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000002253 acid Substances 0.000 description 5
- 238000001816 cooling Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 5
- 230000003628 erosive effect Effects 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 150000001335 aliphatic alkanes Chemical class 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 241000209140 Triticum Species 0.000 description 1
- 235000021307 Triticum Nutrition 0.000 description 1
- 239000003708 ampul Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Weting (AREA)
- Drying Of Semiconductors (AREA)
- Formation Of Insulating Films (AREA)
Abstract
The present invention relates to the preparation methods of a kind of method for improving silicon nitride corrosion resistance and semiconductor devices.The method for improving silicon nitride corrosion resistance includes: offer semiconductor substrate；Using plasma enhances chemical vapor deposition silicon nitride layer on the semiconductor substrate；The silicon nitride layer is deposited using ammonia and silane as reactant, and the gas flow ratio range of the silane and ammonia is 3~6；The silicon nitride layer is made annealing treatment；Substrate described in wet etching and erodable section is carried out to the silicon nitride layer.By the above method, the adhesiveness enhancing of the corrosion resistance enhancing of silicon nitride, silicon nitride layer film layer (polysilicon layer or oxide layer) adjacent thereto also reduces the lateral undercutting size at silicon nitride layer interface after the techniques such as wet etching simultaneously.
Description
Technical field
The present invention relates to a kind of semiconductor fabrication techniques field, more particularly to the method for improving silicon nitride corrosion resistance and
The preparation method of semiconductor devices.
Background technique
Silicon nitride is a kind of common dielectric material in semiconductor fabrication.In current semiconductor fabrication, silicon nitride
Mainly with low-pressure chemical vapor deposition (Low-pressure CVD, LPCVD) or plasma enhanced chemical vapor deposition
(Plasma-Enhanced CVD, PECVD) is formed.But in MEMS manufacture craft, need to deposit thicker silicon nitride layer
When, then select the mode of plasma enhanced chemical vapor deposition PECVD to form silicon nitride layer.But wet-etching technology
When, the corrosion rate of PECVD silicon nitride layer is fast, and the solution such as buffered oxide etch liquid (BOE) are easier along silicon nitride layer
Interface undercutting with other film layers (silicon nitride layer LPSIN or polysilicon layer made of low-pressure chemical vapor deposition) is entered, on boundary
Lateral undercutting is formed at face.
Summary of the invention
Based on this, it is necessary to it is fast for corrosion rate, in silicon nitride section lateral undercutting problem easy to form, provide one kind
Corrosion resistance is strong in wet-etching technology, and can reduce the cross at silicon nitride layer interface as the raising silicon nitride of undercut is resistance to
The preparation method of corrosive method and semiconductor devices.
A method of improving silicon nitride corrosion resistance, comprising:
Semiconductor substrate is provided；
Using plasma enhances chemical vapor deposition silicon nitride layer on the semiconductor substrate；The nitridation
Silicon layer is deposited using ammonia and silane as reactant, and the gas flow ratio range of the silane and ammonia is 3~6；
The silicon nitride layer is made annealing treatment；
Substrate described in wet etching and erodable section is carried out to the silicon nitride layer.
The method of above-mentioned raising silicon nitride corrosion resistance, comprising: semiconductor substrate is provided；It is adopted on the semiconductor substrate
With plasma enhanced chemical vapor deposition method deposited silicon nitride layer；The silicon nitride layer is heavy as reactant using ammonia and silane
Product forms, and the gas flow ratio range of the silane and ammonia is 3~6；It anneals after graphical to the silicon nitride layer
Processing.By the above method, the corrosion resistance enhancing of silicon nitride (PESIN), silicon nitride layer film layer adjacent thereto (LPSIN layers,
Polysilicon layer or oxide layer) adhesiveness enhancing, also reduce the cross at silicon nitride layer interface after the techniques such as wet etching simultaneously
To undercutting size.
In one of the embodiments, the silicon nitride layer with a thickness of 1 micron~3 microns.
The technique of the annealing is n 2 annealing or laser annealing in one of the embodiments,.
The temperature range of the n 2 annealing is 400~800 DEG C in one of the embodiments,；The n 2 annealing
Duration range is 30 minutes~120 minutes.
The etching solution of the wet etching is buffered oxide etch agent or hydrofluoric acid in one of the embodiments,.
In addition, also providing a kind of preparation method of semiconductor devices, comprising:
Semiconductor substrate is provided；
Using plasma enhances chemical vapor deposition silicon nitride layer on the semiconductor substrate；The nitridation
Silicon layer is deposited using ammonia and silane as reactant, and the gas flow ratio range of the silane and ammonia is 3~6；
Dry etching figure is carried out to the silicon nitride layer；
The silicon nitride layer is made annealing treatment；
Substrate described in wet etching and erodable section is carried out to the silicon nitride layer structure.
In one of the embodiments, the silicon nitride layer with a thickness of 1 micron~3 microns.
The technique of the annealing is n 2 annealing or laser annealing in one of the embodiments,
The temperature range of the n 2 annealing is 400~800 DEG C in one of the embodiments,；The n 2 annealing
Duration range is 30 minutes~120 minutes.
The etching solution of the wet etching is buffered oxide etch agent or hydrofluoric acid in one of the embodiments,.
Detailed description of the invention
Fig. 1 is the method flow diagram that silicon nitride corrosion resistance is improved in one embodiment；
Fig. 2 is the cross-sectional view of silicon nitride layer in one embodiment；
Fig. 3 is the enlarged section in one embodiment after silicon nitride layer annealing；
Fig. 4 is unannealed treated the enlarged section of silicon nitride layer in one embodiment；
Fig. 5 is the enlarged section in another embodiment after silicon nitride layer annealing；
Fig. 6 is the flow chart of the preparation method of semiconductor devices in one embodiment.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
A method of reducing silicon nitride etch rate, comprising:
Step S110: semiconductor substrate is provided.
With reference to Fig. 2, semiconductor substrate 100 is provided, in one embodiment, semiconductor substrate includes the silicon lining stacked gradually
Bottom, oxide layer (low pressure silicon nitride layer LPSIN or polysilicon layer).Certainly, semiconductor substrate may also contain connects in several layers of metal
Semiconductor devices interconnected on line or several electrical property, such as metal-oxide-semiconductor, resistance, logic module, MEMS microphone backboard bottom
Structure etc., for convenience, semiconductor substrate is only with the representative of label 100.
Step S120: using plasma enhances chemical vapour deposition technique deposited silicon nitride on the semiconductor substrate
Layer；The silicon nitride layer is deposited using ammonia and silane as reactant, the gas flow ratio model of the silane and ammonia
Enclose is 3~6.
It is deposited on substrate using the P5000 equipment plasma enhanced chemical vapor deposition (PECVD) of apply and forms nitrogen
SiClx layer 102.Plasma enhanced chemical vapor deposition (PECVD) is to utilize silane gas, ammonia under conditions of low vacuum
Gas and nitrogen generate glow discharge by rf electric field and form plasma, to enhance chemical reaction, to reduce deposition temperature
Degree, can be under the conditions of room temperature be to 400 DEG C, deposited silicon nitride layer 102.Wherein, silicon nitride layer 102 is with ammonia and silane for reaction
Object deposits.
In one embodiment, using plasma enhances chemical vapour deposition technique to pass through when preparing silicon nitride layer
Gas and its flow are as follows: the gas flow ratio of silane and ammonia be 3:1.The gas flow of other gases (such as nitrogen) can
It sets according to actual needs.
In one embodiment, using plasma enhances chemical vapour deposition technique to pass through when preparing silicon nitride layer
Gas and its flow are as follows: the gas flow ratio of silane and ammonia be 6:1.The gas flow of other gases (such as nitrogen) can
It sets according to actual needs.
By a large number of experiments show that, the content of silicon is higher in silicide, and corrosion resistance is better, and the embodiment of the present invention passes through
The ratio of silane and ammonia, the gas flow ratio of silane and ammonia is existed when rationally control gas ions enhance chemical vapor deposition
Control can not only reduce corrosion rate of the silicon nitride layer 102 in acid between 3:1~6:1, improve silicon nitride layer 102
Corrosion resistance in acid, while it is horizontal as boring in acid to reduce the contact interfaces such as silicon nitride layer 102 and polysilicon layer
Erosion.
Using CF4/CHF3Or SF6When being patterned dry etching to silicon nitride layer 102, the thickness of silicon nitride layer 102
D, with reference to Fig. 2, thickness d is about between 1 μm~3 μm.
Step S130: the silicon nitride layer is made annealing treatment.
Silicon nitride layer 102 after graphical dry etching is made annealing treatment.Its annealing way can be n 2 annealing
Or laser annealing.When being annealed using n 2 annealing technique, the range of annealing temperature is 400~800 DEG C, and anneal duration is
30 minutes~120 minutes.
In one embodiment, silicon nitride layer 102 is when carrying out has the dry etching of figure, after the completion of pattern etching,
It is made annealing treatment by the way of n 2 annealing.Before heating, the nitrogen that purity is 99.999% is poured into quartzy tube annealing furnace
Gas is simultaneously kept for a period of time, and silicon nitride layer 102 is placed on quartz boat and is pushed into quartzy furnace, is warming up to 420 under nitrogen atmosphere
DEG C, it is kept for 30 minutes, disconnects heating power supply, silicon nitride layer 102 is in quartzy furnace logical without any outer plus cooling provision condition
Quartzy tube annealing furnace self-radiating is crossed to be cooled to room temperature.
In one embodiment, silicon nitride layer 102 is when carrying out has the wet etching of figure, after the completion of pattern etching,
It is made annealing treatment by the way of n 2 annealing.Before heating, the nitrogen that purity is 99.999% is poured into quartzy tube annealing furnace
Gas is simultaneously kept for a period of time, and silicon nitride layer 102 is placed on quartz boat and is pushed into quartzy furnace, is warming up to 700 under nitrogen atmosphere
DEG C, it is kept for 60 minutes, disconnects heating power supply, silicon nitride layer 102 is in quartzy furnace logical without any outer plus cooling provision condition
Quartzy tube annealing furnace self-radiating is crossed to be cooled to room temperature.In other embodiments, it can select suitably to move back according to actual needs
Fiery temperature and anneal duration, wherein the range of annealing temperature be 400~800 DEG C, anneal duration be 30 minutes~
120 minutes.It in other embodiments, can also be by silicon described in different annealing temperatures, anneal duration and step S120
The gas flow ratio of alkane and ammonia carries out any combination.
In one embodiment, using plasma enhances chemical vapour deposition technique deposited silicon nitride layer on substrate
When 102, by gas and its flow are as follows: the gas flow ratio of silane and ammonia be 5:1.Silicon nitride layer 102 is being had
When the wet etching of figure, after the completion of pattern etching, made annealing treatment by the way of n 2 annealing.Using n 2 annealing
Mode made annealing treatment.Before heating, the nitrogen that purity is 99.999% is poured into quartzy tube annealing furnace and is kept for one section
Silicon nitride layer 102 is placed on quartz boat and is pushed into quartzy furnace, be warming up to 750 DEG C under nitrogen atmosphere, kept for 100 points by the time
Clock, disconnects heating power supply, and silicon nitride layer 102 is being annealed without any outer plus cooling provision condition by quartz ampoule in quartzy furnace
Furnace self-radiating is cooled to room temperature.
Step S140: substrate described in wet etching and erodable section is carried out to the silicon nitride layer.
Wet etching is carried out to the silicon nitride layer after annealing, the etching solution of wet etching is buffer oxide quarter
Lose agent (Buffered Oxide Etchant, BOE) or 49% hydrofluoric acid (HF).When carrying out wet etching to silicon nitride layer 102,
Buffered oxide etch agent or 49% hydrofluoric acid are injected into figure made of dry etching, buffered oxide etch agent or
49% hydrofluoric acid at a slow speed or slight erosion silicon nitride layer, and can fall base by the silicon nitride graphic aperture fast erosion of dry etching
Oxide layer in version 100.Specifically, the duration range for carrying out wet etching to the silicon nitride layer is 45~55 minutes.
The ratio of silane and ammonia is 2:1, the silicon nitride layer formed when traditional gas ions enhance chemical vapor deposition
Buffered oxide etch agent corrosion rate between 89~100A/min.And in embodiments of the present invention, by a large amount of
Test statistics obtain, when gas ions enhance chemical vapor deposition, the ratio of silane and ammonia is 3:1, the silicon nitride of formation
Layer corrodes 50 minutes corrosion rates between 48~58A/min in buffered oxide etch agent；When gas ions enhance chemical gas
When the ratio of silane and ammonia is 4:1 when mutually depositing, the silicon nitride layer formed corrodes 50 minutes in buffered oxide etch agent
Corrosion rate between 32~36A/min；When gas ions enhance chemical vapor deposition, the ratio of silane and ammonia is 5:1
When, the silicon nitride layer formed corrodes 50 minutes corrosion rates between 12~16A/min in buffered oxide etch agent；When
When the ratio of silane and ammonia is 5:1 when gas ions enhance chemical vapor deposition, the silicon nitride layer formed is in buffer oxide
50 minutes corrosion rates of etchant are between 8~10A/min.Wherein, 1A=0.1 nanometers (nm)=10-10m。
As shown in figure 3, the silicon nitride for (being warming up to 420 DEG C under nitrogen atmosphere, kept for 30 minutes) after annealing process processing
Lateral undercutting of the layer 102 at interface after wet-etching technology (interface between silicon nitride layer and polysilicon) is reduced to 1.3um, and
And the silicon nitride layer 102 after annealing is difficult to be sticked out by adhesive tape.And traditional nitridation handled without annealing process
The lateral undercutting at the interface after wet-etching technology of silicon layer 102 is 1.8~2um, with reference to Fig. 4, and without annealing
Silicon nitride layer 102 is easier to be sticked out by adhesive tape after the techniques such as wet etching, poor adhesion.
As shown in figure 5, the silicon nitride for (being warming up to 700 DEG C under nitrogen atmosphere, kept for 60 minutes) after annealing process processing
Lateral undercutting of the layer 102 at interface after wet-etching technology (interface between silicon nitride layer 102 and polysilicon) is reduced to
0.3um, and silicon nitride layer is difficult to be sticked out by adhesive tape after high annealing.
Silicon nitride layer 102 and polysilicon layer (or oxygen can be remarkably reinforced in the silicon nitride layer 102 prepared by the above method
Change layer) etc. film layers adhesiveness, and further decrease the lateral undercutting ruler at the interface after the techniques such as wet etching of silicon nitride layer 102
It is very little.The corrosion resistance enhancing of silicon nitride layer 102, silicon nitride layer 102 film layer (LPSIN, polysilicon layer or oxidation adjacent thereto
Layer) adhesiveness enhancing, reduce the lateral undercutting size at the interface after the techniques such as wet etching of silicon nitride layer 102.
In addition, also providing a kind of preparation method of semiconductor devices, in one embodiment, semiconductor devices is MEMS wheat
Gram wind backboard, the preparation method of MEMS microphone backboard, comprising:
Step S610: semiconductor substrate is provided.
Semiconductor substrate is provided.In one embodiment, semiconductor substrate be the semiconductor substrate of lamination, polysilicon layer,
Low pressure silicon nitride layer.Semiconductor substrate can also be semiconductor substrate, polysilicon layer, and semiconductor substrate can moreover be only semiconductor
Substrate.
Step S620: using plasma enhances chemical vapor deposition silicon nitride layer on the polysilicon layer；
The silicon nitride layer is deposited using ammonia and silane as reactant, and the gas flow ratio range of the silane and ammonia is
3~6.
Using plasma enhances chemical vapor deposition (PECVD) deposition on substrate and forms silicon nitride layer.Plasma
Enhance chemical vapor deposition (PECVD), is, using silane gas, ammonia and nitrogen, to pass through radio frequency electrical under conditions of low vacuum
And generate glow discharge and form plasma,, can be in room temperature to 400 DEG C to reduce depositing temperature to enhance chemical reaction
Under the conditions of, deposited silicon nitride layer.Wherein, silicon nitride layer is deposited using ammonia and silane as reactant.
In one embodiment, using plasma enhances chemical vapour deposition technique to pass through when preparing silicon nitride layer
Gas and its flow are as follows: the gas flow ratio of silane and ammonia be 3:1.The gas flow of other gases (such as nitrogen) can
It sets according to actual needs.
In one embodiment, using plasma enhances chemical vapour deposition technique to pass through when preparing silicon nitride layer
Gas and its flow are as follows: the gas flow ratio of silane and ammonia be 6:1.The gas flow of other gases (such as nitrogen) can
It sets according to actual needs.
By a large number of experiments show that, the content of silicon is higher in silicide, and corrosion resistance is better, and the embodiment of the present invention passes through
The ratio of silane and ammonia, the gas flow ratio of silane and ammonia is existed when rationally control gas ions enhance chemical vapor deposition
Control can not only reduce corrosion rate of the silicon nitride layer in acid between 3:1~6:1, improve silicon nitride layer in acid
Corrosion resistance, while it is horizontal as boring in wet-etching technology to reduce the contact interfaces such as silicon nitride layer and polysilicon layer
Erosion.
Silicon nitride layer thickness about between 1 μm~3 μm.
Step S630: dry etching figure is carried out to the silicon nitride layer.
Using CF4/CHF3Or SF6Dry etching silicon nitride layer, that is, carrying out figure to silicon nitride layer using dry etching
Shapeization processing, needs to use photoresist as exposure mask, and then etch on silicon nitride layer during carrying out dry etching
Through-hole array forms the through-hole in MEMS microphone backboard.
Step S640: the silicon nitride layer is made annealing treatment.
The silicon nitride that targeted graphical is formed after dry etching is made annealing treatment.Its annealing way can be n 2 annealing
Or laser annealing.When being annealed using n 2 annealing technique, the range of annealing temperature is 400~800 DEG C, and anneal duration is
30 minutes~120 minutes.
In one embodiment, it is made annealing treatment by the way of n 2 annealing.Before heating, into quartzy tube annealing furnace
It pours the nitrogen that purity is 99.999% and is kept for a period of time, silicon nitride layer is placed on quartz boat and is pushed into quartzy furnace,
It is warming up to 420 DEG C under nitrogen atmosphere, is kept for 30 minutes, disconnects heating power supply, silicon nitride layer adds in quartzy furnace without any outside
The condition of cooling provision is cooled to room temperature by quartzy tube annealing furnace self-radiating.
In one embodiment, it is made annealing treatment by the way of n 2 annealing.Before heating, into quartzy tube annealing furnace
It pours the nitrogen that purity is 99.999% and is kept for a period of time, silicon nitride layer is placed on quartz boat and is pushed into quartzy furnace,
It is warming up to 700 DEG C under nitrogen atmosphere, is kept for 60 minutes, disconnects heating power supply, silicon nitride layer adds in quartzy furnace without any outside
The condition of cooling provision is cooled to room temperature by quartzy tube annealing furnace self-radiating.It in other embodiments, can be according to reality
Demand selects suitable annealing temperature and anneal duration, wherein the range of annealing temperature is 400~800 DEG C, and annealing continues
Time is 30 minutes~120 minutes.By the annealing of a period of time, silicon nitride layer and polysilicon layer can be remarkably reinforced
The adhesiveness of film layers such as (or oxide layers), and further decrease the lateral undercutting at silicon nitride layer interface after the techniques such as wet etching
Size.
It in other embodiments, can also be by silicon described in different annealing temperatures, anneal duration and step S620
The gas flow ratio of alkane and ammonia carries out any combination.
Step S650: substrate described in wet etching and erodable section is carried out to the silicon nitride layer structure.
Wet etching is carried out to the silicon nitride layer after annealing, the etching solution of wet etching is buffer oxide quarter
Lose agent or 49% hydrofluoric acid.When carrying out wet etching to silicon nitride layer, buffered oxide etch agent or 49% hydrofluoric acid are injected
Into through-hole array, buffered oxide etch agent or 49% hydrofluoric acid at a slow speed or slight erosion silicon nitride layer, and can erode half
Oxide layer on conductor substrate.Specifically, the duration range for carrying out wet etching to the silicon nitride layer is 45~55 minutes.
The ratio of silane and ammonia is 2:1, the silicon nitride layer formed when traditional gas ions enhance chemical vapor deposition
Buffered oxide etch agent corrosion rate between 89~100A/min.And in embodiments of the present invention, by a large amount of
Test statistics obtain, when gas ions enhance chemical vapor deposition, the ratio of silane and ammonia is 3:1, the silicon nitride of formation
Layer corrodes 50 minutes corrosion rates between 48~58A/min in buffered oxide etch agent；When gas ions enhance chemical gas
When the ratio of silane and ammonia is 4:1 when mutually depositing, the silicon nitride layer formed corrodes 50 minutes in buffered oxide etch agent
Corrosion rate between 32~36A/min；When gas ions enhance chemical vapor deposition, the ratio of silane and ammonia is 5:1
When, the silicon nitride layer formed corrodes 50 minutes corrosion rates between 12~16A/min in buffered oxide etch agent；When
When the ratio of silane and ammonia is 5:1 when gas ions enhance chemical vapor deposition, the silicon nitride layer formed is in buffer oxide
50 minutes corrosion rates of etchant are between 8~10A/min.Wherein, 1A=0.1 nanometers (nm)=10-10m。
(be warming up under nitrogen atmosphere 420 DEG C, keep 30 minutes) silicon nitride layer is in wet etching after annealing
The lateral undercutting at interface (interface between silicon nitride layer and polysilicon) is reduced to 1.3um after technique, and by annealing
Silicon nitride layer afterwards is difficult to be sticked out by adhesive tape.And traditional silicon nitride layer handled without annealing process is in wet-etching technology
The lateral undercutting at interface is 1.8~2um afterwards, and is relatively held after the techniques such as wet etching without the silicon nitride layer of annealing
It is easily sticked out by adhesive tape, poor adhesion.
(be warming up under nitrogen atmosphere 700 DEG C, keep 60 minutes) silicon nitride layer is in wet etching after annealing process processing
The lateral undercutting at interface (interface between silicon nitride layer and polysilicon) is reduced to 0.3um after technique, and passes through high annealing
Silicon nitride layer is difficult to be sticked out by adhesive tape afterwards.
The silicon nitride layer prepared by the above method, can be remarkably reinforced silicon nitride layer and polysilicon layer (or oxide layer) etc.
The adhesiveness of film layer, and further decrease the lateral undercutting size at silicon nitride layer interface after the techniques such as wet etching.Silicon nitride
The adherency of the corrosion resistance enhancing of layer, silicon nitride layer film layer (low pressure silicon nitride layer, polysilicon layer or oxide layer) adjacent thereto
Property enhancing, reduce the lateral undercutting size at silicon nitride layer interface after the techniques such as wet etching.
Each technical characteristic of embodiment described above can be combined arbitrarily, for simplicity of description, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, all should be considered as described in this specification.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneously
It cannot therefore be construed as limiting the scope of the patent.It should be pointed out that coming for those of ordinary skill in the art
It says, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to protection of the invention
Range.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.
Claims (10)
1. a kind of method for improving silicon nitride corrosion resistance characterized by comprising
Semiconductor substrate is provided；
Using plasma enhances chemical vapor deposition silicon nitride layer on the semiconductor substrate；The silicon nitride layer
It is to be deposited using ammonia and silane as reactant, the gas flow ratio range of the silane and ammonia is 3~6；
The silicon nitride layer is made annealing treatment；
Substrate described in wet etching and erodable section is carried out to the silicon nitride layer.
2. the method according to claim 1 for improving silicon nitride corrosion resistance, which is characterized in that the thickness of the silicon nitride layer
Degree is 1 micron~3 microns.
3. the method according to claim 1 for improving silicon nitride corrosion resistance, which is characterized in that the work of the annealing
Skill is n 2 annealing or laser annealing.
4. the method according to claim 3 for reducing silicon nitride etch rate, which is characterized in that the temperature of the n 2 annealing
Spending range is 400~800 DEG C；The duration range of the n 2 annealing is 30 minutes~120 minutes.
5. the method according to claim 1 for improving silicon nitride corrosion resistance, which is characterized in that the quarter of the wet etching
Losing solution is buffered oxide etch agent or hydrofluoric acid.
6. a kind of preparation method of semiconductor devices characterized by comprising
Semiconductor substrate is provided；
Using plasma enhances chemical vapor deposition silicon nitride layer on the semiconductor substrate；The silicon nitride layer
It is to be deposited using ammonia and silane as reactant, the gas flow ratio range of the silane and ammonia is 3~6；
Dry etching figure is carried out to the silicon nitride layer；
The silicon nitride layer is made annealing treatment；
Substrate described in wet etching and erodable section is carried out to the silicon nitride layer structure.
7. the preparation method of semiconductor devices according to claim 6, which is characterized in that the silicon nitride layer with a thickness of
1 micron~3 microns.
8. the preparation method of semiconductor devices according to claim 7, which is characterized in that the technique of the annealing is
N 2 annealing or laser annealing.
9. the preparation method of semiconductor devices according to claim 8, which is characterized in that the temperature model of the n 2 annealing
Enclose is 400~800 DEG C；The duration range of the n 2 annealing is 30 minutes~120 minutes.
10. the preparation method of semiconductor devices according to claim 6, which is characterized in that the etching of the wet etching
Solution is buffered oxide etch agent or hydrofluoric acid.
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| CN201710534160.8A CN109216153B (en) | 2017-07-03 | 2017-07-03 | Method for improving corrosion resistance of silicon nitride and preparation method of semiconductor device |
| PCT/CN2018/094333 WO2019007341A1 (en) | 2017-07-03 | 2018-07-03 | Method for improving corrosion resistance of silicon nitride, and method for manufacturing semiconductor device |
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| CN201710534160.8A CN109216153B (en) | 2017-07-03 | 2017-07-03 | Method for improving corrosion resistance of silicon nitride and preparation method of semiconductor device |
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| WO2023279648A1 (en) * | 2021-07-09 | 2023-01-12 | 长鑫存储技术有限公司 | Manufacturing method for semiconductor structure, semiconductor structure, and memory |
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| WO2019007341A1 (en) | 2019-01-10 |
| CN109216153B (en) | 2021-01-05 |
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