CN109148461B

CN109148461B - 3D memory device and method of manufacturing the same

Info

Publication number: CN109148461B
Application number: CN201810940288.9A
Authority: CN
Inventors: 左明光
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2018-08-17
Filing date: 2018-08-17
Publication date: 2021-02-12
Anticipated expiration: 2038-08-17
Also published as: CN109148461A

Abstract

The application discloses a 3D memory device and a method of manufacturing the same. The 3D memory device includes: a semiconductor substrate; the array structure is positioned on the semiconductor substrate and comprises a gate stack structure positioned above the semiconductor substrate and a plurality of conductive channels penetrating through the gate stack structure; and the contact layer comprises a metal silicide formed by deposition and is positioned in the semiconductor substrate, wherein the contact layer is respectively contacted with the active region and the conductive channel which are formed in the semiconductor substrate. The 3D memory device forms a contact layer in the substrate, reduces contact resistance between the conductive channel and an active region in the substrate, and therefore provides good conditions for interconnection of memory cell strings.

Description

3D memory device and method of manufacturing the same

Technical Field

The present invention relates to a memory technology, and more particularly, to a 3D memory device and a method of manufacturing the same.

Background

The increase in memory density of memory devices is closely related to the progress of semiconductor manufacturing processes. As the feature size of semiconductor manufacturing processes becomes smaller, the storage density of memory devices becomes higher. In order to further increase the memory density, a memory device of a three-dimensional structure (i.e., a 3D memory device) has been developed. The 3D memory device includes a plurality of memory cells stacked in a vertical direction, can increase integration in multiples on a unit area of a wafer, and can reduce cost.

Existing 3D memory devices are mainly used as non-volatile flash memories. Two major non-volatile flash memory technologies employ NAND and NOR architectures, respectively. The read speed is slightly slower in the NAND memory device compared to the NOR memory device, but the write speed is fast, the erase operation is simple, and a smaller memory cell can be realized, thereby achieving higher memory density. Therefore, the 3D memory device adopting the NAND structure is widely used.

In the 3D memory device of the NAND structure, the array structure includes a stacked structure, a channel pillar penetrating the stacked structure, and a conductive channel, the stacked structure is used to provide gate conductors of a select transistor and a memory transistor, the channel pillar is used to provide channel layers and gate dielectric stacks of the select transistor and the memory transistor, and the conductive channel is used to realize interconnection of memory cell strings. As the number of layers of the stacked structure increases, the conductive channel cannot be well interconnected with the memory cell string, and the number of layers of the stacked structure is limited accordingly.

It is desirable to further improve the structure of the 3D memory device and the method of manufacturing the same, not only to increase the memory density of the 3D memory device, but also to further increase the yield and reliability.

Disclosure of Invention

It is an object of the present invention to provide an improved 3D memory device and a method of manufacturing the same, in which a contact layer is formed in a substrate, reducing contact resistance between a conductive path and an active region in the substrate, thereby providing good conditions for interconnection of memory cell strings.

According to an aspect of the present invention, there is provided a 3D memory device including: a semiconductor substrate; the array structure is positioned on the semiconductor substrate and comprises a grid laminated structure positioned above the semiconductor substrate and a plurality of conductive channels penetrating through the grid laminated structure; and the contact layer is positioned in the semiconductor substrate, wherein the contact layer comprises a metal silicide formed by deposition and is respectively contacted with the active region formed in the semiconductor substrate and the conductive channel.

Preferably, the conductive via forms an ohmic contact with the active region through the contact layer.

Preferably, the active region includes: the deep well region is formed in the semiconductor substrate; the first high-voltage well region is formed in the deep well region and is opposite in doping type; a second hvw region adjacent to the first hvw region and of opposite doping type; the first doping regions are formed in the first high-voltage well region and are the same in doping type; and a second doped region formed in the second hvw region and having the same doping type.

Preferably, the contact layer includes: a first contact layer located in the first high voltage well region; the second contact layer is positioned in the first doping region; and a third contact layer in the second doped region.

Preferably, the conductive path includes: the first conductive channel is in contact with the first contact layer and is used for forming a plurality of channel columns for source connection; the second conductive channel is in contact with the second contact layer and is used for forming electric connection between the first doped region and an external circuit; and a third conductive path in contact with the third contact layer for forming an electrical connection between the second hvw region and an external circuit.

Preferably, the gate stack structure includes a plurality of gate conductors and a plurality of interlayer insulating layers that are alternately stacked.

Preferably, the method further comprises the following steps: and the grid line gap is used for dividing the grid conductor in the grid laminated structure into a plurality of grid lines.

Preferably, the conductive channel is located in the gate line slit.

Preferably, the material of the contact layer comprises tungsten silicide.

According to another aspect of the present invention, there is provided a method of manufacturing a 3D memory device, including: depositing and forming a contact layer in the semiconductor substrate; and forming an array structure on the semiconductor substrate, the forming of the array structure including forming a gate stack structure over the semiconductor substrate, forming a plurality of conductive channels through the gate stack structure, wherein the contact layer includes a metal silicide and is in contact with an active region formed in the semiconductor substrate and the conductive channels, respectively.

Preferably, the step of forming the active region includes: forming a deep well region in the semiconductor substrate; forming a first high-voltage well region in the deep well region and enabling doping types to be opposite; forming a second hvw region in the semiconductor substrate adjacent to the first hvw region, the second hvw region being of an opposite doping type to the first hvw region; forming a first doped region in the first high-voltage well region, wherein the doping types of the first doped region are the same; and forming a second doped region in the second hvw region and having the same doping type.

Preferably, the step of forming the contact layer includes: patterning the substrate, forming a plurality of openings in the substrate; and depositing the metal silicide in the plurality of openings.

Preferably, the depth of the opening ranges from 0 to 5 μm.

Preferably, the step of forming the contact layer includes: forming a first contact layer in the first high-voltage well region; forming a second contact layer in the first doped region; and forming a third contact layer in the second doped region.

Preferably, the step of forming the conductive channel includes forming a gate line slit for dividing the gate conductive layer in the gate stack structure into a plurality of gate lines, and forming the conductive channel in the gate line slit.

Preferably, the step of forming the conductive path comprises: etching the first array structure to form a conductive channel hole; and depositing material of the conductive via in the conductive via hole, wherein the etching stops when the contact layer is encountered.

Preferably, the material of the contact layer comprises tungsten silicide.

According to the 3D memory device and the method of manufacturing the same of the embodiment of the invention, the contact resistance and the contact capacitance between the conductive channel and the active region in the substrate are reduced by forming the contact layer in the substrate and making the contact layer contact the active region and the conductive channel formed in the semiconductor substrate, respectively.

Different from the prior art, the 3D memory provided by the embodiment of the invention adopts the contact layer to enable the electric channel to form ohmic contact with the active area, so that the area of the ohmic contact formed between the electric channel and the active area is increased, the resistivity between the electric channel and the active area is reduced, and the electrical property and the yield of the 3D memory are improved.

Furthermore, the 3D memory device manufacturing method provided by the embodiment of the invention adopts the contact layer as the etching stop layer, and stops when the etching reaches the contact layer, so that the etching window is enlarged, and the number of etching layers is increased.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.

Fig. 1a and 1b show an equivalent circuit diagram and a structural schematic diagram, respectively, of a memory cell string of a 3D memory device.

Fig. 2 illustrates a perspective view of a 3D memory device according to an embodiment of the present invention.

Fig. 3 illustrates a flowchart of a method of manufacturing a 3D memory device according to an embodiment of the present invention.

Fig. 4 to 8 show cross-sectional views of stages of a method of manufacturing a 3D memory device according to an embodiment of the present invention.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.

It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.

If for the purpose of describing the situation directly on another layer, another area, the expression "directly on … …" or "on … … and adjacent thereto" will be used herein.

In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

In an ideal process, an etching step and a filling step are used to form conductive vias through the array structure. In the filling step, a metal (for example, TI) is deposited and heated to react with the bottom silicon substrate to form TiSix as a contact layer to realize ohmic contact and reduce contact resistance. However, the inventors of the present application have found that, as the number of layers of the stacked structure of the array structure increases, the etching step cannot ensure that the opening of the etching endpoint matches the area of the active region in the substrate, and if the contact between the conductive channel and the substrate is insufficient (e.g., Ti deposition is insufficient or TISIx thickness is insufficient), the conductive performance of the device will be greatly reduced, thereby affecting the product yield. Therefore, it is expected to further improve the contact structure of the conductive channel and the active region, thereby further improving yield and reliability.

The present invention may be embodied in various forms, some examples of which are described below.

Fig. 1a and 1b show a circuit diagram and a structural schematic diagram, respectively, of a memory cell string of a 3D memory device. The case where the memory cell string includes 4 memory cells is shown in this embodiment. It is to be understood that the present invention is not limited thereto, and the number of memory cells in the memory cell string may be any number, for example, 32 or 64.

As shown in fig. 1a, a first terminal of the memory cell string 100 is connected to a Bit Line (BL), and a second terminal is connected to a Source Line (SL). The memory cell string 100 includes a plurality of transistors connected in series between a first terminal and a second terminal, including: a first select transistor Q1, memory transistors M1-M4, and a second select transistor Q2. The Gate of the first select transistor Q1 is connected to a string select line (SGD), and the Gate of the second select transistor Q2 is connected to a Source select line (SGS). The gates of the memory transistors M1 to M4 are connected to corresponding ones of Word lines (Word-Line) WL1 to WL4, respectively.

As shown in fig. 1b, the selection transistors Q1 and Q2 of the memory cell string 100 include gate conductor layers 122 and 123, respectively, and the memory transistors M1 to M4 include gate conductor layers 121, respectively. The gate conductor layers 121, 122, and 123 are in accordance with the stacking order of the transistors in the memory cell string 100, and adjacent gate conductor layers are spaced apart from each other by an interlayer insulating layer, thereby forming a gate stack structure. Further, the memory cell string 100 includes a channel pillar 110. The channel pillar 110 is adjacent to or through the gate stack structure. In the middle portion of the channel pillar 110, a tunnel dielectric layer 112, a charge storage layer 113, and a gate dielectric layer 114 are interposed between the gate conductor layer 121 and the channel layer 111, thereby forming memory transistors M1 through M4. Gate dielectric layers 114 are sandwiched between the gate conductor layers 122 and 123 and the channel layer 111 at both ends of the channel pillar 110, thereby forming selection transistors Q1 and Q2.

In this embodiment, the channel layer 111 is composed of, for example, polysilicon, the tunnel dielectric layer 112 and the gate dielectric layer 114 are respectively composed of an oxide such as silicon oxide, the charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals such as silicon nitride containing particles of a metal or a semiconductor, and the gate conductor layers 121, 122, and 123 are composed of a metal such as tungsten. The channel layer 111 serves to provide channel regions of the control selection transistor and the control transistor, and the doping type of the channel layer 111 is the same as that of the selection transistor and the control transistor. For example, for an N-type select transistor and control transistor, the channel layer 111 may be N-type doped polysilicon.

In this embodiment, the core of channel pillar 110 is channel layer 111, and tunnel dielectric layer 112, charge storage layer 113, and gate dielectric layer 114 form a stacked structure around the core sidewall. In an alternative embodiment, the core of channel pillar 110 is an additional insulating layer, and channel layer 111, tunnel dielectric layer 112, charge storage layer 113, and gate dielectric layer 114 form a stacked structure surrounding the semiconductor layers.

In this embodiment, the selection transistors Q1 and Q2, and the memory transistors M1 to M4 use the common channel layer 111 and gate dielectric layer 114. In the channel pillar 110, the channel layer 111 provides source-drain regions and a channel layer of a plurality of transistors. In an alternative embodiment, the semiconductor layer and the gate dielectric layer of the selection transistors Q1 and Q2 and the semiconductor layer and the gate dielectric layer of the memory transistors M1 to M4, respectively, may be formed in separate steps from each other. In the channel column 110, semiconductor layers of the selection transistors Q1 and Q2 and semiconductor layers of the memory transistors M1 to M4 are electrically connected to each other.

In a write operation, the memory cell string 100 writes data to a selected one of the memory transistors M1 through M4 using FN tunneling. Taking memory transistor M2 as an example, while the source line SL is grounded, the source select line SGS is biased to approximately zero volts such that select transistor Q2 corresponding to source select line SGS is turned off, and the string select line SGD is biased to a high voltage VDD such that select transistor Q1 corresponding to string select line SGD is turned on. Further, the bit line BL2 is grounded, the word line WL2 is biased at the programming voltage VPG, e.g., around 20V, and the remaining word lines are biased at the low voltage VPS 1. Since only the word line voltage of the selected memory transistor M2 is higher than the tunneling voltage, electrons in the channel region of the memory transistor M2 reach the charge storage layer 113 via the tunneling dielectric layer 112, thereby converting data into charges stored in the charge storage layer 113 of the memory transistor M2.

In a read operation, the memory cell string 100 determines the amount of charge in the charge storage layer from the on-state of a selected one of the memory transistors M1 through M4, thereby obtaining data indicative of the amount of charge. Taking the memory transistor M2 as an example, the word line WL2 is biased at the read voltage VRD, and the remaining word lines are biased at the high voltage VPS 2. The on state of the memory transistor M2 is related to its threshold voltage, i.e., the amount of charge in the charge storage layer, so that a data value can be determined according to the on state of the memory transistor M2. The memory transistors M1, M3, and M4 are always in a conductive state, and therefore, the conductive state of the memory cell string 100 depends on the conductive state of the memory transistor M2. The control circuit judges the conductive state of the memory transistor M2 based on the electric signals detected on the bit line BL and the source line SL, thereby obtaining the data stored in the memory transistor M2.

Fig. 2 illustrates a perspective view of a 3D memory device. For clarity, the respective insulating layers in the 3D memory device are not shown in fig. 2.

The 3D memory device shown in this embodiment includes 4 x 4 and 16 memory cell strings 100 in total, each memory cell string 100 including 4 memory cells, thereby forming a memory array of 64 memory cells in total 4 x 4. It is understood that the present invention is not limited thereto and the 3D memory device may include any number of memory cell strings, for example, 1024, and the number of memory cells in each memory cell string may be any number, for example, 32 or 64.

In the 3D memory device, the memory cell strings respectively include the respective channel pillars 110, and the common gate conductor layers 121, 122, and 123. The gate conductor layers 121, 122, and 123 are in accordance with the stacking order of the transistors in the memory cell string 100, and adjacent gate conductor layers are spaced apart from each other by an interlayer insulating layer, thereby forming a gate stack structure 120. The interlayer insulating layer is not shown in the figure.

The internal structure of the channel pillar 110 is shown in fig. 1b and will not be described in detail. In the middle portion of the channel pillar 110, the gate conductor layer 121 forms memory transistors M1 through M4 together with the channel layer 111, the tunnel dielectric layer 112, the charge storage layer 113, and the gate dielectric layer 114 inside the channel pillar 110. At both ends of the channel pillar 110, the gate conductor layers 122 and 123 form the selection transistors Q1 and Q2 together with the channel layer 111 and the gate dielectric layer 114 inside the channel pillar 110.

The channel pillars 110 penetrate through the gate stack structure 120 and are arranged in an array, and a plurality of channel pillars 110 in a same column have first ends commonly connected to a same bit line (i.e., one of the bit lines BL1 to BL 4), second ends commonly connected to the substrate 101, and second ends forming a common source connection through the substrate 100.

The gate conductor 122 of the string selection transistor Q1 is divided into different gate lines by a gate line slit (gate line slit). Gate lines of the plurality of channel pillars 110 of the same row are commonly connected to the same string selection line (i.e., one of string selection lines SGD1 through SGD 4).

The gate conductor layers 121 of the memory transistors M1 and M4 are integrally connected at different layers. If the gate conductor layers 121 of the memory transistors M1 and M4 are split into different gate lines by the gate line slit, the gate lines of the same level reach the interconnect layer 132 via respective conductive paths 131 to be interconnected with each other, and then are connected to the same word line (i.e., one of the word lines WL1 to WL 4) via the conductive path 133.

The gate conductors of the source select transistors Q2 are connected in one piece. If the gate conductor 123 of the source select transistor Q2 is split into different gate lines by the gate line slit, the gate lines reach the interconnect layer 132 via respective conductive channels 131 to be interconnected with each other, and then are connected to the same source select line SGS via the conductive channel 133.

Preferably, CMOS circuitry is included in the substrate semiconductor substrate 101, for example. Conductive vias are used to provide electrical connections between the CMOS circuitry and external circuitry.

Fig. 3 illustrates a flowchart of a method of manufacturing a 3D memory device according to an embodiment of the present invention, and fig. 4 to 8 illustrate cross-sectional views of stages of the method of manufacturing a 3D memory device according to an embodiment of the present invention. The cross-sectional view is taken along line AA in fig. 2, and the method for fabricating the memory structure of the present invention will be described in detail with reference to fig. 3 to 8.

In step S01, a contact layer is deposited in the semiconductor substrate. Specifically, as shown in fig. 4, an active region is formed in a semiconductor substrate 101, including: the deep well region 102, the first hvw region 103, the second hvw region 104, the first doped region 105 and the second doped region 106. The deep well region 102 and the second hvw region 104 are located in the semiconductor substrate 101, the first hvw region 103 is located in the deep well region 102, the first hvw region 103 is adjacent to the second hvw region 104, the first doped region 105 is located in the first hvw region 103, and the second doped region 106 is located in the second hvw region 104, wherein the semiconductor substrate 101, the first hvw region 103, and the first doped region 105 are of a first doping type, the deep well region 102, the second hvw region 104, and the second doped region 106 are of a second doping type, the first doping type is selected from one of N-type doping and P-type doping, the second doping type is selected from the other of N-type doping and P-type doping, in this embodiment, the first doping type is P-type doping, and the second doping type is N-type doping. In the present embodiment, the high voltage P well (first high voltage well region) 103 serves as a common source region of the channel pillar, the high voltage N well (second high voltage well region) 104 serves to pre-charge the common source region, and the P + doped region (first doped region) 105 and the N + doped region (second doped region) 106 serve as contact regions, respectively, to reduce contact resistance.

Further, for example, a photoresist mask is formed on the surface of the semiconductor substrate 101, and then anisotropic etching is performed to form openings 10 in the first hvw region 103, the first doped region 105, and the second doped region 106, respectively, and the depth of the opening 10 is in the range of 0-5 μm, as shown in fig. 5.

In the prior art, holes need to be punched from the array structure to the substrate, in order to ensure the contact area between the conductive channel and the substrate, the depth of the holes in the substrate is relatively deep, and the operation difficulty is high in actual production.

Further, the contact Layer is formed in the opening 10 by, for example, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), including: a plurality of first contact layers 1071 located in the first hvw region 103, a second contact layer 1072 located in the first doped region 105, and a third contact layer 1073 located in the second doped region 106. Next, the semiconductor substrate 101 is polished by a Chemical Mechanical Polishing (CMP) process, as shown in fig. 6.

In the present embodiment, the material of the contact layer includes a metal silicide, such as tungsten silicide, since the depth of the opening 10 is shallow, and the material of the contact layer is directly deposited in the opening 10, so that the contact material is uniformly distributed in the opening 10.

In step S02, an array structure is formed on a semiconductor substrate. Specifically, an insulating stack structure including a plurality of interlayer insulating layers 141 and a plurality of sacrificial layers alternately stacked is formed over the semiconductor substrate 101. In this embodiment, the semiconductor substrate 101 is, for example, a single crystal silicon substrate, the interlayer insulating layer 141 is, for example, composed of silicon oxide, and the sacrificial layer is, for example, composed of silicon nitride. Hereinafter, the sacrificial layer will be replaced with gate conductor layers 121, 122 and 122, etc., to form a stacked structure 120, the gate conductor layers being further connected to word lines, and the insulating stacked structure being covered with an insulating layer 142, as shown in fig. 7.

Further, channel pillars 110 penetrating the insulating stack structure are formed in the array structure and conductive paths are formed in the gate stack structure to form the 3D memory device of the present embodiment, as shown in fig. 8.

In the middle portion of the channel pillar 110, the channel pillar 110 includes a tunneling dielectric layer, a charge storage layer, and a blocking dielectric layer sequentially stacked on the channel layer, and at both ends of the channel pillar 110, the channel pillar 110 includes a blocking dielectric layer stacked on the channel layer. The lower end of the channel pillar 110 is in contact with the high voltage P-well 103 in the semiconductor substrate 101. In the final 3D memory device, the upper end of the channel pillar 110 is connected to a bit line, thereby forming an effective memory cell.

The step of forming the conductive via comprises: the first array structure is etched to form the conductive via holes, and the etching is stopped when the contact layer is encountered, because the contact layer is made of tungsten silicide, which has a high selectivity with respect to oxide and nitride, so that the contact layer can serve as an etch stop layer. Next, a material of the conductive via is deposited in the conductive via hole to form a conductive via in contact with the active region, the conductive via forming an ohmic contact with the active region through the contact layer. The material of the conductive channel comprises titanium nitride or tungsten, or a combination of titanium nitride and tungsten, or a combination of titanium nitride, tungsten and polysilicon. Specifically, when the material of the conductive via includes titanium nitride and tungsten, the material of the core of the conductive via is tungsten, and the titanium nitride surrounds the core and is in contact with the inner surface of the conductive via. When the material of the conductive channel comprises titanium nitride, tungsten and polysilicon, the material of the core of the conductive channel comprises tungsten and polysilicon, the lower portion of the core is polysilicon, the upper portion of the core is tungsten to meet the stress requirement, and the titanium nitride surrounds the core and is in contact with the inner surface of the conductive channel.

In the prior art, the material of the conductive channel needs to be deposited from the array structure to the hole in the substrate, and the material filled in the hole is not uniformly distributed due to process limitation, so that the contact area between the conductive channel and the semiconductor substrate cannot be ensured.

In this embodiment, the conductive via hole may be a gate line slit for dividing the

gate conductor layer

121, 122, 123 in the gate stack structure into a plurality of gate lines, and the conductive via is formed in the gate line slit.

In this embodiment, the conductive path includes: a first conductive channel 151, a second conductive channel 152, and a third conductive channel 153, wherein the first conductive channel 151 contacts the first contact layer 1071 for forming a source connection of the plurality of channel pillars 110, the second conductive channel 152 contacts the second contact layer 1072 for forming an electrical connection between the hvpwell region 103 and an external circuit, and the third conductive channel 153 contacts the third contact layer 1073 for forming an electrical connection between the hvpwell region and an external circuit.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the invention, and these alternatives and modifications are intended to fall within the scope of the invention.

Claims

1. A method of fabricating a 3D memory device, comprising:

depositing a contact layer in the semiconductor substrate; and

forming an array structure on the semiconductor substrate, the forming the array structure including forming a gate stack structure over the semiconductor substrate, a plurality of channel pillars extending through the gate stack structure, and a plurality of conductive vias, a portion of the conductive vias extending through the gate stack structure,

wherein the contact layer comprises a metal silicide and is in contact with an active region formed in the semiconductor substrate and the conductive channel, respectively,

at least a portion of the conductive channel is used to form a source connection for the plurality of channel pillars.

2. The method of claim 1, wherein the conductive via forms an ohmic contact with the active region through the contact layer.

3. The method of claim 1, wherein the step of forming the active region comprises:

forming a deep well region in the semiconductor substrate;

forming a first high-voltage well region in the deep well region and enabling doping types to be opposite;

forming a second hvw region in the semiconductor substrate adjacent to the first hvw region, the second hvw region being of an opposite doping type to the first hvw region;

forming a first doped region in the first high-voltage well region, wherein the doping types of the first doped region are the same; and

and forming a second doping region in the second high-voltage well region, wherein the doping types are the same.

4. The method of claim 1, wherein forming the contact layer comprises:

patterning the substrate, forming a plurality of openings in the substrate; and

depositing the metal silicide in the plurality of openings.

5. The method of claim 4, wherein the depth of the opening ranges from 0-5 μm inclusive, and the depth of the opening does not include 0 μm inclusive.

6. The method of claim 3, wherein forming the contact layer comprises:

forming a first contact layer in the first high-voltage well region;

forming a second contact layer in the first doped region; and

and forming a third contact layer in the second doping region.

7. The method of claim 6, wherein the conductive path comprises:

a first conductive channel in contact with the first contact layer for forming a source connection of the plurality of channel pillars, the first conductive channel penetrating the gate stack structure;

the second conductive channel is in contact with the second contact layer and is used for forming electric connection between the first doped region and an external circuit; and

and a third conductive channel in contact with the third contact layer for forming an electrical connection between the second high-voltage well region and an external circuit.

8. The method of claim 1, wherein the gate stack structure comprises a plurality of gate conductors and a plurality of interlayer insulating layers that are alternately stacked.

9. The method of claim 1, wherein the step of forming a conductive via comprises forming a gate line slit for dividing the gate conductive layer in the gate stack structure into a plurality of gate lines, and forming a conductive via in the gate line slit.

10. The method of claim 1, wherein the step of forming the conductive via comprises:

etching the array structure to form a conductive channel hole; and

depositing material of the conductive via in the conductive via hole,

wherein the etching stops when the contact layer is encountered.

11. The method of any of claims 1-10, wherein the material of the contact layer comprises tungsten silicide.