CN109119481A - A kind of chip and preparation method thereof - Google Patents
A kind of chip and preparation method thereof Download PDFInfo
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- CN109119481A CN109119481A CN201811023167.4A CN201811023167A CN109119481A CN 109119481 A CN109119481 A CN 109119481A CN 201811023167 A CN201811023167 A CN 201811023167A CN 109119481 A CN109119481 A CN 109119481A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/512—Disposition of the gate electrodes, e.g. buried gates
- H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
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- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
本发明涉及半导体技术领域，具体涉及一种芯片及其制作方法，通过在芯片的截止环和划片道上，刻蚀获得一个沟槽，并在沟槽内进行金属填充，通过增加侧面金属的方式，增加了芯片的侧壁散热结构，进一步提升了芯片的散热效率，提高了芯片的工作性能。
The invention relates to the technical field of semiconductors, in particular to a chip and a manufacturing method thereof. A groove is obtained by etching on a cut-off ring and a scribing track of the chip, and metal filling is performed in the groove, and the metal on the side is added by adding metal on the side. , the heat dissipation structure of the sidewall of the chip is increased, the heat dissipation efficiency of the chip is further improved, and the working performance of the chip is improved.
Description
Technical field
The present invention relates to technical field of semiconductors, and in particular to a kind of novel chip and preparation method thereof.
Background technique
Power electronic device just develops towards modularization, intelligentized direction, it is extensive, super large-scale integration go out
Now cause the integrated level of power electronic device higher and higher, the assembling number of all kinds of chips and packing density be also increasingly on substrate
Greatly, it is desirable that the volume for reducing power electronics modules further increases power density, it is desirable to no matter in stable state or transient condition
Under, power module can possess good electric heating property and functional reliability.These result in chip and hold in use
By more and more high temperature or temperature drift.High temperature has a significant impact to the reliability of power electronic product and quick aging, and
Temperature is excessively high and temperature cycles frequently can lead to product premature failure.Therefore, effective heat management becomes power electronic future
A major challenge of development, more stringent requirements are proposed for research and development and progress to encapsulation technology and encapsulating material.
When conventional power Electronic Packaging, power chip is welded direct on substrate, then the substrate for posting chip is connected to
Cooling fin, this packing forms are known as single side encapsulation, and the heat dissipation channel of single side encapsulation is that the heat that chip generates passes through adhesive layer
Substrate is passed to, then passes to cooling fin via another adhesive layer, last cooling fin conducts heat with cross-ventilation or water cooling carries out heat
It distributes, the heat that chip generates at this time radiates only by chip single side, and radiating efficiency is low, influences the workability of chip
Energy.
Summary of the invention
In view of the above circumstances, the present invention to be solved its technical problem the following technical solution is employed to realize.
In a first aspect, the embodiment of the present invention provides a kind of production method of chip, comprising: provide semiconductor substrate；Institute
It states and forms epitaxial layer in semiconductor substrate；Surface forms gate oxide on said epitaxial layer there；In the gate oxide upper surface
Deposit forms polysilicon gate；Body area is formed in the epitaxial layer；Sealing ring is formed in the epitaxial layer；Source is formed in the body area
Area；Cut-off ring is formed in the epitaxial layer；Dielectric layer is formed in the polycrystalline silicon gate surface and the epitaxial layer upper surface；Remote
Groove is formed on the substrate of in vitro area side, the trench depth is greater than the thickness of the cut-off ring, and the groove is located at cut-off
The junction of ring region and dicing lane area；Oxide layer is formed in the trenched side-wall；It performs etching to be formed in the channel bottom and pass through
Wear the deep trench that the epitaxial layer extends in the substrate；Metal filling is carried out in the deep trench；In the dielectric layer
And the epitaxial layer upper surface forms front metal layer, forms the Metal field plate in the cut-off ring upper surface；In the lining
Metal layer on back is formed on bottom bottom.
Further, the groove is located at the cut-off ring region and the junction in the dicing lane area specifically includes, described
A part of shallow trench is located at the cut-off ring region, and another part of the shallow trench is located at the dicing lane area.
Further, it forms oxide layer in the trenched side-wall to specifically include, the groove forms institute by oxidation technology
Oxide layer is stated, dry back is carried out to the oxide layer and carves the oxide layer for removing the channel bottom.
Further, metal filling is carried out in the deep trench to specifically include, by sputtering technology in the deep trench
Interior and stress lesser metal good filled with thermal conductivity.
Further, it is specifically included after metal layer on back is formed on the substrate bottom, the chip is along dicing lane area
It is cut, the metal in the deep trench positioned at the dicing lane area is also completely or partially cut simultaneously.
Second aspect, the embodiment of the present invention also provide a kind of chip, including, semiconductor substrate；Epitaxial layer is formed in described
In semiconductor substrate；Gate oxide is formed in the epitaxial layer upper surface；Polysilicon gate is formed in table on the gate oxide
Face；Body area is formed in the epitaxial layer；Sealing ring is formed in the epitaxial layer；Source region is formed in the body area；End ring,
It is formed in the epitaxial layer；Dielectric layer is formed in the polycrystalline silicon gate surface and the epitaxial layer upper surface；Groove is formed in
Far from body area side on the substrate；The trench depth is greater than the thickness of the cut-off ring, and the groove is located at cut-off ring region
With the junction in dicing lane area；Oxide layer is formed in the trenched side-wall；Deep trench extends to institute through the epitaxial layer
It states in substrate；Metal filling, is formed in the deep trench；Front metal layer is formed in the dielectric layer and the epitaxial layer
Upper surface, Metal field plate are formed in the cut-off ring upper surface；Metal layer on back is formed in the substrate bottom.
Further, a part of the groove is located at the cut-off ring region, and another part of the groove is located at described
Dicing lane area, for making the filling metal in subsequent trench is all or part of to cut along the dicing lane area, the trench depth
Greater than the cut-off ring thickness.
Further, the groove forms after oxide layer and carries out dry back quarter to the oxide layer, removes the trench bottom
The oxide layer in portion only retains the oxide layer of trenched side-wall.
Further, the zanjon groove depth is greater than the epitaxy layer thickness, for increasing metal in the deep trench
Heat dissipation effect.
Further, and stress lesser metal good filled with thermal conductivity in the deep trench.
The technical solution of the embodiment of the present invention has the advantage that by optimizing power device chip structure, in conventional junction
In structure on the outside of the ring, introduce metal heat-conducting, by increasing the thermally conductive mode of side metal, improve the heat dissipation effect of chip
Rate improves the working performance of chip.
Detailed description of the invention
The attached drawing for constituting a part of the invention is used to provide further understanding of the present invention, schematic reality of the invention
It applies example and its explanation is used to explain the present invention, do not constitute improper limitations of the present invention.
In the accompanying drawings:
Fig. 1 is chip manufacture method flow diagram described in the embodiment of the present invention；
Fig. 2 is the structural schematic diagram of substrate and epitaxial layer described in the embodiment of the present invention；
Fig. 3 is the structural schematic diagram of polysilicon gate and body area described in the embodiment of the present invention；
Fig. 4 is the structural schematic diagram of source region and sealing ring described in the embodiment of the present invention；
Fig. 5 is the structural schematic diagram of dielectric layer described in the embodiment of the present invention；
Fig. 6 is the structural schematic diagram of groove and oxide layer described in the embodiment of the present invention；
Fig. 7 is the structural schematic diagram of deep trench described in the embodiment of the present invention；
Fig. 8 is the structural schematic diagram of front metal layer described in the embodiment of the present invention；
Fig. 9 is the structural schematic diagram of metal layer on back described in the embodiment of the present invention.
Specific embodiment
It is clear in order to be more clear the purpose of the present invention, technical solution and advantageous effects, below in conjunction with this hair
Attached drawing in bright embodiment, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described
Embodiment is only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field
Those of ordinary skill's every other embodiment obtained without making creative work, belongs to protection of the present invention
Range.
In the description of the present invention, it should be noted that term " center ", "upper", "lower", "left", "right", "vertical",
The orientation or positional relationship of the instructions such as "horizontal", "inner", "outside" is to be based on the orientation or positional relationship shown in the drawings, or be somebody's turn to do
Invention product using when the orientation or positional relationship usually put, be merely for convenience of description of the present invention and simplification of the description, without
It is that the device of indication or suggestion meaning or element must have a particular orientation, be constructed and operated in a specific orientation, therefore not
It can be interpreted as limitation of the present invention.In addition, term " first ", " second ", " third " etc. are only used for distinguishing description, and cannot manage
Solution is indication or suggestion relative importance.
Usually using two complicated manufacture craft manufacturing semiconductor devices: front end manufacture and back-end manufacturing.Front end manufacture
It include that multiple small pieces are formed on the surface of semiconductor wafer.Each small pieces include active and passive electronic member on the wafer
Part, described active and passive electronic components are electrically connected to form functional circuitry, active electron component, such as transistor and two poles
Pipe has the ability of control electric current flowing.Passive electronic components, such as capacitor, inductor, resistor and transformer.It generates
Relationship between voltage and current necessary to execution circuit function.
By a series of processing step, passive and active element, the processing step are formed on the surface of semiconductor
Including doping, deposition, photoetching, etching and planarization.Doping passes through the technology of such as ion implanting or thermal diffusion, adds impurities to
In semiconductor material.Doping process changes the conductivity of the semiconductor material in active device, and semiconductor material is converted to absolutely
Edge body, conductor, or dynamically change in response to electric field or base current the conductivity of semiconductor material.
Active and passive element is formed by the layer of the material with different electrical properties.It can be by partly by deposited material
A variety of deposition techniques that the type of material is determined form these layers.For example, film deposition may include chemical vapor deposition, physics
Vapor deposition, electrolysis plating and plated by electroless plating technique.Usually pattern each layer with formed active component, passive element or
The part of electrical connection between element.
Below in conjunction with Fig. 1-Fig. 9, the production method for providing a kind of transistor to the embodiment of the present invention is described in detail, should
Method includes:
S01: semiconductor substrate 1 is provided；
S02: epitaxial layer 2 is formed in the semiconductor substrate 1；
S03: surface forms gate oxide 3 on the epitaxial layer 2；
S04: it deposits to form polysilicon gate 4 in 3 layers of upper surface of the gate oxidation；
S05: body area 5 is formed in the epitaxial layer 2；
S06: sealing ring 6 is formed in the epitaxial layer 2；
S07: source region 7 is formed in the body area 5；
S08: cut-off ring 8 is formed in the epitaxial layer 2；
S09: dielectric layer 9 is formed on 4 surface of polysilicon gate and 2 upper surface of the epitaxial layer；
S10: forming groove 10 on the substrate 1 far from 5 side of body area, and 10 depth of groove is greater than the cut-off ring 2
Thickness, the groove 10 be located at cut-off ring region and dicing lane area junction；
S11: oxide layer 11 is formed in 10 side wall of groove；
S12: the depth to be formed and be extended in the substrate 1 through the epitaxial layer 2 is performed etching in 10 bottom of groove
Groove 12；
S13: metal filling 13 is carried out in the deep trench 12；
S14: front metal layer 14, the table on the cut-off ring are formed in the dielectric layer 9 and 2 upper surface of the epitaxial layer
Face forms the Metal field plate 15；
S15: metal layer on back 16 is formed in the substrate bottom.
The technical solution of the embodiment of the present invention by optimization power device chip structure, in traditional architectures by outside ring
Side introduces metal heat-conducting, by increasing the thermally conductive mode of side metal, improves the radiating efficiency of chip, improves chip
Working performance.
With reference to the accompanying drawings, the specific method of the above-mentioned formation transistor is elaborated.
As shown in Fig. 2, step S01: semiconductor substrate 1 is provided, specifically, the substrate 1 adulterates the first conduction type
The ion of ion or the second conduction type, first conduction type are p-type doping and one of n-type doping, described the
Two conduction types are p-type doping and the another kind in n-type doping.
Special to illustrate herein for convenience of description: first conduction type can be n-type doping, so that described second is conductive
Type is p-type doping；First conduction type can also adulterate for p-type, so that second conduction type is n-type doping.
In next embodiment, using first conduction type as n-type doping, second conduction type is doped to for p-type
Example is described, but is defined not to this.
Specifically, P type substrate and p-type extension belong to P-type semiconductor, and N-type substrate and N-type extension belong to N-type and partly lead
Body.The P-type semiconductor is the silicon wafer for adulterating triad, such as any group of boron element or phosphide element or aluminium element or three
It closes, the N-type semiconductor be any combination of silicon wafer of doping pentad, such as P elements or arsenic element or both.
The substrate 1 is the carrier in integrated circuit, and the substrate 1 plays the role of support, and the substrate 1 also assists in institute
State the work of integrated circuit.The substrate 1 can be silicon substrate, or Sapphire Substrate, it might even be possible to it is silicon Chu substrate,
Preferably, the substrate 1 is silicon substrate, and the especially described substrate 1 is monocrystalline substrate, this is because silicon substrate material and wherein
Single crystal silicon material have the characteristics that low cost, large scale, conductive, avoid edge effect, yield can be increased substantially.
In one embodiment of the invention, the substrate 1 is the semiconductor of the first conduction type, and the substrate 1 can be in monocrystalline
Any combination that P elements or arsenic element or both are adulterated in silicon is made.
As shown in Fig. 2, step S02: epitaxial layer 2 is formed in the semiconductor substrate 1, specifically, the substrate 1 is enterprising
The n-type doping of the first conduction type of row forms the epitaxial layer 2, and the doping concentration and thickness of epitaxial layer 2 not only determine device
Breakdown voltage, also affect the conducting resistance of device, high breakdown voltage requires the thick epitaxial layer being lightly doped, and low leads
The resistance that is powered then requires the epitaxial layer of thin heavy doping, it is therefore necessary to optimal extension parameter is selected, so that it is same to meet breakdown voltage
When conducting resistance it is smaller, in one embodiment of the invention, 2 doping concentration of epitaxial layer be less than the semiconductor doping
Concentration so that epitaxial layer has a higher breakdown voltage, and then protects device.
As shown in Fig. 2, step S03: surface forms gate oxide 3 on the epitaxial layer 2；Wherein, method for oxidation includes
Dry-oxygen oxidation, steam oxidation, mixes oxychloride, Oxidation Process By Hydrogen Oxygen Synthesis etc. at wet-oxygen oxidation, in the present embodiment preferred dry oxygen oxygen
Change, oxidizing temperature is 800 DEG C -1000 DEG C in oxidation process, is passed directly into oxygen and is aoxidized, is generated by dry-oxygen oxidation
The advantages that gate oxide compact structure, uniformity and reproducible is strong to impurity screening ability, good with the adhesion of photoresist.
As shown in Fig. 2, step S04: depositing to form polysilicon gate 4 in 3 upper surface of gate oxide；Its depositional mode packet
Aumospheric pressure cvd method, Low Pressure Chemical Vapor Deposition, plasma auxiliary chemical vapor deposition method etc. are included, in this implementation
In mode, it is therefore preferable to which Low Pressure Chemical Vapor Deposition, the polysilicon purity is high of doping, uniformity are strong.
As shown in figure 3, step S05: surface forms body area 5 on the epitaxial layer 2；Specifically, the body area 5 is in extension
2 upper surface photoetching of layer, etching and ion implanting, carrying out coating photoresist to 2 upper surface of epitaxial layer, then chemical wet etching goes out wait infuse
The body area for entering ion carries out ion implantation technology to the epitaxial layer 2 using the photoresist as masking film, and the ion of injection is logical
It is often boron ion, the body area 5 is for avoiding latch-up.
As shown in figure 3, step S06: forming sealing ring 6 in the epitaxial layer 2；Specifically, in the upper table of the epitaxial layer 2
For wheat flour for mask material, the mask material is specially photoresist, and photoresist forms photoresist in the upper surface of the epitaxial layer
Layer forms sealing ring 6 by injection ion on the photoresist layer.
As shown in figure 4, step S07: forming source region 7 in the body area 5；Specifically, in the upper surface system of the epitaxial layer 2
Standby mask material, the mask material are specially photoresist, and photoresist forms photoresist layer in the upper surface of the epitaxial layer 2,
Source region 7 is formed by the heavy doping ion of the first conduction type of injection on the photoresist layer, the source region 7 is formed in described
5 upper surface of body area.
As shown in figure 4, step S08: forming cut-off ring 8 in the epitaxial layer 2；Specifically, surface on the epitaxial layer 2
Mask material is prepared, the mask material is specially photoresist, and photoresist forms photoresist layer in the upper surface of the epitaxial layer,
It is sheltered with doping window of the photoresist layer to cut-off ring, ion implanting is carried out to the doping window of cut-off ring and forms institute
Cut-off ring 8 is stated, the cut-off ring 8 is used to be truncated the surface conduction channel of active area Yu dicing lane area, avoids the occurrence of groove electric leakage
The case where.
As shown in figure 5, step S09: forming dielectric layer 9 on 4 surface of polysilicon gate and 2 upper surface of the epitaxial layer；
Specifically, the polycrystalline silicon gate surface and 2 upper surface of the epitaxial layer are by using sputtering or thermal oxidation method or chemical vapor deposition
Product technique or in which several formation dielectric layer 9, the dielectric layer 9 usually formed by the preferable material of insulating properties, for example,
The material of the dielectric layer 9 is silicon oxide or silicon nitride or silicon oxynitride, for protecting device not contaminated and having isolation
Effect, in one embodiment, by the method for sputtering, surface forms the dielectric layer 9 of silica on the epitaxial layer 2.
As shown in fig. 6, step S10: forming groove 10 on the substrate 1 far from 5 side of body area, 10 depth of groove is big
In the thickness of the cut-off ring 8, the groove 10 is located at the junction of cut-off ring region and dicing lane area；Specifically, the groove
10 are located at the junction of the cut-off ring region and the dicing lane area, and the region that ring 8 is ended on the substrate 1 is cut-off ring region,
A part of the groove 101 is located in the cut-off ring region, and one of the groove is located in the dicing lane area, so that after
When continuous chip is cut along the dicing lane area, metal in 10 groove is also all or part of simultaneously to be cut.The ditch
The depth of slot 10 is greater than the thickness of the cut-off ring region, and depth is greater than the cut-off when generating oxide layer for subsequent trench side wall
The thickness of ring region.Wherein, the method for etching groove includes dry etching and wet etching, it is preferred that the method for the etching used
For dry etching, dry etching includes photoablation, gaseous corrosion, plasma etching etc., and dry etching easily realize automation,
Treatment process is not introduced into pollution, cleannes height.In one embodiment of the invention, the lithographic method used is dry etching,
Specifically, preparing mask material in the upper surface of the epitaxial layer 2, the mask material is specially photoresist, and photoresist is in institute
The upper surface for stating epitaxial layer forms photoresist layer, is formed on the epitaxial layer 2 on the photoresist layer by dry etching
The groove on surface removes the photoresist layer.
As shown in fig. 6, step S11: forming oxide layer 11 in 10 side wall of groove；Specifically, the oxide layer 11 is thick
Degree is determined that 11 thickness of oxide layer is generally 300A-600A (Angstrom, angstrom), wherein method for oxidation by the cut-in voltage of chip
Including dry-oxygen oxidation, wet-oxygen oxidation, steam oxidation, mix oxychloride, Oxidation Process By Hydrogen Oxygen Synthesis etc., in the present embodiment preferred dry oxygen
Oxidation, oxidizing temperature are 800 DEG C -1000 DEG C in oxidation process, are passed directly into oxygen and are aoxidized, are generated by dry-oxygen oxidation
Oxide layer compact structure, uniformity and reproducible is strong to impurity screening ability, it is good with the adhesion of photoresist the advantages that,
In one embodiment of the invention, using dry-oxygen oxidation, wall and bottom generation have oxide layer in the groove, generate oxidation
After layer, dry back quarter is carried out to the oxide layer, removes the oxide layer of the channel bottom, only retaining is the trenched side-wall
Oxide layer 11.
As shown in fig. 7, step S12: performing etching to be formed in 10 bottom of groove and extend to institute through the epitaxial layer 2
State the deep trench 12 in substrate；Specifically, performing etching shape to the groove 10 after 10 side wall of groove generates oxide layer 11
At the deep trench 12, the deep trench 12 extends in the substrate 1 through the epitaxial layer 2, for high tension apparatus,
The epitaxial layer 2 is applied not only to tolerance high pressure, and the epitaxial layer 2 is also the main hot zone of chip, the deep trench 12
Depth be greater than 2 depth of epitaxial layer so that the metal of subsequent filling preferably radiates to chip.Etch deep trench
Technique is not specifically limited, such as above-mentioned dry etching and wet-etching technology all can, but the depth of the deep trench 12 need it is big
In the thickness of the epitaxial layer 2.
As shown in figure 8, step S13: carrying out metal filling 13 in the deep trench 12；Specifically, passing through depositing technics
Deposit generates the good metal of thermal conductivity in the deep trench, and the good metal of thermal conductivity makes the heat dissipation effect of chip more
Good, the metal needs will meet the lesser condition of its stress under external force simultaneously, prevent the metal of subsequent deep trench from being cut
Its stress larger damage chip when cutting.It is described since the deep trench is located at the junction of the cut-off ring region and dicing lane area
When subsequent chip is cut along the dicing lane area, the metal of the deep trench is partly or entirely cut simultaneously, is used for subsequent core
Side wall radiator structure when piece encapsulates.
As shown in figure 8, step S14: front metal layer 14 is formed in the dielectric layer 9 and 2 upper surface of the epitaxial layer,
8 upper surface of cut-off ring forms the Metal field plate 15；Specifically, 2 upper surface of epitaxial layer is formed by sputtering method
The front metal layer 14, the front metal layer 14 is source metal, by the oxide layer and the cut-off ring
Surface covers one layer of metal and obtains side end structure, so that surface field strength becomes smaller, to improve the resistance to pressure of chip.
As shown in figure 9, step S15: forming metal layer on back 16 in 1 bottom of substrate；Specifically, under the substrate 1
Surface forms the metal layer on back 16 by the method evaporated, and the metal layer on back 16 is the drain metal layer.
The production method of a kind of chip provided in an embodiment of the present invention, by optimizing power device chip structure, in tradition
In structure on the outside of the ring, introduce metal heat-conducting, by increasing the thermally conductive mode of side metal, improve the heat dissipation effect of chip
Rate improves the working performance of chip.
The embodiment of the present invention provides a kind of chip, comprising:
Semiconductor substrate 1；
Epitaxial layer 2 is formed in the semiconductor substrate 1；
Gate oxide 3 is formed in 2 upper surface of epitaxial layer；
Polysilicon gate 4 is formed in 3 upper surface of gate oxide；
Body area 5 is formed in the epitaxial layer 2；
Sealing ring 6 is formed in the epitaxial layer 2；
Source region 7 is formed in the body area 5；
End ring 8, is formed in the epitaxial layer 2；
Dielectric layer 9 is formed in 2 upper surface of 4 surface of polysilicon gate and the epitaxial layer；
Groove 10 is formed on the substrate 1 far from 5 side of body area；10 depth of groove is greater than the cut-off ring 8
Thickness, the groove 10 are located at the junction of cut-off ring region and dicing lane area；
Oxide layer 11 is formed in 10 side wall of groove；
Deep trench 12 extends in the substrate 1 through the epitaxial layer 2；
Metal filling 13, is formed in the deep trench 12；
Front metal layer 14, is formed in 2 upper surface of the dielectric layer 9 and the epitaxial layer, and Metal field plate 15 is formed in institute
State cut-off 8 upper surface of ring；
Metal layer on back 16 is formed in 1 bottom of substrate.
Further, a part of the groove 10 is located at the cut-off ring region, and another part of the groove is located at institute
Dicing lane area is stated, for making the filling metal in subsequent trench is all or part of to cut along the dicing lane area, the ditch groove depth
Degree is greater than the cut-off ring region thickness.
Further, the groove 10 forms after oxide layer 11 and carries out dry back quarter to the oxide layer, removes the ditch
The oxide layer of trench bottom only retains the oxide layer of trenched side-wall.
Further, 12 depth of deep trench is greater than 2 thickness of epitaxial layer, for increasing metal in the deep trench
Heat dissipation effect.
Further, and stress lesser metal good filled with thermal conductivity in the deep trench 12.
The technical scheme of the present invention has been explained in detail above with reference to the attached drawings, and the present invention passes through optimization power device chip knot
Structure, in traditional architectures on the outside of the ring, introduce metal heat-conducting, by increasing the thermally conductive mode of side metal, improve core
The radiating efficiency of piece improves the working performance of chip.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all in essence of the invention
Within mind and principle, any modification, equivalent substitution, improvement and etc. done be should be included within the scope of the present invention.
Claims (10)
1. a kind of production method of chip, which is characterized in that the described method includes:
Semiconductor substrate is provided；
Epitaxial layer is formed on the semiconductor substrate；
Surface forms gate oxide on said epitaxial layer there；
It deposits to form polysilicon gate in the gate oxide upper surface；
Body area is formed in the epitaxial layer；
Sealing ring is formed in the epitaxial layer；
Source region is formed in the body area；
Cut-off ring is formed in the epitaxial layer；
Dielectric layer is formed in the polycrystalline silicon gate surface and the epitaxial layer upper surface；
Groove is formed on the substrate far from body area side, the trench depth is greater than the thickness of the cut-off ring, the groove
Positioned at the junction of cut-off ring region and dicing lane area；
Oxide layer is formed in the trenched side-wall；
The deep trench to be formed and be extended in the substrate through the epitaxial layer is performed etching in the channel bottom；
Metal filling is carried out in the deep trench；
Front metal layer is formed in the dielectric layer and the epitaxial layer upper surface, forms the gold in the cut-off ring upper surface
Belong to field plate；
Metal layer on back is formed in the substrate bottom.
2. manufacturing method according to claim 1, which is characterized in that the groove is located at the cut-off ring region and described stroke
The junction in film channel area specifically includes, and a part of the groove is located at the cut-off ring region, another part position of the groove
In the dicing lane area.
3. manufacturing method according to claim 1, which is characterized in that form oxide layer in the trenched side-wall and specifically wrap
It includes, the groove forms the oxide layer by oxidation technology, carries out dry back to the oxide layer and carves for removing the ditch
The oxide layer of trench bottom.
4. manufacturing method according to claim 1, which is characterized in that carry out the specific packet of metal filling in the deep trench
It includes, by sputtering technology filled with thermal conductivity is good and the lesser metal of stress in the deep trench.
5. manufacturing method according to claim 1, which is characterized in that after metal layer on back is formed on the substrate bottom
It specifically includes, the chip is cut along the dicing lane area, and the metal in the dicing lane area is located in the deep trench
It is completely or partially cut simultaneously.
6. a kind of chip characterized by comprising
Semiconductor substrate；
Epitaxial layer is formed in the semiconductor substrate；
Gate oxide is formed in the epitaxial layer upper surface；
Polysilicon gate is formed in the gate oxide upper surface；
Body area is formed in the epitaxial layer；
Sealing ring is formed in the epitaxial layer；
Source region is formed in the body area；
End ring, is formed in the epitaxial layer；
Dielectric layer is formed in the polycrystalline silicon gate surface and the epitaxial layer upper surface；
Groove is formed on the substrate far from body area side；The trench depth is greater than the thickness of the cut-off ring, the ditch
Slot position is in the junction of cut-off ring region and dicing lane area；
Oxide layer is formed in the trenched side-wall；
Deep trench extends in the substrate through the epitaxial layer；
Metal filling, is formed in the deep trench；
Front metal layer is formed in the dielectric layer and the epitaxial layer upper surface, Metal field plate, is formed on the cut-off ring
Surface；
Metal layer on back is formed in the substrate bottom.
7. chip according to claim 6, which is characterized in that a part of the groove is located at the cut-off ring region, institute
The another part for stating groove is located at the dicing lane area, for keeping the filling metal in subsequent trench all or part of along described stroke
The cutting of film channel area, the trench depth are greater than the cut-off ring region thickness.
8. chip according to claim 6, which is characterized in that the groove carries out the oxide layer after forming oxide layer
Dry back is carved, and the oxide layer of the channel bottom is removed, and only retains the oxide layer of trenched side-wall.
9. chip according to claim 6, which is characterized in that the zanjon groove depth is greater than the epitaxy layer thickness, uses
In the heat dissipation effect for increasing metal in the deep trench.
10. chip according to claim 6, which is characterized in that in the deep trench and stress good filled with thermal conductivity compared with
Small metal.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110690160A (en) * | 2019-10-16 | 2020-01-14 | 上海先方半导体有限公司 | Chip protection structure and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5241211A (en) * | 1989-12-20 | 1993-08-31 | Nec Corporation | Semiconductor device |
| CN106571394A (en) * | 2016-11-01 | 2017-04-19 | 杭州士兰微电子股份有限公司 | Power device and manufacturing method thereof |
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2018
- 2018-09-04 CN CN201811023167.4A patent/CN109119481A/en not_active Withdrawn
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5241211A (en) * | 1989-12-20 | 1993-08-31 | Nec Corporation | Semiconductor device |
| CN106571394A (en) * | 2016-11-01 | 2017-04-19 | 杭州士兰微电子股份有限公司 | Power device and manufacturing method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110690160A (en) * | 2019-10-16 | 2020-01-14 | 上海先方半导体有限公司 | Chip protection structure and manufacturing method thereof |
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