CN109088309A - A kind of frequency vertical cavity surface emitting lasers chip and preparation method thereof - Google Patents
A kind of frequency vertical cavity surface emitting lasers chip and preparation method thereof Download PDFInfo
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- CN109088309A CN109088309A CN201811205140.7A CN201811205140A CN109088309A CN 109088309 A CN109088309 A CN 109088309A CN 201811205140 A CN201811205140 A CN 201811205140A CN 109088309 A CN109088309 A CN 109088309A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 80
- 238000002347 injection Methods 0.000 claims abstract description 56
- 239000007924 injection Substances 0.000 claims abstract description 56
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 claims description 9
- MDPILPRLPQYEEN-UHFFFAOYSA-N aluminium arsenide Chemical compound [As]#[Al] MDPILPRLPQYEEN-UHFFFAOYSA-N 0.000 claims description 9
- 239000004744 fabric Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 9
- 238000000034 method Methods 0.000 description 7
- 239000000243 solution Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 238000002310 reflectometry Methods 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 239000002305 electric material Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
- H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
- H01S5/18361—Structure of the reflectors, e.g. hybrid mirrors
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- Optics & Photonics (AREA)
- Semiconductor Lasers (AREA)
Abstract
The embodiment of the present application provides a kind of frequency vertical cavity surface emitting lasers chip and preparation method thereof, wherein, the frequency vertical cavity surface emitting lasers chip includes: substrate, the N-type layer being sequentially formed on substrate, luminescent layer, current-limiting layer, P-type layer and P-type electrode layer, and substrate back is formed with N-type electrode layer；N-type layer and P-type layer include multilayer reflective layers；The fringe region of luminescent layer, current-limiting layer and P-type layer exposure N-type layer；The fringe region of the N-type layer exposure substrate；N-type layer edge is provided with the conductive layer of the multilayer reflective layers of connection N-type layer；Current-limiting layer includes current injection area domain and insulating regions；P-type layer includes exposed region corresponding with insulating regions, the reflecting layer of the bottom in exposed region exposure P-type layer；The covering of P-type electrode layer includes the P-type layer of exposed region, and P-type electrode layer includes light hole corresponding with current injection area domain.The embodiment of the present application improves the high frequency sensibility of vertical cavity surface emitting laser chip.
Description
Technical field
This application involves technical field of semiconductors, in particular to a kind of frequency vertical cavity surface emitting lasers chip
And preparation method thereof.
Background technique
VCSEL, complete entitled vertical cavity surface emitting laser (Vertical Cavity Surface Emitting
Laser), developed based on gallium arsenide semiconductor material, being different from LED (light emitting diode) and LD, (Laser Diode swashs
Optical diode) etc. other light sources, have small in size, round output facula, single longitudinal mode output, threshold current it is small, cheap, easy
The advantages that being integrated into large area array is widely applied and the fields such as optic communication, light network, optical storage.
In VCSEL chip, in order to increase the light emission rate of luminescent layer, N-type layer and P-type layer in chip are typically chosen distribution
Bragg mirror structure, distributed bragg reflector mirror structure include multiple reflecting layer, when injecting high-frequency current in chip,
Capacity effect can be generated between multiple reflecting layer in Bragg mirror structure, cause the high frequency sensibility of VCSEL chip compared with
Difference.
To sum up, for VCSEL chip in logical high-frequency current, high frequency sensibility is poor in the prior art.
Summary of the invention
In view of this, the application's has been designed to provide a kind of frequency vertical cavity surface emitting lasers chip and its preparation
Method, to improve the high frequency sensibility of vertical cavity surface emitting laser chip.
In a first aspect, the embodiment of the present application provides a kind of frequency vertical cavity surface emitting lasers chip, comprising:
Substrate, the N-type layer being sequentially formed on the substrate, luminescent layer, current-limiting layer, P-type layer and P-type electrode layer,
The substrate back is formed with N-type electrode layer；The N-type layer and the P-type layer include multilayer reflective layers；The luminescent layer,
The fringe region of the current-limiting layer and the P-type layer exposure N-type layer；The edge of the N-type layer exposure substrate
Region；
The N-type layer edge is provided with the conductive layer for being connected to the multilayer reflective layers of the N-type layer；
The current-limiting layer includes current injection area domain and insulating regions；
The P-type layer includes exposed region corresponding with the insulating regions, in the exposed region exposure P-type layer
Bottom reflecting layer；
The P-type electrode layer covering includes the P-type layer of the exposed region, and the P-type electrode layer includes and the electric current
The corresponding light hole of injection zone.
With reference to first aspect, the embodiment of the present application provides the first possible embodiment of first aspect, the p-type
Layer further includes the ohmic contact layer being set on multilayer reflective layers.
With reference to first aspect, the embodiment of the present application provides second of possible embodiment of first aspect, the p-type
The multilayer reflective layers of layer constitute p-type distributed bragg reflector mirror structure, and the multilayer reflective layers of the N-type layer constitute N-type distribution
Formula Bragg mirror structure.
The possible embodiment of second with reference to first aspect, the embodiment of the present application provide the third of first aspect
Possible embodiment, the p-type distributed bragg reflector mirror structure include the alternate aluminium arsenide layer of multilayer and aluminum gallium arsenide
Layer；
The N-type distributed bragg reflector mirror structure includes the alternate aluminium arsenide layer of multilayer and aluminum gallium arsenide layer.
With reference to first aspect, the embodiment of the present application provides the 4th kind of possible embodiment of first aspect, the electricity
Stream injection zone is circular hole region, and the diameter range in the circular hole region is 5-15um.
Second aspect, the embodiment of the present application provide a kind of frequency vertical cavity surface emitting lasers chip, comprising:
Substrate, the N-type layer being sequentially formed on the substrate, luminescent layer, current-limiting layer, P-type layer and P-type electrode layer,
The substrate back is formed with N-type electrode layer；The N-type layer and the P-type layer include multilayer reflective layers；
The current-limiting layer includes current injection area domain and insulating regions；
The P-type layer includes exposed region corresponding with the insulating regions, in the exposed region exposure P-type layer
Bottom reflecting layer；
The P-type electrode layer covering includes the P-type layer of the exposed region, and the P-type electrode layer includes and the electric current
The corresponding light hole of injection zone.
The third aspect, the embodiment of the present application provide a kind of frequency vertical cavity surface emitting lasers chip, comprising:
Substrate, the N-type layer being sequentially formed on the substrate, luminescent layer, current-limiting layer, P-type layer and P-type electrode layer,
The substrate back is formed with N-type electrode layer；The N-type layer and the P-type layer include multilayer reflective layers；The luminescent layer,
The fringe region of the current-limiting layer and the P-type layer exposure N-type layer；The side of the exposure of the N-type layer substrate
Edge region；
The N-type layer edge is provided with the conductive layer for being connected to the multilayer reflective layers of the N-type layer；
The current-limiting layer includes current injection area domain and insulating regions；
The P-type electrode layer includes light hole corresponding with the current injection area domain.
Fourth aspect, the embodiment of the present application provide a kind of preparation method of frequency vertical cavity surface emitting lasers chip,
It is used to prepare any frequency vertical Cavity surface hair of the first aspect into the 4th kind of possible embodiment of first aspect
Penetrate chip of laser, comprising:
N-type layer, luminescent layer, current-limiting layer and P-type layer are sequentially formed on substrate, and the N-type layer and the P-type layer are equal
Including multilayer reflective layers, the current-limiting layer includes current injection area domain and insulating regions；
Remove the fringe region of the P-type layer, the current-limiting layer and the luminescent layer, the side of the exposure N-type layer
Edge region；And the fringe region of the removal N-type layer, the fringe region of the exposure substrate；
The P-type layer is etched, so that the P-type layer forms exposed region corresponding with the insulating regions, the exposure
The reflecting layer of bottom in the region exposure P-type layer；
P-type electrode layer is formed in the P-type layer, so that P-type electrode layer covering includes the p-type of the exposed region
Layer；
The P-type electrode layer is etched, so that the P-type electrode layer forms light out corresponding with the current injection area domain
Hole；
The conductive layer for being connected to the multilayer reflective layers of the N-type layer is formed in the fringe region of the N-type layer；
N-type electrode layer is formed in the substrate back.
5th aspect, the embodiment of the present application provide a kind of preparation method of frequency vertical cavity surface emitting lasers chip,
It is used to prepare frequency vertical cavity surface emitting lasers chip described in second aspect, comprising:
N-type layer, luminescent layer, current-limiting layer and P-type layer are sequentially formed on substrate, and the N-type layer and the P-type layer are equal
Including multilayer reflective layers, the current-limiting layer includes current injection area domain and insulating regions；
The P-type layer is etched, so that the P-type layer forms exposed region corresponding with the insulating regions, the exposure
The reflecting layer of bottom in the region exposure P-type layer；
P-type electrode layer is formed in the P-type layer, so that P-type electrode layer covering includes the p-type of the exposed region
Layer；
The P-type electrode layer is etched, so that the P-type electrode layer forms light out corresponding with the current injection area domain
Hole；
N-type electrode layer is formed in the substrate back.
6th aspect, the embodiment of the present application provide a kind of preparation method of frequency vertical cavity surface emitting lasers chip,
It is used to prepare frequency vertical cavity surface emitting lasers chip described in the third aspect, comprising:
N-type layer, luminescent layer, current-limiting layer and P-type layer are sequentially formed on substrate, and the N-type layer and the P-type layer are equal
Including multilayer reflective layers, the current-limiting layer includes current injection area domain and insulating regions；
Remove the fringe region of the P-type layer, luminescent layer and current-limiting layer, the fringe region of the exposure N-type layer；With
And the fringe region of the removal N-type layer, the fringe region of the exposure substrate；
P-type electrode layer is formed in the P-type layer；
The P-type electrode layer is etched, so that the P-type electrode layer forms light out corresponding with the current injection area domain
Hole；
The conductive layer for being connected to the multilayer reflective layers of the N-type layer is formed in the fringe region of the N-type layer；
N-type electrode layer is formed in the substrate back.
Compared with prior art, a kind of frequency vertical cavity surface emitting lasers chip provided by the embodiments of the present application, comprising:
Substrate, the N-type layer being sequentially formed on substrate, luminescent layer, current-limiting layer, P-type layer and P-type electrode layer, substrate back are formed
There is N-type electrode layer；N-type layer and P-type layer include multilayer reflective layers；Luminescent layer, current-limiting layer and P-type layer expose N-type layer
Fringe region；The fringe region of the exposure substrate of N-type layer；N-type layer edge is provided with the conduction of the multilayer reflective layers of connection N-type layer
Layer；Current-limiting layer includes current injection area domain and insulating regions；P-type layer includes exposed region corresponding with insulating regions, cruelly
Reveal the reflecting layer of the bottom in region exposure P-type layer；The covering of P-type electrode layer includes the P-type layer of exposed region, P-type electrode layer packet
Include light hole corresponding with current injection area domain.
As it can be seen that the multilayer in P-type layer and N-type layer is anti-in the frequency vertical cavity surface emitting lasers chip that the application provides
Layer is penetrated to be connected to by conductive material, such frequency vertical cavity surface emitting lasers chip after powered up, the phase in P-type layer and N-type layer
Will not occur capacity effect between adjacent reflecting layer again, so that the high frequency for improving frequency vertical cavity surface emitting lasers chip is sensitive
Property.
To enable the above objects, features, and advantages of the application to be clearer and more comprehensible, preferred embodiment is cited below particularly, and cooperate
Appended attached drawing, is described in detail below.
Detailed description of the invention
Technical solution in ord to more clearly illustrate embodiments of the present application, below will be to needed in the embodiment attached
Figure is briefly described, it should be understood that the following drawings illustrates only some embodiments of the application, therefore is not construed as pair
The restriction of range for those of ordinary skill in the art without creative efforts, can also be according to this
A little attached drawings obtain other relevant attached drawings.
Fig. 1 a shows the section of the first frequency vertical cavity surface emitting lasers chip provided by the embodiment of the present application
Structural schematic diagram；
Fig. 1 b shows the vertical view of the first frequency vertical cavity surface emitting lasers chip provided by the embodiment of the present application
Figure structure schematic representation；
Fig. 2 shows the preparation sides of the first frequency vertical cavity surface emitting lasers chip provided by the embodiment of the present application
Method flow diagram；
Fig. 3 shows the first corresponding system of frequency vertical cavity surface emitting lasers chip provided by the embodiment of the present application
One of standby process structure diagram；
Fig. 4 shows the first corresponding system of frequency vertical cavity surface emitting lasers chip provided by the embodiment of the present application
The two of standby process structure diagram；
Fig. 5 shows the first corresponding system of frequency vertical cavity surface emitting lasers chip provided by the embodiment of the present application
The three of standby process structure diagram；
Fig. 6 shows second of frequency vertical cavity surface emitting lasers chip structure signal provided by the embodiment of the present application
Figure；
Fig. 7 shows the preparation stream of second of frequency vertical cavity surface emitting lasers chip provided by the embodiment of the present application
Cheng Tu；
Fig. 8 shows the third frequency vertical cavity surface emitting lasers chip structure signal provided by application embodiment
Figure；
Fig. 9 shows the preparation stream of the third frequency vertical cavity surface emitting lasers chip provided by the embodiment of the present application
Cheng Tu.
Icon: 11- substrate；12-N type layer；13- luminescent layer；14- current-limiting layer；15-P type layer；16-P type electrode layer；
17-N type electrode layer；18- conductive layer；The current injection area 141- domain；142- insulating regions；151- exposed region；152- ohm connect
Contact layer；161- light hole.
Specific embodiment
To keep the purposes, technical schemes and advantages of the embodiment of the present application clearer, below in conjunction with the embodiment of the present application
Middle attached drawing, the technical scheme in the embodiment of the application is clearly and completely described, it is clear that described embodiment is only
It is some embodiments of the present application, instead of all the embodiments.The application being usually described and illustrated herein in the accompanying drawings is real
The component for applying example can be arranged and be designed with a variety of different configurations.Therefore, below to the application's provided in the accompanying drawings
The detailed description of embodiment is not intended to limit claimed scope of the present application, but is merely representative of the selected reality of the application
Apply example.Based on embodiments herein, those skilled in the art institute obtained without making creative work
There are other embodiments, shall fall in the protection scope of this application.
The embodiment of the present application provides a kind of frequency vertical cavity surface emitting lasers chip, as shown in Figure 1a, hangs down for high frequency
The section schematic diagram of straight cavity surface-emitting laser chip, Fig. 1 b are the top view of the frequency vertical cavity surface emitting lasers chip,
It include: substrate 11, the N-type layer being sequentially formed on substrate 11 12, luminescent layer 13, current-limiting layer 14, P-type layer 15 and p-type electricity
Pole layer 16,11 back side of substrate is formed with N-type electrode layer 17；N-type layer 12 and P-type layer 15 include multilayer reflective layers；Luminescent layer 13,
The fringe region of current-limiting layer 14 and the exposure N-type layer 12 of P-type layer 15；The fringe region of the exposure substrate 11 of N-type layer 12.
Optionally, substrate can be gallium arsenide substrate.
Optionally, the luminescent layer in the embodiment of the present application is AlxGa1-xAs/In xGaAs/AlxGa1-xAs Quantum Well knot
Structure, wherein x is the content of In, is adjusted according to wavelength.
In order to be depressured to the electric current being input in chip, P-type layer 15 further includes being set on multilayer reflective layers
Ohmic contact layer 152.Optionally, the ohmic contact layer in the application includes gallium arsenide layer.
The material of P-type electrode layer and N-type electrode layer is metal material, such as copper, silver and gold with good conductivity etc..
Wherein, 12 edge of N-type layer is provided with the conductive layer 18 of the multilayer reflective layers of connection N-type layer 12.
Current-limiting layer 14 includes current injection area domain 141 and insulating regions 142.
Here current injection area domain is conductive, and electric current can be connected to by the current injection area domain with luminescent layer, wherein
Current injection area domain in current-limiting layer can be square region, can be border circular areas, be in the embodiment of the present application circle
Bore region, and the diameter range in circular hole region is 5-15um.
P-type layer 15 includes exposed region 151 corresponding with insulating regions 142, and exposed region 151 exposes in P-type layer 15
The reflecting layer of bottom.
Here the reflecting layer of the bottom in exposed region exposure P-type layer, for example expose undermost a pair of of reflection in P-type layer
Layer or the last layer reflecting layer are in order to enable avoiding P-type electrode layer and electric current from limiting when P-type electrode layer is deposited in the later period here
Insulating regions contact in preparative layer, and cause electric current that can not enter luminescent layer by current injection area domain by insulation.
The covering of P-type electrode layer 16 includes the P-type layer 15 of exposed region 151, and P-type electrode layer includes and current injection area domain
141 corresponding light holes 161.
Optionally, the multilayer reflective layers of P-type layer constitute distributed bragg reflector mirror structure, the multilayer reflective layers of N-type layer
Constitute distributed bragg reflector mirror structure.
Specifically, the multilayer reflective layers in P-type layer constitute P-DBR structure, i.e. p-type distributed bragg reflector mirror, knot
Structure includes the alternate aluminium arsenide of multilayer and aluminum gallium arsenide, preferably, P-DBR structure includes 18 pairs alternate in the embodiment of the present application
Aluminium arsenide and aluminum gallium arsenide, structure as P-DBR structure, can increase the reflectivity to light, reflectivity is up to 99.8%.
N-type layer constitutes N-DBR structure, i.e. N-type distributed bragg reflector mirror, optionally, the N- in the embodiment of the present application
Dbr structure also includes the alternate aluminium arsenide layer of multilayer and aluminum gallium arsenide layer, it is preferable that N-DBR structure packet in the embodiment of the present application
32 pairs of alternate aluminium arsenide layers and aluminum gallium arsenide layer are included, structure as N-DBR structure can increase the reflectivity to light,
Reflectivity is up to 99.9%.
Preferably, the thickness of every layer of aluminium arsenide layer and aluminum gallium arsenide layer is wavelength in P-DBR structure and N-DBR structure
1/4.
The embodiment of the present application provides a kind of straight cavity surface-emitting laser chip, is used to prepare above-mentioned frequency vertical Cavity surface hair
Chip of laser is penetrated, as shown in Fig. 2, comprising the following specific steps
S200, sequentially forms N-type layer, luminescent layer, current-limiting layer and P-type layer on substrate, and N-type layer and P-type layer are wrapped
Multilayer reflective layers are included, current-limiting layer includes current injection area domain and insulating regions.
Here current-limiting layer can be by forming, so that oxide layer formation is led after carrying out wet oxidation to oxide layer
The current injection area domain of electricity and nonconducting insulating regions；It can also be by shape after conductive layer progress dielectric ion injection
At so that the conductive layer forms conductive current injection area domain and nonconducting insulating regions.
N-type layer 12, luminescent layer 13, current-limiting layer 14 and P-type layer 15 are sequentially formed on substrate 11, wherein N-type layer 12
It include multilayer reflective layers with P-type layer 15, current-limiting layer 14 includes current injection area domain 141 and insulating regions 142, P-type layer
Including the P-DBR layer being formed on current-limiting layer 14, and the ohmic contact layer 152 being formed on P-DBR layer, obtain in this way
Structure chart as shown in Figure 3.
Here the preparation method of current-limiting layer can not be done herein by the methods of ion implanting or patterned oxide
It is specific to limit.
S201, the fringe region of removal P-type layer, current-limiting layer and luminescent layer, the fringe region of exposure N-type layer；And
Remove the fringe region of N-type layer, the fringe region of exposure substrate.
Here removal may include wet etching or dry etching, as long as fringe region can be got rid of so that lower layer is sudden and violent
Dew, the method removed here are not specifically limited.
On the basis of Fig. 3, removal P-type layer 15 (here including ohmic contact layer 152 and P-DBR layers), current-limiting layer
14 and luminescent layer 13 fringe region, exposure N-type layer 12 fringe region；And the fringe region of removal N-type layer 12, exposure lining
The fringe region at bottom 11 obtains structure chart as shown in Figure 4.
S202 etches P-type layer, so that P-type layer forms exposed region corresponding with insulating regions, exposed region exposure p-type
The reflecting layer of bottom in layer.
S203 forms P-type electrode layer in P-type layer, so that the covering of P-type electrode layer includes the P-type layer of exposed region.
S204 etches P-type electrode layer, so that P-type electrode layer forms light hole corresponding with current injection area domain.
On the basis of fig. 4, P-type layer 15 is etched, so that P-type layer 15 forms exposed region corresponding with insulating regions 142
151, exposed region 151 exposes the reflecting layer of the bottom in P-type layer 15；Then vapor deposition forms P-type electrode layer in P-type layer 15
16, so that the covering of P-type electrode layer 16 includes the P-type layer 15 of exposed region 151.Then in etching P-type electrode layer 16, so that p-type
Electrode layer forms light hole 161 corresponding with current injection area domain, obtains structural schematic diagram as shown in Figure 5.
S305 forms the conductive layer of the multilayer reflective layers of connection N-type layer in the fringe region of N-type layer.
S306 forms N-type electrode layer in substrate back.
In the resulting structure basis of Fig. 5, the multilayer reflective layers of connection N-type layer are formed in the fringe region of N-type layer 12
Conductive layer 18 finally forms N-type electrode layer 17 in substrate back to get structure as shown in Figure 1 is arrived.
Compared with prior art, a kind of frequency vertical cavity surface emitting lasers chip provided by the embodiments of the present application, comprising:
Substrate, the N-type layer being sequentially formed on substrate, luminescent layer, current-limiting layer, P-type layer and P-type electrode layer, substrate back are formed
There is N-type electrode layer；N-type layer and P-type layer include multilayer reflective layers；Luminescent layer, current-limiting layer and P-type layer expose N-type layer
Fringe region；The fringe region of the exposure substrate of N-type layer；N-type layer edge is provided with the conduction of the multilayer reflective layers of connection N-type layer
Layer；Current-limiting layer includes current injection area domain and insulating regions；P-type layer includes exposed region corresponding with insulating regions, cruelly
Reveal the reflecting layer of the bottom in region exposure P-type layer；The covering of P-type electrode layer includes the P-type layer of exposed region, P-type electrode layer packet
Include light hole corresponding with current injection area domain.
As it can be seen that the multilayer in P-type layer and N-type layer is anti-in the frequency vertical cavity surface emitting lasers chip that the application provides
Layer is penetrated to be connected to by conductive material, such frequency vertical cavity surface emitting lasers chip after powered up, the phase in P-type layer and N-type layer
Will not occur capacity effect between adjacent reflecting layer again, to improve the high frequency sensibility of vertical cavity surface emitting laser chip.
The embodiment of the present application also provides a kind of frequency vertical cavity surface emitting lasers chips, as shown in Figure 6 include: substrate
11, N-type layer 12, luminescent layer 13, current-limiting layer 14, P-type layer 15 and the P-type electrode layer 16 being sequentially formed on substrate 11, lining
11 back side of bottom is formed with N-type electrode layer 17；N-type layer 12 and P-type layer 15 include multilayer reflective layers.
Current-limiting layer 14 includes current injection area domain 141 and insulating regions 142.
P-type layer 15 includes exposed region 151 corresponding with insulating regions 142, and exposed region 151 exposes in P-type layer 15
The reflecting layer of bottom.
The covering of P-type electrode layer 16 includes the P-type layer 15 of exposed region 151, and P-type electrode layer 16 includes and current injection area domain
141 corresponding light holes 161.
The frequency vertical Cavity surface in frequency vertical cavity surface emitting lasers chip and a upper embodiment in the embodiment is sent out
The material for penetrating each layer in chip of laser is identical, in a upper embodiment P-type layer, N-type layer and current-limiting layer structure it is identical,
Details are not described herein.
The embodiment of the present application provides a kind of preparation method of frequency vertical cavity surface emitting lasers chip, is used to prepare
Frequency vertical cavity surface emitting lasers chip is stated, as shown in fig. 7, comprises following steps S700~S704:
S700, sequentially forms N-type layer, luminescent layer, current-limiting layer and P-type layer on substrate, and N-type layer and P-type layer are wrapped
Multilayer reflective layers are included, current-limiting layer includes current injection area domain and insulating regions.
Here by step S700, obtained structural schematic diagram is as shown in figure 3, wherein P-type layer here further includes being formed
In the ohmic contact layer in multilayer reflective layers.
S701 etches P-type layer, so that P-type layer forms exposed region corresponding with insulating regions, exposed region exposure p-type
The reflecting layer of bottom in layer.
S702 forms P-type electrode layer in P-type layer, so that the covering of P-type electrode layer includes the P-type layer of exposed region.
S703 etches P-type electrode layer, so that P-type electrode layer forms light hole corresponding with current injection area domain.
S704 forms N-type electrode layer in substrate back.
On the basis of Fig. 3, P-type layer is etched, so that P-type layer forms exposed region corresponding with insulating regions, exposed region
The reflecting layer of bottom in domain exposure P-type layer；Then, P-type electrode layer is formed in P-type layer, so that the covering of P-type electrode layer includes
The P-type layer of exposed region；Then, P-type electrode layer is etched, so that P-type electrode layer forms light out corresponding with current injection area domain
Hole；Finally, N-type electrode layer is formed in substrate back, to obtain structure as shown in FIG. 6.
Compared with prior art, frequency vertical cavity surface emitting lasers chip provided by the embodiments of the present application include: substrate,
N-type layer, luminescent layer, current-limiting layer, P-type layer and P-type electrode layer, the substrate back being sequentially formed on substrate are formed with N-type
Electrode layer；N-type layer and P-type layer include multilayer reflective layers；Current-limiting layer includes current injection area domain and insulating regions；P-type
Layer includes exposed region corresponding with insulating regions, the reflecting layer of the bottom in exposed region exposure P-type layer；P-type electrode layer covers
Lid includes the P-type layer of exposed region, and P-type electrode layer includes light hole corresponding with current injection area domain.
As it can be seen that the multilayer reflective layers in P-type layer are led in the frequency vertical cavity surface emitting lasers chip that the application provides
Electric material connection, such frequency vertical cavity surface emitting lasers chip after powered up, will not between the subsequent reflective layers in P-type layer
Occurs capacity effect again, to improve the high frequency sensibility of vertical cavity surface emitting laser chip.
The embodiment of the present application provides a kind of frequency vertical cavity surface emitting lasers chip, as shown in Figure 8, comprising: substrate
11, N-type layer 12, luminescent layer 13, current-limiting layer 14, P-type layer 15 and the P-type electrode layer 16 being sequentially formed on substrate 11, lining
11 back side of bottom is formed with N-type electrode layer 17；N-type layer 12 and P-type layer 15 include multilayer reflective layers；Luminescent layer 13, current limit
The fringe region of layer 14 and the exposure N-type layer 12 of P-type layer 15；The fringe region of the exposure substrate 11 of N-type layer 12.
Wherein, P-type layer 15 includes the multilayer reflective layers being formed on current-limiting layer and is formed in multilayer reflective layers
Ohmic contact layer 152.
12 edge of N-type layer is provided with the conductive layer 18 of the multilayer reflective layers of connection N-type layer.
Current-limiting layer 14 includes current injection area domain 141 and insulating regions 142.
P-type electrode layer 16 includes light hole 161 corresponding with current injection area domain 141.
The frequency vertical Cavity surface in frequency vertical cavity surface emitting lasers chip and a upper embodiment in the embodiment is sent out
The material for penetrating each layer in chip of laser is identical, in a upper embodiment P-type layer, N-type layer and current-limiting layer structure it is identical,
Details are not described herein.
The embodiment of the present application provides a kind of preparation method of frequency vertical cavity surface emitting lasers chip, is used to prepare
Frequency vertical cavity surface emitting lasers chip is stated, as shown in figure 9, including step S900~S904 in detail below:
S900, sequentially forms N-type layer, luminescent layer, current-limiting layer and P-type layer on substrate, and N-type layer and P-type layer are wrapped
Multilayer reflective layers are included, current-limiting layer includes current injection area domain and insulating regions.
Here by step S900, obtained structural schematic diagram is as shown in figure 3, wherein P-type layer here further includes being formed
In the ohmic contact layer in multilayer reflective layers.
S901, the fringe region of removal P-type layer, current-limiting layer and luminescent layer, the fringe region of exposure N-type layer；And
Remove the fringe region of N-type layer, the fringe region of exposure substrate.
On the basis of Fig. 3, step S901 is executed, structure as shown in Figure 4 is obtained.
S902 forms P-type electrode layer in P-type layer；P-type electrode layer is etched, is injected so that P-type electrode layer is formed with electric current
The corresponding light hole in region.
S903 forms the conductive layer of the multilayer reflective layers of connection N-type layer in the fringe region of N-type layer.
S904 forms N-type electrode layer in substrate back.
On the basis of fig. 4, step S902, S903 and S904 are successively executed, structure as shown in Figure 8 is obtained.
Compared with prior art, a kind of frequency vertical cavity surface emitting lasers chip provided by the embodiments of the present application, comprising:
Substrate, the N-type layer being sequentially formed on the substrate, luminescent layer, current-limiting layer, P-type layer and P-type electrode layer, substrate back
It is formed with N-type electrode layer；N-type layer and P-type layer include multilayer reflective layers；Luminescent layer, current-limiting layer and P-type layer exposure N-type
The fringe region of layer；The fringe region of the exposure substrate of N-type layer；N-type layer edge is provided with the multilayer reflective layers of connection N-type layer
Conductive layer；Current-limiting layer includes current injection area domain and insulating regions；P-type electrode layer includes corresponding with current injection area domain
Light hole.
As it can be seen that the multilayer reflective layers in N-type layer are led in the frequency vertical cavity surface emitting lasers chip that the application provides
Electric material connection, such frequency vertical cavity surface emitting lasers chip after powered up, will not between the subsequent reflective layers in N-type layer
Occurs capacity effect again, to improve the high frequency sensibility of vertical cavity surface emitting laser chip.
It should also be noted that similar label and letter indicate similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined in a attached drawing, does not then need that it is further defined and explained in subsequent attached drawing.
In the description of the present application, it should be noted that term " center ", "upper", "lower", "left", "right", "vertical",
The orientation or positional relationship of the instructions such as "horizontal", "inner", "outside" is to be based on the orientation or positional relationship shown in the drawings, or be somebody's turn to do
Invention product using when the orientation or positional relationship usually put, be merely for convenience of description the application and simplify description, without
It is that the device of indication or suggestion meaning or element must have a particular orientation, be constructed and operated in a specific orientation, therefore not
It can be interpreted as the limitation to the application.In addition, term " first ", " second ", " third " etc. are only used for distinguishing description, and cannot manage
Solution is indication or suggestion relative importance.
In the description of the present application, it is also necessary to which explanation is unless specifically defined or limited otherwise, term " setting ",
" installation ", " connected ", " connection " shall be understood in a broad sense, for example, it may be fixedly connected, may be a detachable connection or one
Connect to body；It can be mechanical connection, be also possible to be electrically connected；It can be directly connected, it can also be indirect by intermediary
It is connected, can be the connection inside two elements.For the ordinary skill in the art, on being understood with concrete condition
State the concrete meaning of term in this application.
Finally, it should be noted that embodiment described above, the only specific embodiment of the application, to illustrate the application
Technical solution, rather than its limitations, the protection scope of the application is not limited thereto, although with reference to the foregoing embodiments to this Shen
It please be described in detail, those skilled in the art should understand that: anyone skilled in the art
Within the technical scope of the present application, it can still modify to technical solution documented by previous embodiment or can be light
It is readily conceivable that variation or equivalent replacement of some of the technical features；And these modifications, variation or replacement, do not make
The essence of corresponding technical solution is detached from the spirit and scope of the embodiment of the present application technical solution.The protection in the application should all be covered
Within the scope of.Therefore, the protection scope of the application shall be subject to the protection scope of the claim.
Claims (10)
1. a kind of frequency vertical cavity surface emitting lasers chip characterized by comprising
Substrate, the N-type layer being sequentially formed on the substrate, luminescent layer, current-limiting layer, P-type layer and P-type electrode layer, it is described
Substrate back is formed with N-type electrode layer；The N-type layer and the P-type layer include multilayer reflective layers；It is the luminescent layer, described
The fringe region of current-limiting layer and the P-type layer exposure N-type layer；The fringe region of the N-type layer exposure substrate；
The N-type layer edge is provided with the conductive layer for being connected to the multilayer reflective layers of the N-type layer；
The current-limiting layer includes current injection area domain and insulating regions；
The P-type layer includes exposed region corresponding with the insulating regions, the bottom in the exposed region exposure P-type layer
The reflecting layer of layer；
The P-type electrode layer covering includes the P-type layer of the exposed region, and the P-type electrode layer includes injecting with the electric current
The corresponding light hole in region.
2. chip according to claim 1, which is characterized in that the P-type layer further includes being set on multilayer reflective layers
Ohmic contact layer.
3. chip according to claim 1, which is characterized in that the multilayer reflective layers of the P-type layer constitute p-type distribution cloth
The multilayer reflective layers of glug mirror structure, the N-type layer constitute N-type distributed bragg reflector mirror structure.
4. chip according to claim 3, which is characterized in that the p-type distributed bragg reflector mirror structure includes more
The alternate aluminium arsenide layer of layer and aluminum gallium arsenide layer；
The N-type distributed bragg reflector mirror structure includes the alternate aluminium arsenide layer of multilayer and aluminum gallium arsenide layer.
5. chip according to claim 1, which is characterized in that the current injection area domain is circular hole region, the circular hole
The diameter range in region is 5-15um.
6. a kind of frequency vertical cavity surface emitting lasers chip characterized by comprising
Substrate, the N-type layer being sequentially formed on the substrate, luminescent layer, current-limiting layer, P-type layer and P-type electrode layer, it is described
Substrate back is formed with N-type electrode layer；The N-type layer and the P-type layer include multilayer reflective layers；
The current-limiting layer includes current injection area domain and insulating regions；
The P-type layer includes exposed region corresponding with the insulating regions, the bottom in the exposed region exposure P-type layer
The reflecting layer of layer；
The P-type electrode layer covering includes the P-type layer of the exposed region, and the P-type electrode layer includes injecting with the electric current
The corresponding light hole in region.
7. a kind of frequency vertical cavity surface emitting lasers chip characterized by comprising
Substrate, the N-type layer being sequentially formed on the substrate, luminescent layer, current-limiting layer, P-type layer and P-type electrode layer, it is described
Substrate back is formed with N-type electrode layer；The N-type layer and the P-type layer include multilayer reflective layers；It is the luminescent layer, described
The fringe region of current-limiting layer and the P-type layer exposure N-type layer；The fringe region of the N-type layer exposure substrate；
The N-type layer edge is provided with the conductive layer for being connected to the multilayer reflective layers of the N-type layer；
The current-limiting layer includes current injection area domain and insulating regions；
The P-type electrode layer includes light hole corresponding with the current injection area domain.
8. a kind of preparation method of frequency vertical cavity surface emitting lasers chip, it is any described to be used to prepare claim 1 to 5
Frequency vertical cavity surface emitting lasers chip characterized by comprising
N-type layer, luminescent layer, current-limiting layer and P-type layer are sequentially formed on substrate, and the N-type layer and the P-type layer include
Multilayer reflective layers, the current-limiting layer include current injection area domain and insulating regions；
Remove the fringe region of the P-type layer, the current-limiting layer and the luminescent layer, the marginal zone of the exposure N-type layer
Domain；And the fringe region of the removal N-type layer, the fringe region of the exposure substrate；
The P-type layer is etched, so that the P-type layer forms exposed region corresponding with the insulating regions, the exposed region
The reflecting layer of bottom in the exposure P-type layer；
P-type electrode layer is formed in the P-type layer, so that P-type electrode layer covering includes the P-type layer of the exposed region；
The P-type electrode layer is etched, so that the P-type electrode layer forms light hole corresponding with the current injection area domain；
The conductive layer for being connected to the multilayer reflective layers of the N-type layer is formed in the fringe region of the N-type layer；
N-type electrode layer is formed in the substrate back.
9. a kind of preparation method of frequency vertical cavity surface emitting lasers chip is used to prepare high frequency as claimed in claim 6 and hangs down
Straight cavity surface-emitting laser chip characterized by comprising
N-type layer, luminescent layer, current-limiting layer and P-type layer are sequentially formed on substrate, and the N-type layer and the P-type layer include
Multilayer reflective layers, the current-limiting layer include current injection area domain and insulating regions；
The P-type layer is etched, so that the P-type layer forms exposed region corresponding with the insulating regions, the exposed region
The reflecting layer of bottom in the exposure P-type layer；
P-type electrode layer is formed in the P-type layer, so that P-type electrode layer covering includes the P-type layer of the exposed region；
The P-type electrode layer is etched, so that the P-type electrode layer forms light hole corresponding with the current injection area domain；
N-type electrode layer is formed in the substrate back.
10. a kind of preparation method of frequency vertical cavity surface emitting lasers chip is used to prepare high frequency as claimed in claim 7 and hangs down
Straight cavity surface-emitting laser chip characterized by comprising
N-type layer, luminescent layer, current-limiting layer and P-type layer are sequentially formed on substrate, and the N-type layer and the P-type layer include
Multilayer reflective layers, the current-limiting layer include current injection area domain and insulating regions；
Remove the fringe region of the P-type layer, luminescent layer and current-limiting layer, the fringe region of the exposure N-type layer；And it goes
Except the fringe region of the N-type layer, the fringe region of the exposure substrate；
P-type electrode layer is formed in the P-type layer；
The P-type electrode layer is etched, so that the P-type electrode layer forms light hole corresponding with the current injection area domain；
The conductive layer for being connected to the multilayer reflective layers of the N-type layer is formed in the fringe region of the N-type layer；
N-type electrode layer is formed in the substrate back.
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