CN109066292A - A kind of vertical cavity surface emitting laser chip of multilayer current limliting and preparation method thereof - Google Patents
A kind of vertical cavity surface emitting laser chip of multilayer current limliting and preparation method thereof Download PDFInfo
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- CN109066292A CN109066292A CN201811205139.4A CN201811205139A CN109066292A CN 109066292 A CN109066292 A CN 109066292A CN 201811205139 A CN201811205139 A CN 201811205139A CN 109066292 A CN109066292 A CN 109066292A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
- H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
- H01S5/343—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
- H01S5/34313—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser with a well layer having only As as V-compound, e.g. AlGaAs, InGaAs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
- H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
- H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
- H01S5/343—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
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- Semiconductor Lasers (AREA)
Abstract
The embodiment of the present application provides a kind of vertical cavity surface emitting laser chip and preparation method thereof of multilayer current limliting, wherein, which includes: substrate, the N-type layer being sequentially formed on the substrate, luminescent layer, current-limiting layer, P-type layer and P-type electrode layer；The substrate back is formed with N-type electrode layer；The current-limiting layer includes the first current-limiting layer being formed on the luminescent layer and is formed in the second current-limiting layer on first current-limiting layer；First current-limiting layer includes the first current injection area domain；Second current-limiting layer includes the second current injection area domain corresponding with first current injection area domain, and the cross-sectional area in first current injection area domain is less than the cross-sectional area in second current injection area domain；The P-type electrode layer includes light hole corresponding with second current injection area domain.The embodiment of the present application improves the single mode effect of vertical cavity surface emitting laser.
Description
Technical field
This application involves technical field of semiconductors, in particular to a kind of vertical cavity surface-emitting laser of multilayer current limliting
Device chip and preparation method thereof.
Background technique
VCSEL, complete entitled vertical cavity surface emitting laser (Vertical Cavity Surface Emitting
Laser), developed based on gallium arsenide semiconductor material, being different from LED (light emitting diode) and LD, (Laser Diode swashs
Optical diode) etc. other light sources, have small in size, round output facula, single longitudinal mode output, threshold current it is small, cheap, easy
The advantages that being integrated into large area array is widely applied and the fields such as optic communication, light network, optical storage.
Currently, VCSEL chip mainly limits electric current by the way that oxide regions are arranged in oxide layer, to reach
The chip of single mode array, however since the prior art mainly forms conductive region by being aoxidized in oxide layer, it is existing
Have in technology because the cross-sectional area of conductive region is more difficult to control, in this way when the cross-sectional area of conductive region is not small enough when aoxidizing
When, can not just current limit be carried out to the electric current for flowing into oxide regions, to obtain the VCSEL chip of single mode array.
To sum up, the VCSEL chip of single mode array in the prior art is prepared cumbersome, obtained VCSEL chip single mode effect
It is bad.
Summary of the invention
In view of this, a kind of vertical cavity surface emitting laser chip for being designed to provide multilayer current limliting of the application and its
Preparation method, to improve the single mode effect of vertical cavity surface emitting laser.
In a first aspect, the embodiment of the present application provides a kind of vertical cavity surface emitting laser chip of multilayer current limliting, comprising:
Substrate, the N-type layer being sequentially formed on the substrate, luminescent layer, current-limiting layer, P-type layer and P-type electrode layer；
The substrate back is formed with N-type electrode layer；
The current-limiting layer includes the first current-limiting layer being formed on the luminescent layer and is formed in described first
Second current-limiting layer on current-limiting layer；
First current-limiting layer includes the first current injection area domain；Second current-limiting layer includes and described
One corresponding second current injection area in current injection area domain domain, the cross-sectional area in first current injection area domain are less than described the
The cross-sectional area of two current injection areas domain；
The P-type electrode layer includes light hole corresponding with second current injection area domain.
With reference to first aspect, the embodiment of the present application provides the first possible embodiment of first aspect, the p-type
Layer includes the P-DBR layer being formed on the current-limiting layer and the ohmic contact layer being formed on the P-DBR layer.
The possible embodiment of with reference to first aspect the first, the embodiment of the present application provide second of first aspect
Possible embodiment, described P-DBR layers includes the alternate aluminium arsenide layer of multilayer and aluminum gallium arsenide layer.
With reference to first aspect, the embodiment of the present application provides the third possible embodiment of first aspect, the N-type
Layer is N-DBR layers, and described N-DBR layers includes the alternate aluminium arsenide layer of multilayer and aluminum gallium arsenide layer.
With reference to first aspect, the embodiment of the present application provides the 4th kind of possible embodiment of first aspect, and described
One current injection area domain is the first cylindrical region, and the diameter range of first cylindrical region is 3-5um.
With reference to first aspect, the embodiment of the present application provides the 5th kind of possible embodiment of first aspect, and described
Two current injection areas domain are the second cylindrical region, and the diameter range of second cylindrical region is 5-15um.
With reference to first aspect, the embodiment of the present application provides the 6th kind of possible embodiment of first aspect, it is described go out
The cross-sectional area of unthreaded hole is less than the cross-sectional area in second current injection area domain.
With reference to first aspect, the embodiment of the present application provides the 7th kind of possible embodiment of first aspect, the hair
Photosphere is quantum well structure.
With reference to first aspect, the embodiment of the present application provides the 8th kind of possible embodiment of first aspect, and described
The thickness range of two current-limiting layers is 20-40nm.
Second aspect, the embodiment of the present application provide a kind of preparation of the vertical cavity surface emitting laser chip of multilayer current limliting
Method, comprising:
N-type layer and luminescent layer are sequentially formed on substrate；
The first current-limiting layer is formed on the light-emitting layer, is carried out ion implanting to first current-limiting layer, is made
It obtains unimplanted region and forms the first current injection area domain；
Form the second current-limiting layer on first current-limiting layer so that second current-limiting layer formed with
First current injection area domain corresponding second current injection area domain, and the cross-sectional area in first current injection area domain is small
Cross-sectional area in second current injection area domain；
P-type layer and P-type electrode layer are sequentially formed on second current-limiting layer, so that the P-type electrode layer is formed
Light hole corresponding with second current injection area domain；
N-type electrode layer is formed in the substrate back.
Compared with prior art, vertical cavity surface emitting laser chip provided by the embodiments of the present application, comprising: substrate, according to
Secondary N-type layer formed on substrate, luminescent layer, current-limiting layer, P-type layer and P-type electrode layer；Substrate back is formed with N-type electricity
Pole layer；Current-limiting layer includes the first current-limiting layer being formed on luminescent layer and is formed in second on the first current-limiting layer
Current-limiting layer；First current-limiting layer includes the first current injection area domain；Second current-limiting layer includes infusing with the first electric current
Enter corresponding second current injection area in region domain, the cross-sectional area in the first current injection area domain is less than the second current injection area domain
Cross-sectional area；P-type electrode layer includes light hole corresponding with the second current injection area domain.
As it can be seen that the embodiment of the present application passes through two layers of current-limiting layer of setting, and this two layers of current-limiting layer is leaned on luminescent layer
The current injection area domain of the current-limiting layer of the small layer thereon of the cross-sectional area in the current injection area domain of close current-limiting layer
Cross-sectional area, in this way, after P-type electrode layer is powered, on the one hand the in the second current-limiting layer first by being located at upper layer
Two current injection areas domain the electric current of injection is carried out it is extending transversely, then pass through in the first current-limiting layer for being located at lower layer first
Current injection area domain further homogenizes the electric current after extending transversely；On the other hand by two layers current-limiting layer into
One step has elongated the road strength of electric current, thus the comprehensive single mode effect for improving the vertical cavity surface emitting laser.
To enable the above objects, features, and advantages of the application to be clearer and more comprehensible, preferred embodiment is cited below particularly, and cooperate
Appended attached drawing, is described in detail below.
Detailed description of the invention
Technical solution in ord to more clearly illustrate embodiments of the present application, below will be to needed in the embodiment attached
Figure is briefly described, it should be understood that the following drawings illustrates only some embodiments of the application, therefore is not construed as pair
The restriction of range for those of ordinary skill in the art without creative efforts, can also be according to this
A little attached drawings obtain other relevant attached drawings.
Fig. 1 shows a kind of knot of the vertical cavity surface emitting laser chip of multilayer current limliting provided by the embodiment of the present application
Structure schematic diagram；
Fig. 2 shows a kind of vertical cavity surface emitting laser chips for preparing multilayer current limliting provided by the embodiment of the present application
Method flow schematic diagram；
Fig. 3 shows the mistake of the vertical cavity surface emitting laser chip of preparation multilayer current limliting provided by the embodiment of the present application
One of journey figure；
Fig. 4 shows the mistake of the vertical cavity surface emitting laser chip of preparation multilayer current limliting provided by the embodiment of the present application
The two of journey figure；
Fig. 5 shows the mistake of the vertical cavity surface emitting laser chip of preparation multilayer current limliting provided by the embodiment of the present application
The three of journey figure；
Fig. 6 shows the mistake of the vertical cavity surface emitting laser chip of preparation multilayer current limliting provided by the embodiment of the present application
The four of journey figure.
Icon: 11- substrate；12-N type layer；13- luminescent layer；14- current-limiting layer；15-P type layer；16-P type electrode layer；
17-N type electrode layer；The first current-limiting layer of 141-；The second current-limiting layer of 142-；The first current injection area 1411- domain；
The second current injection area 1421- domain；151-P-DBR layers；152- ohmic contact layer；161- light hole.
Specific embodiment
To keep the purposes, technical schemes and advantages of the embodiment of the present application clearer, below in conjunction with the embodiment of the present application
Middle attached drawing, the technical scheme in the embodiment of the application is clearly and completely described, it is clear that described embodiment is only
It is some embodiments of the present application, instead of all the embodiments.The application being usually described and illustrated herein in the accompanying drawings is real
The component for applying example can be arranged and be designed with a variety of different configurations.Therefore, below to the application's provided in the accompanying drawings
The detailed description of embodiment is not intended to limit claimed scope of the present application, but is merely representative of the selected reality of the application
Apply example.Based on embodiments herein, those skilled in the art institute obtained without making creative work
There are other embodiments, shall fall in the protection scope of this application.
The embodiment of the present application provides a kind of vertical cavity surface emitting laser chip of multilayer current limliting, as shown in Figure 1, packet
It includes:
Substrate 11, the N-type layer 12 being sequentially formed on substrate 11, luminescent layer 13, current-limiting layer 14, P-type layer 15 and p-type
Electrode layer 16；Substrate back is formed with N-type electrode layer 17.
Optionally, substrate can be gallium arsenide substrate.
Optionally, the luminescent layer in the embodiment of the present application is AlxGa1-xAs/In xGaAs/AlxGa1-xAs Quantum Well knot
Structure, wherein x is the content of In, is adjusted according to wavelength.
The material of P-type electrode layer and N-type electrode layer is metal material, such as copper, silver and gold with good conductivity etc..
Wherein, in order to be depressured to the electric current being input in chip, P-type layer 15 includes being formed on current-limiting layer 14
P-DBR layer 151 and the ohmic contact layer 152 that is formed on P-DBR layer 151.Ohmic contact layer in the application includes arsenic
Gallium layer.
Current-limiting layer 14 includes that the first current-limiting layer 141 being formed on luminescent layer 13 is limited with the first electric current is formed in
Second current-limiting layer 142 on preparative layer 141.
First current-limiting layer 141 includes the first current injection area domain 1411；Second current-limiting layer 142 includes and first
1411 corresponding second current injection area domain 1421 of current injection area domain, the cross-sectional area in the first current injection area domain 1411 are less than
The cross-sectional area of second current injection area domain 1421.
P-type electrode layer 16 includes light hole 161 corresponding with the second current injection area domain 1421.
Specifically, the multilayer reflective layers in P-type layer constitute P-DBR structure, i.e. p-type distributed bragg reflector mirror, knot
Structure includes the alternate aluminium arsenide of multilayer and aluminum gallium arsenide, preferably, P-DBR structure includes 20 pairs alternate in the embodiment of the present application
Aluminium arsenide and aluminum gallium arsenide, structure as P-DBR structure, can increase the reflectivity to light, reflectivity is up to 99.8%.
N-type layer constitutes N-DBR structure, i.e. N-type distributed bragg reflector mirror, optionally, the N- in the embodiment of the present application
Dbr structure also includes the alternate aluminium arsenide layer of multilayer and aluminum gallium arsenide layer, it is preferable that N-DBR structure packet in the embodiment of the present application
32 pairs of alternate aluminium arsenide layers and aluminum gallium arsenide layer are included, structure as N-DBR structure can increase the reflectivity to light,
Reflectivity is up to 99.9%.
Optionally, the shape in the first current injection area domain can be square body and be also possible to cylindrical body, it is preferable that the first electricity
Stream injection zone is the first cylindrical region, and the diameter range of the first cylindrical region is 3-5um, it is preferable that the first cylindrical region
Diameter is 4um.
Equally, the shape in the second current injection area domain can be square body and be also possible to cylindrical body, it is preferable that the second electric current
Injection zone is the second cylindrical region, and the diameter range of the second cylindrical region is 5-15um.Optionally, second current-limiting layer
Thickness range is 20-40nm；Preferably, the diameter of the second cylindrical region be 10um, the second current-limiting layer with a thickness of 30um.
Optionally, the material in the first current injection area domain in the first current-limiting layer in the embodiment of the present application is arsenic
Gallium, by being doped charcoal, magnesium or zinc etc. to GaAs, doping concentration is 5 × e18/cm3, so that GaAs is led
It electrically improves, the material in the second current injection area domain in the second current-limiting layer is aluminium arsenide, here the first current injection area
The electric conductivity of the material in domain is greater than the electric conductivity of the material in the second current injection area domain.It can be improved the vertical-cavity surface-emitting in this way
The power of chip of laser.
When the light of luminescent layer transmitting is emitted from the second current injection area domain, close to the second current injection area domain inner sidewall
The light of position, outgoing may have multimode emergent light, in order to enable the light being emitted from P-type electrode layer keeps single mode, the application
In embodiment, less than the cross-sectional area in the second current injection area domain, such P-type electrode layer can be filtered for the cross-sectional area of light hole
The multimode light of second current injection area domain edge, only allows the light of single mode to be emitted.
In the embodiment of the present application, the current injection area domain of this two layers of current-limiting layer and the close current-limiting layer of luminescent layer
The small layer thereon of cross-sectional area current-limiting layer current injection area domain cross-sectional area, in this way, when P-type electrode layer be powered
Afterwards, the second current injection area domain on the one hand in the second current-limiting layer first by being located at upper layer carries out the electric current of injection
It is extending transversely, then the first current injection area domain in the first current-limiting layer by being located at lower layer, to the electricity after extending transversely
Stream is further homogenized；On the other hand pass through two layers of current-limiting layer further elongation road strength of electric current, thus comprehensive
Improve the single mode effect of the vertical cavity surface emitting laser.
Further, the cross-sectional area of the light hole in the embodiment of the present application in P-type electrode layer is injected less than the second electric current
The cross-sectional area in region, such P-type electrode layer can filter the multimode light at the second current injection area domain edge, only allow the light of single mode
Outgoing, further increases the single mode effect of the vertical cavity surface emitting laser in this way.
Further, the electric conductivity of the material in the first current injection area domain in the embodiment of the present application is infused greater than the second electric current
Enter the electric conductivity of the material in region.It can be improved the power of the vertical cavity surface emitting laser chip in this way.
The embodiment of the present application also provides a kind of preparation methods of the vertical cavity surface emitting laser chip of multilayer current limliting, such as
Shown in Fig. 2, including step S200~S20 in detail below:
S200 sequentially forms N-type layer and luminescent layer on substrate.
Wherein, the preferred gallium arsenide substrate of substrate 11 forms N-type layer 12 and luminescent layer 13 in gallium arsenide substrate, is forming N
When type layer 12, it is specially alternatively formed 32 pairs of aluminium arsenide layers and aluminum gallium arsenide layer on substrate, then in one layer of arsenic topmost
Luminescent layer 13 is formed on gallium aluminium layer, obtains structure as shown in Figure 3.
S201 forms the first current-limiting layer on the light-emitting layer, ion implanting is carried out to the first current-limiting layer, so that not
The region of injection forms the first current injection area domain.
On the basis of Fig. 3, the first current-limiting layer 141, such as gallium arsenide layer are formed on luminescent layer 13, is then passed through
Ion implantation injects insulating particle, so that the region of injection insulating particle forms insulating regions, unimplanted insulating particle
Region forms the first current injection area domain 1411, it is preferable that the second current injection area domain is cylindrical region, and diameter range is
3-5um obtains structure as shown in Figure 4 in this way.
S202 forms the second current-limiting layer on the first current-limiting layer, so that the second current-limiting layer is formed and the
One corresponding second current injection area in current injection area domain domain, and the cross-sectional area in the first current injection area domain is less than the second electric current
The cross-sectional area of injection zone.
On the basis of fig. 4, the second current-limiting layer 142, the second current limit are formed on the first current-limiting layer 141
The material of layer 142 can be aluminium arsenide, then by the method for wet oxidation, so that the second current-limiting layer 142 is formed and the
One current injection area domain, 1411 corresponding second current injection area domain 1421；Alternatively, using the method for ion implanting in the second electricity
Ductility limit preparative layer 142 injects insulating particle, so that the formation of the second current-limiting layer 142 is corresponding with the first current injection area domain 1411
Second current injection area domain 1421, and make the cross-sectional area in the first current injection area domain 1411 less than the second current injection area domain
1421 cross-sectional area obtains structure as shown in Figure 5.
S203 sequentially forms P-type layer and P-type electrode layer on the second current-limiting layer, so that P-type electrode layer is formed and the
The corresponding light hole in two current injection areas domain.
Specifically, in step S203, forming P-type layer 15 includes:
S2031 forms P-DBR layer 151 on the second current-limiting layer 142, i.e., replaces shape on the second current-limiting layer
At 20 pairs of aluminium arsenide layers and aluminum gallium arsenide layer, ohmic contact layer 152 then is formed on one layer of aluminum gallium arsenide layer topmost, here
Ohmic contact layer 152 is preferably gallium arsenide layer.
S2032 forms P-type electrode layer 16 on ohmic contact layer 152, and is etched to P-type electrode layer, so that p-type
Electrode layer 16 forms light hole 161 corresponding with the second current injection area domain 1421.
Structure as shown in FIG. 6 is obtained by S2031 and S2032.
S204 forms N-type electrode layer in substrate back.
Finally on the basis of Fig. 6, N-type electrode layer is prepared at 11 back side of substrate, obtains structure as shown in Figure 1.
Compared with prior art, the vertical cavity surface emitting laser chip of multilayer current limliting provided by the embodiments of the present application, packet
It includes: substrate, the N-type layer being sequentially formed on substrate, luminescent layer, current-limiting layer, P-type layer and P-type electrode layer；Substrate back shape
At there is N-type electrode layer；Current-limiting layer includes that the first current-limiting layer being formed on luminescent layer is limited with the first electric current is formed in
Second current-limiting layer on preparative layer；First current-limiting layer includes the first current injection area domain；Second current-limiting layer include with
First corresponding second current injection area in current injection area domain domain, the cross-sectional area in the first current injection area domain is less than the second electric current
The cross-sectional area of injection zone；P-type electrode layer includes light hole corresponding with the second current injection area domain.
As it can be seen that the embodiment of the present application passes through two layers of current-limiting layer of setting, and this two layers of current-limiting layer is leaned on luminescent layer
The current injection area domain of the current-limiting layer of the small layer thereon of the cross-sectional area in the current injection area domain of close current-limiting layer
Cross-sectional area, in this way, after P-type electrode layer is powered, on the one hand the in the second current-limiting layer first by being located at upper layer
Two current injection areas domain the electric current of injection is carried out it is extending transversely, then pass through in the first current-limiting layer for being located at lower layer first
Current injection area domain further homogenizes the electric current after extending transversely；On the other hand by two layers current-limiting layer into
One step has elongated the road strength of electric current, thus the comprehensive single mode effect for improving the vertical cavity surface emitting laser.
Further, the cross-sectional area of the light hole in the embodiment of the present application in P-type electrode layer is injected less than the second electric current
The cross-sectional area in region, such P-type electrode layer can filter the multimode light at the second current injection area domain edge, only allow the light of single mode
Outgoing, further increases the single mode effect of the vertical cavity surface emitting laser in this way.
Further, the electric conductivity of the material in the first current injection area domain in the embodiment of the present application is infused greater than the second electric current
Enter the electric conductivity of the material in region.It can be improved the power of the vertical cavity surface emitting laser chip in this way.
It should also be noted that similar label and letter indicate similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined in a attached drawing, does not then need that it is further defined and explained in subsequent attached drawing.
In the description of the present application, it should be noted that term " center ", "upper", "lower", "left", "right", "vertical",
The orientation or positional relationship of the instructions such as "horizontal", "inner", "outside" is to be based on the orientation or positional relationship shown in the drawings, or be somebody's turn to do
Invention product using when the orientation or positional relationship usually put, be merely for convenience of description the application and simplify description, without
It is that the device of indication or suggestion meaning or element must have a particular orientation, be constructed and operated in a specific orientation, therefore not
It can be interpreted as the limitation to the application.In addition, term " first ", " second ", " third " etc. are only used for distinguishing description, and cannot manage
Solution is indication or suggestion relative importance.
In the description of the present application, it is also necessary to which explanation is unless specifically defined or limited otherwise, term " setting ",
" installation ", " connected ", " connection " shall be understood in a broad sense, for example, it may be fixedly connected, may be a detachable connection or one
Connect to body；It can be mechanical connection, be also possible to be electrically connected；It can be directly connected, it can also be indirect by intermediary
It is connected, can be the connection inside two elements.For the ordinary skill in the art, on being understood with concrete condition
State the concrete meaning of term in this application.
Finally, it should be noted that embodiment described above, the only specific embodiment of the application, to illustrate the application
Technical solution, rather than its limitations, the protection scope of the application is not limited thereto, although with reference to the foregoing embodiments to this Shen
It please be described in detail, those skilled in the art should understand that: anyone skilled in the art
Within the technical scope of the present application, it can still modify to technical solution documented by previous embodiment or can be light
It is readily conceivable that variation or equivalent replacement of some of the technical features；And these modifications, variation or replacement, do not make
The essence of corresponding technical solution is detached from the spirit and scope of the embodiment of the present application technical solution.The protection in the application should all be covered
Within the scope of.Therefore, the protection scope of the application shall be subject to the protection scope of the claim.
Claims (10)
1. a kind of vertical cavity surface emitting laser chip of multilayer current limliting characterized by comprising
Substrate, the N-type layer being sequentially formed on the substrate, luminescent layer, current-limiting layer, P-type layer and P-type electrode layer；It is described
Substrate back is formed with N-type electrode layer；
The current-limiting layer includes the first current-limiting layer being formed on the luminescent layer and is formed in first electric current
Second current-limiting layer on limiting layer；
First current-limiting layer includes the first current injection area domain；Second current-limiting layer include and it is described first electricity
Injection zone corresponding second current injection area domain is flowed, the cross-sectional area in first current injection area domain is less than second electricity
Flow the cross-sectional area of injection zone；
The P-type electrode layer includes light hole corresponding with second current injection area domain.
2. chip according to claim 1, which is characterized in that the P-type layer includes being formed on the current-limiting layer
P-DBR layer and the ohmic contact layer that is formed on the P-DBR layer.
3. chip according to claim 2, which is characterized in that described P-DBR layers include the alternate aluminium arsenide layer of multilayer and
Aluminum gallium arsenide layer.
4. chip according to claim 1, which is characterized in that the N-type layer is N-DBR layers, and described N-DBR layers includes more
The alternate aluminium arsenide layer of layer and aluminum gallium arsenide layer.
5. chip according to claim 1, which is characterized in that first current injection area domain is the first cylindrical region,
The diameter range of first cylindrical region is 3-5um.
6. chip according to claim 1, which is characterized in that second current injection area domain is the second cylindrical region,
The diameter range of second cylindrical region is 5-15um.
7. chip according to claim 1, which is characterized in that the cross-sectional area of the light hole is less than second electric current
The cross-sectional area of injection zone.
8. chip according to claim 1, which is characterized in that the luminescent layer is quantum well structure.
9. chip according to claim 1, which is characterized in that the thickness range of second current-limiting layer is 20-
40nm。
10. a kind of preparation method of the vertical cavity surface emitting laser chip of multilayer current limliting characterized by comprising
N-type layer and luminescent layer are sequentially formed on substrate；
The first current-limiting layer is formed on the light-emitting layer, ion implanting is carried out to first current-limiting layer, so that not
The region of injection forms the first current injection area domain；
Form the second current-limiting layer on first current-limiting layer so that second current-limiting layer formed with it is described
First corresponding second current injection area in current injection area domain domain, and the cross-sectional area in first current injection area domain is less than institute
State the cross-sectional area in the second current injection area domain；
P-type layer and P-type electrode layer are sequentially formed on second current-limiting layer, so that the P-type electrode layer is formed and institute
State the corresponding light hole in the second current injection area domain；
N-type electrode layer is formed in the substrate back.
Priority Applications (1)
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109713566A (en) * | 2019-03-01 | 2019-05-03 | 厦门乾照半导体科技有限公司 | A kind of VCSEL array structure and preparation method thereof |
| CN110148885A (en) * | 2019-06-13 | 2019-08-20 | 海南师范大学 | A kind of vertical cavity surface emitting laser of horizontal air column current injection aperture structure |
| CN114300939A (en) * | 2021-12-28 | 2022-04-08 | 北京工业大学 | A kind of high beam quality VCSEL structure and preparation method |
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| US20050078726A1 (en) * | 2003-10-10 | 2005-04-14 | Sony Corporation | Vertical-cavity surface-emitting laser device array and method of manufacturing the same |
| CN1901299A (en) * | 2005-07-22 | 2007-01-24 | 海德威电子工业股份有限公司 | Vertical cavity surface emitting laser and method of manufacturing the same |
| CN208890097U (en) * | 2018-10-16 | 2019-05-21 | 厦门乾照半导体科技有限公司 | A kind of the vertical cavity surface emitting laser chip and laser of multilayer current limliting |
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| US20050078726A1 (en) * | 2003-10-10 | 2005-04-14 | Sony Corporation | Vertical-cavity surface-emitting laser device array and method of manufacturing the same |
| CN1901299A (en) * | 2005-07-22 | 2007-01-24 | 海德威电子工业股份有限公司 | Vertical cavity surface emitting laser and method of manufacturing the same |
| CN208890097U (en) * | 2018-10-16 | 2019-05-21 | 厦门乾照半导体科技有限公司 | A kind of the vertical cavity surface emitting laser chip and laser of multilayer current limliting |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109713566A (en) * | 2019-03-01 | 2019-05-03 | 厦门乾照半导体科技有限公司 | A kind of VCSEL array structure and preparation method thereof |
| CN110148885A (en) * | 2019-06-13 | 2019-08-20 | 海南师范大学 | A kind of vertical cavity surface emitting laser of horizontal air column current injection aperture structure |
| CN110148885B (en) * | 2019-06-13 | 2024-05-03 | 海南师范大学 | Vertical cavity surface emitting laser with horizontal air column current injection aperture structure |
| CN114300939A (en) * | 2021-12-28 | 2022-04-08 | 北京工业大学 | A kind of high beam quality VCSEL structure and preparation method |
| CN114300939B (en) * | 2021-12-28 | 2022-12-02 | 北京工业大学 | A VCSEL structure and preparation method with high beam quality |
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