CN109065613B - A kind of manufacturing method of vertical structure germanium channel field effect transistor device - Google Patents

Abstract

The invention discloses a manufacturing method of a vertical structure germanium channel field effect transistor device. First, a germanium film and a nickel film are deposited on the substrate, and a nickel-germanium alloy film is formed by annealing as the source electrode of the device; secondly, a first insulating layer film, a hafnium nitride film and a second insulating layer film are deposited on the source electrode; The first insulating layer film, the hafnium nitride film and the second insulating layer film are etched to form a channel hole, and the hafnium nitride on the inner wall of the channel hole is oxidized to generate hafnium oxynitride or hafnium oxide, which is used as the gate insulating layer of the device; Amorphous germanium is deposited in the channel holes, and the germanium is crystallized to form the channel of the device by annealing; finally, a nickel film is deposited over the channel and annealed to form a nickel-germanium alloy as the drain of the device. The invention adopts the method of firstly preparing the gate stack and then preparing the channel, which fully reduces the technological difficulty in the process of preparing the vertical structure device, reduces the process cost, and the prepared device has the advantages of large driving current and high integration density.

Description

A kind of manufacturing method of vertical structure germanium channel field effect transistor device

technical field

The invention belongs to the field of semiconductor devices, and relates to a manufacturing method of a high-performance vertical structure germanium channel field effect transistor device.

Background technique

Silicon channel field effect transistor (Si MOSFET) is the most basic unit of modern integrated circuits, and is the basis for integrated circuits to realize functions such as operation and storage. The most important indicator to measure the performance of a MOSFET device is the turn-on current of the device, and the performance of the device can be improved by reducing the channel length of the MOSFET device. After half a century of technological progress, the feature size of MOSFET devices is getting smaller and smaller, and the channel length of the current mass-produced MOSFET devices has reached 20nm. The method of further reducing the size of the device will result in severe short-channel effect, making it difficult to further improve the performance of the integrated circuit. To solve this problem, germanium channel MOSFET (Ge MOSFET) device technology has been proposed. Taking advantage of the higher carrier mobility of germanium than silicon, the performance of MOSFET devices can be continuously improved without shrinking the device size. Major enterprises and scientific research institutions at home and abroad have regarded Ge MOSFET device technology as one of the candidates for the next generation of high-performance integrated circuit devices. After rapid development in recent years, Ge MOSFET device technology has made significant progress, mainly reflected in the device's turn-on current has been significantly higher than the traditional Si MOSFET device, showing the broad application prospects of GeMOSFET device technology.

In addition to increasing the turn-on current of a larger device, improving the integration of the device is also an effective means to obtain higher integrated circuit performance. In a traditional MOSFET device, the channel is parallel to the surface of the substrate. Since the area of the source, drain, channel and other regions of the device cannot be continuously reduced, the integration density of the MOSFET device is limited. Using a MOSFET device with a vertical structure (the channel is perpendicular to the surface of the substrate) can fully reduce the projected area of the device and improve the integration degree of the device. The source, channel and drain regions of the vertical structure germanium channel field effect transistor are stacked from bottom to top, and the gate stack surrounds the periphery of the vertical channel. Such structural characteristics make it difficult to form a germanium channel field effect transistor with a vertical structure in the traditional method of fabricating the channel first and then fabricating the gate stack. Therefore, the present invention proposes a method for preparing the gate stack first and then preparing the channel, so as to realize the preparation of the vertical structure germanium channel field effect transistor.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a manufacturing method of a germanium channel effect transistor device based on a vertical channel structure in view of the deficiencies of the existing silicon channel field effect transistor device.

The object of the present invention is achieved through the following technical solutions: a manufacturing method of a vertical structure germanium channel field effect transistor device, the method comprises the following steps:

(1) depositing a germanium film and a nickel film in turn on the substrate, and forming a nickel-germanium alloy film by annealing as the source electrode of the device;

(2) sequentially depositing the first insulating layer film, the hafnium nitride film and the second insulating layer film on the source electrode;

(3) Etch the first insulating layer film, the hafnium nitride film and the second insulating layer film to form a channel hole, and oxidize the hafnium nitride on the inner wall of the channel hole to generate hafnium oxynitride or hafnium oxide, which is used as the gate insulation of the device Floor;

(4) depositing amorphous germanium in the channel hole, and crystallizing the germanium to form the channel of the device by annealing;

(5) A nickel film is deposited over the channel and annealed to form a nickel-germanium alloy as the drain of the device, and finally a vertical structure germanium channel field effect transistor device is formed.

Further, the substrate materials include but are not limited to silicon, silicon oxide deposited on the surface of silicon, quartz, and sapphire; the materials of the first insulating layer and the second insulating layer include but are not limited to silicon oxide, silicon nitride, aluminum oxide and hafnium oxide.

Further, in the step (1), the method for depositing the germanium film and the nickel film is thermal evaporation or sputtering; the annealing method is thermal annealing, flash lamp annealing or laser annealing; in the step (2), depositing the first The method of the first insulating layer and the second insulating layer is atomic layer deposition; the method of depositing the hafnium nitride thin film is atomic layer deposition or sputtering.

Further, in the step (2), the method for etching the first insulating layer, the hafnium nitride thin film and the second insulating layer to form the channel holes is reactive ion etching.

Further, in the step (3), the method for oxidizing the hafnium nitride on the inner wall of the channel hole is thermal oxidation or ozone oxidation.

Further, in the step (4), the method of depositing amorphous germanium in the channel hole is thermal evaporation, sputtering or chemical vapor deposition; the method of annealing to crystallize germanium is thermal annealing, flash lamp annealing or laser annealing.

Further, in the step (5), the method of depositing the nickel film is thermal evaporation or sputtering; the method of annealing is thermal annealing, flash lamp annealing or laser annealing.

Further, in the step (2), the thickness of the hafnium nitride film is 20 to 500 nanometers, and the thicknesses of the first insulating layer and the second insulating layer are both 5 to 10 nanometers; in the step (3), the gate insulating layer is The thickness is 2 to 20 nanometers.

Further, in the step (3), the channel hole is cylindrical with a diameter of 10 to 25 nanometers.

Further, in the step (5), the lower surface of the drain electrode is not higher than the upper surface of the second insulating layer.

The beneficial effects of the present invention are: 1. The germanium channel can obtain a larger driving current without changing the size of the device and improve the performance of the device; The integration density of large devices can obtain high-performance integrated circuits; 3. First, the hafnium nitride film is deposited as a metal gate, and then the hafnium nitride film is etched to form a channel hole, and the hafnium nitride on the inner wall of the channel hole is oxidized to form a gate. The insulating layer is used to obtain the gate stack of the device, and finally germanium is deposited in the channel hole to obtain the channel of the device; by the above method of first preparing the gate stack and then preparing the channel, the vertical preparation method is fully reduced. The process difficulty in the process of structuring the device reduces the process cost. The present invention utilizes the germanium channel of the vertical structure, and has the advantages of high carrier mobility, small device projection area, high integration, and compatibility with the existing integrated circuit manufacturing process, etc. The field has broad application prospects.

Description of drawings

Figure 1(a) is a schematic diagram of growing a germanium film and a first nickel film on a substrate;

Fig. 1(b) is a schematic diagram of the source electrode of the device where the germanium film and the first nickel film are reacted by annealing to form a nickel-germanium alloy;

Figure 2 (a) is a schematic diagram of growing a first insulating layer, a hafnium nitride film and a second insulating layer on the surface of the nickel-germanium alloy film;

FIG. 2(b) is a schematic diagram illustrating the formation of channel holes by etching the second insulating layer, the hafnium nitride film and the first insulating layer;

FIG. 2(c) is a schematic diagram illustrating the formation of a hafnium oxynitride or hafnium oxide gate insulating layer by oxidizing the inner wall of the channel hole;

Figure 3(a) is a schematic diagram of depositing amorphous germanium in a channel hole;

Figure 3(b) is a schematic diagram of a channel formed by annealing amorphous germanium to form a device;

Figure 4 (a) is a schematic diagram of depositing a second nickel film on the channel;

FIG. 4(b) is a schematic diagram of the drain electrode of the device using annealing to make the second nickel film react with germanium in the channel to form a nickel-germanium alloy;

5 is a structural diagram of a vertical structure germanium channel field effect transistor device;

In the figure, quartz substrate 10, germanium film 11, first nickel film 12, source electrode 13, first insulating layer 20, hafnium nitride film 21, second insulating layer 22, gate insulating layer 23, amorphous germanium 30, Channel 31 , second nickel film 40 , drain 41 .

Detailed ways

The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

A manufacturing method of a vertical structure germanium channel field effect transistor device provided by the present invention comprises the following steps:

(1) depositing a germanium film and a first nickel film in turn on the substrate, and forming a nickel-germanium alloy film by annealing as the source of the device;

(2) sequentially depositing the first insulating layer film, the hafnium nitride film and the second insulating layer film on the source electrode;

(3) Etch the first insulating layer film, the hafnium nitride film and the second insulating layer film to form a channel hole, and oxidize the hafnium nitride on the inner wall of the channel hole to generate hafnium oxynitride or hafnium oxide, which is used as the gate insulation of the device Floor;

(4) depositing amorphous germanium in the channel hole, and crystallizing the germanium to form the channel of the device by annealing;

(5) depositing a second nickel film over the channel and annealing to form a nickel-germanium alloy as the drain of the device, finally forming a vertical structure germanium channel field effect transistor device.

Further, the substrate material includes but is not limited to silicon, silicon oxide deposited on the surface of silicon, quartz, and sapphire.

Further, the thickness of the hafnium nitride thin film is 20 to 500 nanometers.

Further, the materials of the first insulating layer and the second insulating layer include but are not limited to silicon oxide, silicon nitride, aluminum oxide and hafnium oxide, and have a thickness of 5 to 10 nanometers.

Further, the channel hole is cylindrical with a diameter of 10 to 25 nanometers.

Further, the thickness of the gate insulating layer is 2 to 20 nanometers.

Further, in the step (1), the method for depositing the germanium film and the nickel film is thermal evaporation or sputtering; the annealing method is thermal annealing, flash lamp annealing or laser annealing.

Further, in the step (2), the method for depositing the first insulating layer and the second insulating layer is atomic layer deposition; the method for depositing the hafnium nitride thin film is atomic layer deposition or sputtering.

Further, in the step (2), the method for etching the first insulating layer, the hafnium nitride thin film and the second insulating layer to form the channel holes is reactive ion etching.

Further, in the step (3), the method for oxidizing the hafnium nitride on the inner wall of the channel hole is thermal oxidation or ozone oxidation.

Further, in the step (4), the method of depositing amorphous germanium in the channel hole is thermal evaporation, sputtering or chemical vapor deposition; the method of annealing to crystallize germanium is thermal annealing, flash lamp annealing or laser annealing;

Further, in the step (5), the method for depositing the second nickel film is thermal evaporation or sputtering; the annealing method is thermal annealing, flash lamp annealing or laser annealing.

Embodiment 1: In this embodiment, a quartz substrate is used, and the preparation method of the vertical structure germanium channel field effect transistor device is as follows:

(1) As shown in FIG. 1( a ), a germanium film 11 is deposited on the quartz substrate 10 , and the deposition method is chemical vapor deposition, thermal evaporation or sputtering; a first nickel film 12 is deposited on the germanium film 11 and deposited The method is chemical vapor deposition, thermal evaporation or sputtering; the thickness of the germanium film 11 is the same as that of the first nickel film 12;

(2) As shown in FIG. 1(b), the germanium film 11 and the first nickel film 12 are reacted by annealing to form a nickel-germanium alloy as the source electrode 13 of the device; the annealing method is thermal annealing, flash lamp annealing or laser annealing;

(3) As shown in FIG. 2( a ), sequentially deposit a first insulating layer 20 , a hafnium nitride film 21 and a second insulating layer 22 on the source electrode 13 ; the materials of the first insulating layer 20 and the second insulating layer 22 Including but not limited to silicon oxide, silicon nitride, aluminum oxide and hafnium oxide, the thickness is 5 to 10 nanometers, and the deposition method is atomic layer deposition; the thickness of the hafnium nitride film 21 is 20 to 500 nanometers, and the deposition method is atomic layer deposition or sputtering;

(4) As shown in FIG. 2(b), the second insulating layer 22, the hafnium nitride film 21 and the first insulating layer 20 are etched until the surface of the source electrode 13 is etched to form a channel hole, and the channel hole is preferably cylindrical, Its diameter is 10 to 25 nanometers, but the shape is not limited to cylindrical, for example, rectangular and irregular shapes can be realized, and the etching method is reactive ion etching;

(5) as shown in Fig. 2 (c), oxidize the hafnium nitride of the inner wall of the channel hole to form hafnium oxynitride or hafnium oxide thin film as the gate insulating layer 23 of the device; the oxidation method is thermal oxidation or ozone oxidation;

(6) As shown in FIG. 3(a), amorphous germanium 30 is deposited in the channel hole, and the upper surface of the amorphous germanium 30 is higher than the upper surface of the second insulating layer 22; the deposition method is chemical vapor deposition, thermal evaporation plating or sputtering;

(7) As shown in FIG. 3(b), annealing crystallizes amorphous germanium 30 to form single crystal germanium as the channel 31 of the device; the annealing method is thermal annealing, flash lamp annealing or laser annealing;

(8) As shown in FIG. 4(a), a second nickel film 40 is deposited on the surface of the channel 31, and the deposition method is thermal evaporation or sputtering;

(9) As shown in FIG. 4(b), annealing makes the second nickel film 40 react with germanium in the channel 31 to form a nickel-germanium alloy, which is used as the drain 41 of the device; the lower surface of the drain 41 is not higher than the second The upper surface of the insulating layer 22; the annealing method is rapid thermal annealing, flash lamp annealing or laser annealing;

(10) FIG. 5 is the finally obtained vertical structure germanium channel field effect transistor device.

The above-mentioned embodiments are used to explain the present invention, rather than limit the present invention. Within the spirit of the present invention and the protection scope of the claims, any modifications and changes made to the present invention all fall into the protection scope of the present invention.

Claims (10)

1. A method of fabricating a vertical structure ge-channel field effect transistor device, the method comprising the steps of:

(1) sequentially depositing a germanium film and a nickel film on a substrate, and annealing to form a nickel-germanium alloy film as a source electrode of the device;

(2) depositing a first insulating layer film, a hafnium nitride film and a second insulating layer film on the source electrode in sequence;

(3) etching the first insulating layer film, the hafnium nitride film and the second insulating layer film to form a channel hole, and oxidizing hafnium nitride on the inner wall of the channel hole to generate hafnium oxynitride or hafnium oxide serving as a gate insulating layer of the device;

(4) depositing amorphous germanium in the channel hole, and crystallizing the germanium to form a channel of the device through annealing;

(5) and depositing a nickel film above the channel and annealing to form a nickel-germanium alloy as a drain electrode of the device, and finally forming the germanium channel field effect transistor device with the vertical structure.

2. The method of fabricating a vertical structure germanium channel field effect transistor device as claimed in claim 1 wherein the substrate material includes but is not limited to silicon, silicon surface deposited silicon oxide, quartz, sapphire; the materials of the first and second insulating layers include, but are not limited to, silicon oxide, silicon nitride, aluminum oxide, and hafnium oxide.

3. The method for manufacturing a vertical structure germanium channel field effect transistor device according to claim 1, wherein in the step (1), the method for depositing the germanium thin film and the nickel thin film is thermal evaporation or sputtering; the annealing method comprises thermal annealing, flash lamp annealing or laser annealing; in the step (2), the method for depositing the first insulating layer and the second insulating layer is atomic layer deposition; the method for depositing the hafnium nitride film is atomic layer deposition or sputtering.

4. The method for manufacturing a vertical structure germanium channel field effect transistor device according to claim 1, wherein in the step (3), the method for etching the first insulating layer, the hafnium nitride film and the second insulating layer to form the channel hole is reactive ion etching.

5. The method for manufacturing a vertical structure germanium channel field effect transistor device according to claim 1, wherein in the step (3), the method for oxidizing the hafnium nitride on the inner wall of the channel hole is thermal oxidation or ozone oxidation.

6. The method for manufacturing a vertical structure germanium channel field effect transistor device according to claim 1, wherein in the step (4), the method for depositing the amorphous germanium in the channel hole is thermal evaporation, sputtering or chemical vapor deposition; the method for crystallizing germanium by annealing is thermal annealing, flash lamp annealing or laser annealing.

7. The method for manufacturing a vertical structure germanium channel field effect transistor device according to claim 1, wherein in the step (5), the method for depositing the nickel thin film is thermal evaporation or sputtering; the annealing method is thermal annealing, flash lamp annealing or laser annealing.

8. The method for manufacturing a vertical structure germanium channel field effect transistor device according to claim 1, wherein the thickness of the hafnium nitride film in the step (2) is 20 to 500 nm, and the thickness of each of the first insulating layer and the second insulating layer is 5 to 10 nm; the thickness of the gate insulating layer in the step (3) is 2 to 20 nanometers.

9. The method of claim 1, wherein the channel hole in step (3) is cylindrical and has a diameter of 10 to 25 nm.

10. The method of manufacturing a vertical structure germanium channel field effect transistor device according to claim 1, wherein in the step (5), the lower surface of the drain electrode is not higher than the upper surface of the second insulating layer.

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