CN108493112A - A kind of manufacturing method of laminated type polysilicon fet device - Google Patents

Abstract

The invention discloses a method for manufacturing a laminated polysilicon field effect transistor device. First, alternately deposit the isolation layer film and the amorphous silicon film on the insulating substrate to form a laminated structure of the isolation layer film and the amorphous silicon film; secondly, etch the isolation layer film and the amorphous silicon film to form the channel region of the device, And depositing heavily doped amorphous silicon on both sides of the channel region to form the source and drain regions of the device; then annealing the crystallization of the amorphous silicon in the channel region and the source and drain regions to polysilicon, and etching to remove the isolation layer film; Finally, a gate insulating layer and a metal gate layer are sequentially deposited on the surface of the channel region and the source and drain regions, and the gate region is formed by etching the gate insulating layer and the metal gate layer, and finally a stacked polysilicon field effect transistor device is formed. The invention has the advantages of large driving current, small device size, compatibility with the existing polysilicon field effect transistor manufacturing process, and the like, and has broad application prospects in the fields of flexible electronics, transparent display, and on-screen systems.

Description

A method for manufacturing a stacked polysilicon field effect transistor device

technical field

The invention belongs to the field of semiconductor devices and relates to a method for manufacturing a high-performance polysilicon field effect transistor device.

Background technique

Polysilicon field effect transistor devices have the advantages of freedom of substrate selection and are suitable for large-scale preparation. They are widely used in flexible electronic products, transparent displays, and System-on-Panel (SoP) and other fields, and have huge market prospects.

Due to the carrier scattering effect caused by grain boundaries in the polysilicon field effect transistor device, the carrier mobility in the device is low. In order to increase the driving current of the polysilicon field effect transistor device, the method of increasing the channel width of the device is generally adopted, but the increase of the channel width of the device brings great defects to both flexible electronic products and transparent displays. For example, for flexible electronic products, since the silicon material itself is a brittle material, the increase of the device area will lead to a decrease in the bending resistance of the product; for the application of transparent display, the silicon material is opaque in the visible light band, so The increase in the device area will lead to a decrease in the area ratio of the light-emitting area on the display screen. To maintain the same luminous intensity without changing the screen area, a certain resolution needs to be sacrificed. Therefore, how to increase the driving current of the device without increasing the channel width of the polysilicon field effect transistor device is the key to realizing high-performance flexible electronic products, transparent display products and on-screen systems.

Contents of the invention

The object of the present invention is to provide a method for manufacturing a polysilicon field effect transistor device based on a stacked structure to address the shortcomings of the existing polysilicon thin film transistor device.

The purpose of the present invention is achieved by the following technical solutions: a method for manufacturing a stacked polysilicon field effect transistor device, the method comprising the steps of:

(1) Alternately depositing the isolation layer film and the amorphous silicon film on the insulating substrate to form a laminated structure of the isolation layer film and the amorphous silicon film;

(2) etching the isolation layer film and the amorphous silicon film to form the channel region of the device, and depositing heavily doped amorphous silicon on both sides of the channel region to form the source and drain regions of the device;

(3) Transform the crystallization of amorphous silicon in the channel region and the source and drain region into polysilicon by annealing, and etch and remove the isolation layer film;

(4) A gate insulating layer and a metal gate layer are sequentially deposited on the surface of the channel region and the source and drain regions, and the gate region is formed by etching the gate insulating layer and the metal gate layer, and finally a stacked polysilicon field effect transistor device is formed.

Further, the insulating substrate material includes, but is not limited to, silicon oxide deposited on the surface of silicon, silicon nitride deposited on the surface of silicon, quartz, sapphire, and flexible polymer materials.

Further, the number of layers of the polysilicon film in the channel region is 2 to 16 layers.

Further, the polysilicon film in the channel region has a thickness of 3 to 20 nanometers.

Further, the material of the gate insulating layer includes but not limited to silicon oxide, silicon nitride, aluminum oxide, and hafnium oxide.

Further, the gate insulating layer has a thickness of 1 to 100 nanometers.

Further, the doping concentration of the heavily doped amorphous silicon is 10 ¹⁹ per cubic centimeter to 10 ²¹ per cubic centimeter.

Further, in the step (2), the method of etching the isolation layer film and the amorphous silicon film is reactive ion etching; in the step (4), the method of etching the gate insulating layer and the metal gate layer is reaction ion etching.

Further, in the step (2), the method of depositing heavily doped amorphous silicon on both sides of the channel region is sputtering, chemical vapor deposition or molecular beam epitaxy.

Further, in the step (3), the annealing method is rapid thermal annealing, flash lamp annealing or laser annealing.

The beneficial effects of the present invention are: the polysilicon field effect transistor device of the present invention adopts a stacked structure, which has the following advantages compared with the traditional polysilicon thin film transistor: 1. The stacked structure can be used without increasing the channel width of the device. By increasing the number of channel layers, the effective width of the device channel is increased, and a larger drive current is realized in the device, which avoids the decrease in the bending resistance of the flexible electronic system and the light transmission of the transparent electronic system caused by the increase in the device area. 2. Improve the performance by changing the structure of the device, avoiding the introduction of new materials in the device, and making the device manufacturing process compatible with the existing production process as much as possible; The disadvantage of low carrier mobility can improve the driving current of polysilicon field effect transistor devices, which has the advantages of large driving current, small device size, and compatibility with existing polysilicon field effect transistor manufacturing processes. It is used in flexible electronics, transparent displays and screens. System and other fields have broad application prospects.

Description of drawings

Fig. 1 (a) is a schematic diagram of growing a first isolation layer film and a first amorphous silicon film on an insulating substrate;

Fig. 1 (b) is a schematic diagram of growing a second isolation layer film and a second amorphous silicon film;

Fig. 2 (a) is a schematic diagram of etching an amorphous silicon film and an isolation layer film to form a channel region;

Figure 2(b) is a schematic diagram of depositing heavily doped amorphous silicon on both sides of the channel region to form source and drain regions;

Figure 3(a) is a schematic diagram of depositing a protective insulating layer;

Figure 3(b) is a schematic diagram of transforming amorphous silicon into polysilicon by annealing to form a polysilicon channel region and source and drain regions;

Figure 3 (c) is a schematic diagram of etching and removing the protective insulating layer and the isolation layer film;

Figure 4(a) is a schematic cross-sectional view along the channel length of the device after depositing a gate insulating layer on the surface of the channel region and the source and drain regions;

Figure 4(b) is a schematic cross-sectional view along the channel width direction of the device after depositing a gate insulating layer on the surface of the channel region and the source and drain regions;

Figure 5(a) is a schematic cross-sectional view along the device channel length direction after depositing a metal gate layer on the surface of the gate insulating layer;

Figure 5(b) is a schematic cross-sectional view along the device channel width direction after depositing a metal gate layer on the surface of the gate insulating layer;

Figure 6(a) is a schematic cross-sectional view along the channel length direction of the device after etching the metal gate layer and the gate insulating layer to form the gate region of the device;

Figure 6(b) is a schematic cross-sectional view along the channel width direction of the device after etching the metal gate layer and the gate insulating layer to form the gate region of the device;

In the figure, a quartz substrate 10, a first isolation layer film 11, a first amorphous silicon film 12, a second isolation layer film 13, a second amorphous silicon film 14, a heavily doped amorphous silicon layer 20, and a protective insulating layer 30 , heavily doped polysilicon 31 , a first polysilicon channel 32 , a second polysilicon channel 33 , a gate insulating layer 40 , and a metal gate layer 41 .

Detailed ways

The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments.

A method for manufacturing a stacked polysilicon field effect transistor device provided by the present invention comprises the following steps:

(1) Alternately depositing the isolation layer film and the amorphous silicon film on the insulating substrate to form a laminated structure of the isolation layer film and the amorphous silicon film;

(2) etching the isolation layer film and the amorphous silicon film to form the channel region of the device, and depositing heavily doped amorphous silicon on both sides of the channel region to form the source and drain regions of the device;

(3) Transform the crystallization of amorphous silicon in the channel region and the source and drain region into polysilicon by annealing, and etch and remove the isolation layer film;

(4) A gate insulating layer and a metal gate layer are sequentially deposited on the surface of the channel region and the source and drain regions, and the gate region is formed by etching the gate insulating layer and the metal gate layer, and finally a stacked polysilicon field effect transistor device is formed.

Further, the insulating substrate material includes, but is not limited to, silicon oxide deposited on the surface of silicon, silicon nitride deposited on the surface of silicon, quartz, sapphire, and flexible polymer materials.

Further, the number of layers of the polysilicon film in the channel region is 2 to 16 layers.

Further, the polysilicon film in the channel region has a thickness of 3 to 20 nanometers.

Further, the material of the gate insulating layer includes but not limited to silicon oxide, silicon nitride, aluminum oxide, and hafnium oxide.

Further, the gate insulating layer has a thickness of 1 to 100 nanometers.

Further, the doping concentration of the heavily doped amorphous silicon is 10 ¹⁹ per cubic centimeter to 10 ²¹ per cubic centimeter.

Further, in the step (2), the method of etching the isolation layer film and the amorphous silicon film is reactive ion etching; in the step (4), the method of etching the gate insulating layer and the metal gate layer is reaction ion etching.

Further, in the step (2), the method of depositing heavily doped amorphous silicon on both sides of the channel region is sputtering, chemical vapor deposition or molecular beam epitaxy.

Further, in the step (3), the annealing method is rapid thermal annealing, flash lamp annealing or laser annealing.

Embodiment 1: In this embodiment, a quartz substrate is adopted, and the channel stacking number of the stacked polysilicon field effect transistor device is 2 layers, and the preparation method is as follows:

(1) As shown in Figure 1 (a), deposit the first spacer film 11 on the quartz substrate 10, the deposition method is chemical vapor deposition, atomic layer deposition, thermal evaporation or sputtering; Depositing the first amorphous silicon film 12 on the 11, the deposition method is chemical vapor deposition, thermal evaporation or sputtering, and the thickness is 3 nanometers to 20 nanometers;

(2) As shown in Fig. 1 (b), on the first amorphous silicon film 12, deposit the second spacer film 13, the deposition method is chemical vapor deposition, atomic layer deposition, thermal evaporation or sputtering; Depositing a second amorphous silicon film 14 on the isolation layer film 13, the deposition method is chemical vapor deposition, thermal evaporation or sputtering, and the thickness is 3 nanometers to 20 nanometers;

(3) As shown in Figure 2(a), etch the second amorphous silicon film 14, the second spacer film 13, the first amorphous silicon film 12 and the first spacer film 11 to form the channel region of the device , the etching method is reactive ion etching;

(4) As shown in Figure 2(b), heavily doped amorphous silicon 20 is deposited on both sides of the channel region to form the source and drain regions of the device, and the doping concentration of the heavily doped amorphous silicon 20 is 10 ¹⁹ per cubic centimeter to 10 ²¹ per cubic centimeter, the upper surface of the heavily doped amorphous silicon 20 is higher than the upper surface of the second amorphous silicon film 14, and the deposition method is sputtering, chemical vapor deposition or molecular beam epitaxy;

(5) As shown in FIG. 3(a), deposit a protective insulating layer 30 on the surface of the channel region and the source-drain region. The deposition method is chemical vapor deposition or atomic layer deposition, and the thickness is 10 nanometers to 500 nanometers;

(6) As shown in Figure 3(b), the crystallization of the heavily doped amorphous silicon 20 in the source and drain regions is transformed into heavily doped polysilicon 31 by annealing, and the crystallization transformation of the first amorphous silicon thin film 12 in the channel region The crystallization of the first polysilicon channel 32 and the second amorphous silicon thin film 14 in the channel region is transformed into the second polysilicon channel 33, and the annealing method is rapid thermal annealing, flash lamp annealing or laser annealing;

(7) As shown in FIG. 3(c), the protective insulating layer 30, the second isolation layer film 13 and the first isolation layer film 11 are removed by etching, and the etching method is reactive ion etching;

(8) As shown in Figure 4(a) and Figure 4(b), a gate insulating layer 40 is deposited on the surface of the channel region and the source and drain regions, and the material of the gate insulating layer 40 is silicon oxide, silicon nitride, aluminum oxide or Hafnium oxide, deposited by atomic layer deposition or chemical vapor deposition, with a thickness of 1 nm to 100 nm;

(9) As shown in FIG. 5(a) and FIG. 5(b), deposit a metal gate layer 41 on the surface of the gate insulating layer 40, the deposition method is chemical vapor deposition or atomic layer deposition, and the thickness is 10 to 200 nanometers;

(10) As shown in Figure 6(a) and Figure 6(b), etch the metal gate layer 41 and the gate insulating layer 40 to the surface of the source and drain regions to form the gate region of the device, and the edge of the gate region is not smaller than the trench The edge of the channel area is etched by reactive ion etching.

Claims (10)

1. a kind of manufacturing method of laminated type polysilicon fet device, which is characterized in that this method includes following step Suddenly：

(1) alternating deposit isolated layer film and amorphous silicon membrane successively on an insulating substrate, form isolated layer film and non-crystalline silicon The laminated construction of film；

(2) it etches isolated layer film and amorphous silicon membrane forms the channel region of device, and is heavily doped in channel region both sides deposition Miscellaneous non-crystalline silicon forms the source and drain areas of device；

(3) so that the recrystallized amorphous silicon in channel region and source and drain areas is changed into polysilicon by annealing, and etch removing isolation Layer film；

(4) it is sequentially depositing gate insulation layer and Metal gate layer in channel region and source drain region surface, and passes through gate insulator layer Area of grid is formed with Metal gate layer, ultimately forms laminated type polysilicon fet device.

2. the manufacturing method of laminated type polysilicon fet device according to claim 1, which is characterized in that absolutely Edge substrate material is including but not limited to silicon face cvd silicon oxide, silicon face deposited silicon nitride, quartz, sapphire, flexible high score Sub- material.

3. the manufacturing method of laminated type polysilicon fet device according to claim 1, which is characterized in that institute The number of plies for stating the polysilicon membrane in channel region is 2 to 16 layers.

4. the manufacturing method of laminated type polysilicon fet device according to claim 1, which is characterized in that institute The thickness for stating the polysilicon membrane in channel region is 3 to 20 nanometers.

5. the manufacturing method of laminated type polysilicon fet device according to claim 1, which is characterized in that institute The material of gate insulation layer is stated including but not limited to silica, silicon nitride, aluminium oxide, hafnium oxide.

6. the manufacturing method of laminated type polysilicon fet device according to claim 1, which is characterized in that institute The thickness for stating gate insulation layer is 1 to 100 nanometer.

7. the manufacturing method of laminated type polysilicon fet device according to claim 1, which is characterized in that institute The doping concentration for stating heavily doped amorphous silicon is 10¹⁹It is per cubic centimeter to 10²¹It is per cubic centimeter.

8. the manufacturing method of laminated type polysilicon fet device according to claim 1, which is characterized in that institute It states in step (2), the method for etching isolated layer film and amorphous silicon membrane is reactive ion etching；In the step (4), etching The method of gate insulation layer and Metal gate layer is reactive ion etching.

9. the manufacturing method of laminated type polysilicon fet device according to claim 1, which is characterized in that institute It states in step (2), is outside sputtering, chemical vapor deposition or molecular beam in the method for channel region both sides deposition of heavily doped non-crystalline silicon Prolong.

10. the manufacturing method of laminated type polysilicon fet device according to claim 1, which is characterized in that In the step (3), the method for annealing is rapid thermal annealing, flash lamp annealing or laser annealing.