CN109003989B - Array substrate, preparation method thereof, display panel and display device - Google Patents

Abstract

The invention discloses an array substrate and a preparation method thereof, a display panel and a display device, and relates to the field of display technology. A display area and a non-display area are provided. The display area includes an opening area and a non-opening area, including: a base substrate; a buffer layer covering the first surface of the base substrate; a first isolation layer covering the surface of the first buffer layer away from the base substrate; a second buffer layer covering the surface of the first isolation layer away from the base substrate; The pixel driving circuit located in the non-opening area, the pixel driving circuit is arranged on the side of the second buffer layer away from the base substrate, and includes a digging area; wherein, the first isolation layer and the second buffer layer are on the positive side of the base substrate. The projections all overlap with the digging area, and the orthographic projections of the first isolation layer and the second buffer layer on the base substrate do not overlap with the opening area. By introducing the first isolation layer, the problem of over-etching or under-etching caused in the process of digging the opening area and the digging area of the array substrate is effectively improved.

Description

Array substrate and preparation method thereof, display panel and display device

technical field

The present invention relates to the field of display technology, and more particularly, to an array substrate and a preparation method thereof, a display panel and a display device.

Background technique

In recent years, with the continuous development of liquid crystal display technology, the application fields of liquid crystal display (LCD, Liquid Crystal Display) devices, especially color liquid crystal displays, are also constantly expanding. Liquid crystal display devices have been widely used in televisions or monitors due to their superiority and high contrast in displaying moving images. In general, liquid crystal display devices utilize optical anisotropy and polarization properties of liquid crystal molecules to generate images. A liquid crystal display device generally includes a substrate and a second substrate disposed opposite to each other, and a liquid crystal layer located between the first substrate and the second substrate, and liquid crystal molecules in the liquid crystal layer are realigned by an electric field. Therefore, the orientation of the liquid crystal molecules changes according to the direction of the electric field and the light transmittance of the liquid crystal panel also changes, thereby realizing the display function of an image.

Organic electroluminescent device (OLED, Organic Light-Emitting Diode) has also become a very popular flat panel display industry at home and abroad, and has been hailed as the next-generation "star" flat panel display technology, mainly because OLED has low power consumption, self- It has the characteristics of light emission, fast response time, high luminous efficiency, thin panel thickness, large-size and flexible panels, simple process and low cost. The organic electroluminescent device includes a plurality of organic light-emitting structures, and the organic light-emitting structures include a reflective electrode (anode), a light-emitting material layer, and a semi-reflective electrode (cathode). Holes and electrons are injected into the light-emitting material layer from the anode and the cathode, respectively, and combine in the light-emitting material layer to generate excitons and generate energy when the excitons transition from an excited state to a ground state, thereby realizing light emission.

SUMMARY OF THE INVENTION

In view of this, the present invention provides an array substrate and a preparation method thereof, a display panel and a display device, wherein a first isolation layer is introduced between the pixel driving circuit and the first buffer layer, and the opening area and the digging area of the array substrate are It can be etched separately, and the problem of over-etching or under-etching caused in the process of digging grooves in the opening area and the digging area of the array substrate is effectively improved.

In a first aspect, the present application provides an array substrate, which is provided with a display area and a non-display area, the display area includes an open area and a non-open area, and the array substrate includes:

substrate substrate;

a first buffer layer covering the first surface of the base substrate;

a first isolation layer, disposed on the surface of the first buffer layer away from the base substrate;

a second buffer layer covering the surface of the first isolation layer away from the base substrate;

a pixel driving circuit located in the non-opening area, the pixel driving circuit is disposed on the side of the second buffer layer away from the base substrate, and includes a digging area;

Wherein, the orthographic projections of the first isolation layer and the second buffer layer on the base substrate both overlap with the digging region, and the first isolation layer and the second buffer layer are in the The orthographic projections on the base substrate do not overlap with the opening area.

In a second aspect, the present application provides a preparation method of an array substrate, the array substrate is provided with a display area and a non-display area, the display area includes an open area and a non-open area, and the preparation method includes:

Provide a base substrate;

making a first buffer layer, so that the first buffer layer covers the first surface of the base substrate;

making a first isolation layer, so that the first isolation layer covers the surface of the first buffer layer away from the base substrate;

forming a second buffer layer, so that the second buffer layer covers the surface of the first isolation layer away from the base substrate;

A pixel driving circuit is fabricated on the side of the second buffer layer away from the base substrate, and the opening area and the digging area are formed by step-by-step etching, and the digging area is located in the a non-open area, the orthographic projections of the first isolation layer and the second buffer layer on the base substrate are both overlapped with the digging area, and the first isolation layer and the second buffer layer are The orthographic projections of the two buffer layers on the base substrate do not overlap with the opening area.

In a third aspect, the present application provides a display panel including the array substrate provided by the present application.

In a fourth aspect, the present application provides a display device including the display panel provided by the present application.

Compared with the prior art, the array substrate and the preparation method thereof, the display panel and the display device provided by the present invention at least achieve the following beneficial effects:

In the array substrate and its preparation method, the display panel and the display device provided by the present application, the first isolation layer and the second buffer layer are introduced on the side of the first buffer layer away from the base substrate, and the holes in the pixel driving circuit are dug holes. The opening area is arranged on the side of the second buffer layer away from the base substrate and overlaps with the first isolation layer and the second buffer layer, and the opening area does not overlap with the first isolation layer and the second buffer layer. In the process of opening the area, the design of the groove needs to be carried out. After the first isolation layer is introduced in the present application, the groove etching process in the opening area and the groove etching process in the hole drilling area can be carried out separately. The etching time corresponding to the opening area is beneficial to improve the etching accuracy of the digging area and the opening area, thereby effectively avoiding the over-etching of the digging area due to the large difference between the areas of the digging area and the opening area. Or the problem of under-etching of the opening area.

Of course, any product implementing the present invention does not necessarily need to achieve all of the above-mentioned technical effects at the same time.

Other features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the present invention with reference to the accompanying drawings.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

FIG. 1 shows a top view of an array substrate according to an embodiment of the present application;

FIG. 2 shows a top view of a sub-pixel unit in an array substrate according to an embodiment of the present application;

Fig. 3 shows a kind of AA' sectional view of corresponding sub-pixel unit in Fig. 2;

Fig. 4 shows another AA' cross-sectional view of the corresponding sub-pixel unit in Fig. 2;

Figure 5 shows another AA' cross-sectional view of the corresponding sub-pixel unit in Figure 2;

Fig. 6 is a kind of BB' sectional view of the sub-pixel unit shown in Fig. 2;

FIG. 7 shows a flowchart of a method for fabricating an array substrate according to an embodiment of the present application;

FIG. 8 is a schematic diagram of forming a first buffer layer on a base substrate in a method for fabricating an array substrate provided by an embodiment of the present application;

FIG. 9 is a schematic diagram of forming a first isolation layer in a method for preparing an array substrate according to an embodiment of the present application;

FIG. 10 is a schematic diagram of forming a second buffer layer in a method for preparing an array substrate according to an embodiment of the present application;

FIG. 11 is a structural diagram of an array substrate formed by a method for preparing an array substrate provided by an embodiment of the present application;

FIG. 12 is a schematic diagram after the color resist layer and the planarization layer are formed on the basis of FIG. 11;

Figure 13 shows a flow chart of forming an opening area and a digging area by a step-by-step etching method;

FIG. 14 is a diagram showing a formation process of an array substrate in a method for preparing an array substrate provided by an embodiment of the present application;

FIG. 15 is a schematic diagram of removing the interlayer insulating layer and the gate insulating layer located in the first region by the first etching process;

16 is a schematic diagram showing the removal of the interlayer insulating layer and the gate insulating layer in the second region by a second etching process;

17 is a schematic diagram of removing the first isolation layer located in the first region by the third etching process;

18 is a schematic diagram of coating photoresist on the interlayer insulating layer;

FIG. 19 is a schematic diagram of exposing and developing the photoresist in FIG. 18;

FIG. 20 is a schematic diagram after etching the interlayer insulating layer, the gate insulating layer and the second buffer layer corresponding to the first region in FIG. 19;

FIG. 21 is a schematic diagram after ashing of the photoresist in FIG. 20;

FIG. 22 is a schematic diagram showing the etching of the interlayer insulating layer and the gate insulating layer corresponding to the second region;

FIG. 23 is a schematic diagram of etching the first isolation layer by the third etching process;

Fig. 24 is a schematic diagram of forming a semiconductor active layer after removing all photoresist on the basis of Fig. 23;

FIG. 25 shows a schematic diagram of a display panel provided by an embodiment of the present application;

FIG. 26 is a schematic diagram of a display device according to an embodiment of the present application.

Detailed ways

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the invention unless specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification.

In all examples shown and discussed herein, any specific values should be construed as illustrative only and not limiting. Accordingly, other instances of the exemplary embodiment may have different values.

It should be noted that like numerals and letters refer to like items in the following figures, so once an item is defined in one figure, it does not require further discussion in subsequent figures.

In the prior art, in order to improve the transmittance of the display panel, a trench design is usually performed in the pixel opening area of the array substrate. Since the pixel driving circuit on the array substrate usually includes a hole area, the hole area is also Formed by grooved design. Since the area of the grooved area corresponding to the opening area is much larger than the area of the grooved area corresponding to the holed area, the etching process is usually carried out at the same time. The grooving area makes the reaction speed much faster than that of the digging area, so that the etching time corresponding to the opening area and the digging area is very different, so the etching time cannot be accurately controlled, which may lead to under-etching in the digging area. phenomenon or lead to the phenomenon of over-etching in the opening area.

In view of this, the present invention provides an array substrate and a preparation method thereof, a display panel and a display device, wherein a first isolation layer is introduced between the pixel driving circuit and the first buffer layer, and the opening area and the digging area of the array substrate are It can be etched separately, and the problem of over-etching or under-etching caused in the process of digging grooves in the opening area and the digging area of the array substrate is effectively improved.

1 shows a top view of an array substrate provided by an embodiment of the present application, FIG. 2 is a top view of a sub-pixel unit in an array substrate provided by an embodiment of the present application, and FIG. 2 is an AA' cross-sectional view of the corresponding sub-pixel unit. With reference to FIGS. 1 to 3, an embodiment of the present application provides an array substrate 100, which is provided with a display area 11 and a non-display area 12. The display area 11 includes The open area 21 and the non-open area 22, the array substrate 100 includes:

base substrate 20;

The first buffer layer 31 covers the first surface of the base substrate 20;

The first isolation layer 32 is disposed on the surface of the first buffer layer 31 away from the base substrate 20;

The second buffer layer 33 covers the surface of the first isolation layer 32 away from the base substrate 20;

The pixel driving circuit 40 located in the non-opening area 22, the pixel driving circuit 40 is disposed on the side of the second buffer layer 33 away from the base substrate 20, and includes the digging area 23;

Wherein, the orthographic projections of the first isolation layer 32 and the second buffer layer 33 on the base substrate 20 overlap with the digging region 23 , and the orthographic projections of the first isolation layer 32 and the second buffer layer 33 on the base substrate 20 None of the projections overlap with the opening area 21 .

Specifically, referring to FIG. 1 and FIG. 2 , the array substrate 100 provided by the embodiment of the present application is provided with a plurality of gate lines 13 extending along the first direction and arranged along the second direction, arranged along the first direction and A plurality of data lines 14 extending along the second direction, the gate lines 13 and the data lines 14 intersect to define a plurality of sub-pixel units 15; the display area 11 is provided with an opening area 21 and a non-opening area 22, wherein the opening area 21 refers to Each sub-pixel unit 15 can transmit light in an effective area, while other areas in the display area 11 other than the opening area 21 , such as the area corresponding to the pixel driving circuit 40 , are the non-opening area 22 . It should be noted that FIG. 1 only schematically shows the relative positional relationship between the gate line 13 , the data line 14 and the sub-pixel unit 15 , and does not represent the actual size and quantity. Referring to FIG. 2 and FIG. 3 , in the array substrate 100 provided by the embodiment of the present application, the driver circuit located in the non-open area 22 is disposed on the side of the second buffer layer 33 away from the array substrate 100 , that is, in the driver circuit The digging area 23 is overlapped with the second buffer layer 33 and the first isolation layer 32; while the opening area 21 is not overlapped with the second buffer layer 33 and the first isolation layer 32, prepared on the array substrate 100 During the process, the second buffer layer 33 and the first isolation layer 32 corresponding to the opening region 21 will be etched away. In the process of preparing the array substrate 100 , the above-mentioned digging area 23 and the above-mentioned opening area 21 are respectively designed with grooves. After the first isolation layer 32 is introduced in the embodiment of the present application, the digging area 23 and the opening area 21 are designed The process of carrying out the groove etching can be carried out separately, so that the time for the groove etching in the hole digging area 23 and the opening area 21 can be accurately controlled respectively, which effectively avoids the process of etching the two in the prior art. The problem of over-etching or under-etching occurs, which is beneficial to improve the precision of groove etching in the array substrate 100 . In addition, during the preparation process of the array substrate 100, the first isolation layer 32 at the corresponding position of the opening area 21 and many film layers located on the side of the first isolation layer 32 away from the base substrate 20 will all be removed during the trench etching process. is etched away, so that the structure of the film layer corresponding to the final opening area 21 is simple, which is beneficial to improve the penetration rate of the opening area 21 of the array substrate 100 , and is further beneficial to improve the penetration rate of the entire array substrate 100 . Moreover, after the first isolation layer is introduced into the present application, it is beneficial to protect the first buffer layer 31 and prevent the first buffer layer 31 from being damaged during the etching process, thereby helping to ensure the first buffer layer. completeness.

It should be noted that, in order to improve the transmittance of the display panel 400, the array substrate 100 provided by the above-mentioned embodiments of the present application can be applied to the liquid crystal display panel 400, and can also be applied to the organic electroluminescence display panel 400. When the electroluminescent display panel 400 is used, only the planarization layer 50 can be filled in the position corresponding to the opening area 21, please refer to FIG. This application does not specifically limit this, and the specific structure of the array substrate 100 when applied to the liquid crystal display panel 400 will be described below.

Optionally, please refer to FIG. 5 , which is another AA′ cross-sectional view of the corresponding sub-pixel unit 15 in FIG. 2 . The array substrate 100 provided in this embodiment of the present application further includes: a color resist layer 60 , disposed on the surface of the first buffer layer 31 away from the base substrate 20 and located in the opening region 21; and,

The planarization layer 50 covers the surface of the color resist layer 60 and the pixel driving circuit 40 away from the base substrate 20 .

Specifically, please continue to refer to FIG. 5 , the groove area corresponding to the opening area 21 is filled with color resistors. In the array substrate 100 provided by the embodiment of the present application, the sub-pixel unit 15 may include a red sub-pixel unit 15 and a green sub-pixel unit. 15 and the blue sub-pixel unit 15, correspondingly, the red sub-pixel unit 15 is filled with red color resistance, the green sub-pixel unit 15 is filled with green color resistance, and the blue sub-pixel unit 15 is filled with blue color resistance. The planarization layer 50 is filled on the surface of the color resist layer 60 and the pixel driving circuit 40 away from the base substrate 20 , so as to form the subsequent layer structure of the array substrate 100 (for example, the common electrode 71 layer and the pixel electrode 72 layer shown in FIG. 6 ) etc.) to provide a flattened surface.

Optionally, FIG. 6 shows a BB′ cross-sectional view of the sub-pixel unit 15 shown in FIG. 2 . Referring to FIG. 5 and FIG. 6 , in the array substrate 100 provided by the embodiment of the present application, the pixel driving circuit 40 includes a thin film The height difference between the transistor 41 and the source-drain metal layer 39 of the thin film transistor 41 and the color resist layer 60 is h, and h≤0.6 μm. Optionally, the thickness of the color resist layer 60 is D0, 1.5 μm≤D0≤3 μm.

Specifically, in the embodiment shown in FIG. 6 , the thin film transistor 41 includes a semiconductor active layer 35 , a gate insulating layer 36 , a gate metal layer 37 , an interlayer insulating layer 38 and a source-drain metal layer 39 , wherein the source and drain electrodes The metal layer 39 is electrically connected to the semiconductor active layer 35 through the via hole formed in the digging region 23 . In particular, referring to FIG. 5 , the distance h≤0.6 μm between the side of the source-drain metal layer 39 away from the base substrate 20 and the side of the color resist layer 60 away from the base substrate 20 . In the prior art, when the color resist layer 60 is disposed on the array substrate 100 , the color resist layer 60 is usually disposed on the surface of the interlayer insulating layer 38 on the side away from the base substrate 20 . Under the condition that the height of 60 remains unchanged, the height difference between the color resist layer 60 and the source-drain metal layer 39 is usually 1.4 μm or more. However, in the array substrate 100 provided by the embodiment of the present application, when the trench design is performed on the position of the opening region 21 , the interlayer insulating layer 38 , the gate insulating layer 36 , the second buffer layer 33 and the first An isolation layer 32 is completely etched away, and the color resist layer 60 is filled on the surface of the first buffer layer 31 away from the base substrate 20 , which is equivalent to moving the color resist layer 60 downward relative to the source-drain metal layer 39 , usually the height of the interlayer insulating layer 38 will be greater than 0.8 μm, so the distance that the color resist layer 60 moves downward is at least greater than 0.8 μm, which makes the height difference h between the source-drain metal layer 39 and the color resist layer 60 ≤0.6 μm, that is to say, compared with the prior art, the height difference between the source-drain metal layer 39 and the color resist layer 60 is reduced by at least 0.8 μm, and the smaller the height difference, the subsequent filling of the planarization layer 50 The smaller the thickness of the planarization layer 50 required in the process, the more favorable it is to improve the planarization capability in the subsequent planarization process. In addition, referring to FIG. 6 , since the pixel electrode 72 on the array substrate 100 and the source-drain metal layer 39 need to be electrically connected through the via hole 70 penetrating the planarization layer 50 , when the thickness of the planarization layer 50 is smaller, the The easier it is to form the via hole 70 , the easier it is to simplify the process of opening the planarization layer 50 and improve the production efficiency of the array substrate 100 .

It should be noted that the embodiment shown in FIG. 6 only shows the thin film transistor 41 with a top-gate structure, that is, the gate metal layer 37 is located on the side of the semiconductor active layer 35 away from the base substrate 20 . In some embodiments, the thin film transistor 41 with a bottom gate structure can also be used, that is, the gate metal layer 37 is located on the side of the semiconductor active layer 35 close to the base substrate 20 , which is not specifically limited in this application.

Optionally, in the array substrate 100 provided by the embodiment of the present application, the first isolation layer 32 is indium tin oxide. Specifically, when indium tin oxide is used as the first isolation layer 32 in the present application, considering that its high temperature resistance performance is strong, the high temperature resistance reaches 600 ° C, and indium tin oxide is not prone to peeling under high temperature conditions (it may occur in the application field. Peeling ( The reason for peeling) is often the presence of dirt or water vapor on the surface of the substrate, so the subsequent formation of the pixel driving circuit 40 and other related film layers will not affect the performance of the first isolation layer 32 . In addition, the indium tin oxide also has good etchability, and when the first isolation layer 32 corresponding to the opening region 21 is etched, a conventional wet etching process can be used. Of course, in addition to using indium tin oxide as the first isolation layer 32 , other materials that are resistant to high temperature, easy to etch, and difficult to peeling can be used instead in the embodiment of the present application, which is not specifically limited in the present application.

具体地，将第一隔离层32的厚度设计为

一方面使得第一隔离层32具备较好的成膜能力，另一方面该厚度范围的第一隔离层32还较易刻蚀，能够满足后续刻蚀工艺的量产性需求。当采用氧化铟锡作为第一隔离层32时，例如可将氧化铟锡的厚度设计为

成膜后可使得第一隔离层32的穿透率达到95％以上，因此采用氧化铟锡作为第一隔离层32时对阵列基板100的穿透率没有影响或影响很小。Optionally, referring to FIG. 6 , the thickness of the first isolation layer 32 provided in the embodiment of the present application is D1,

Specifically, the thickness of the first isolation layer 32 is designed to be

On the one hand, the first isolation layer 32 has better film-forming ability, and on the other hand, the first isolation layer 32 in this thickness range is easier to be etched, which can meet the mass production requirements of the subsequent etching process. When using indium tin oxide as the first isolation layer 32, for example, the thickness of indium tin oxide can be designed as

After the film is formed, the transmittance of the first isolation layer 32 can reach more than 95%, so the use of indium tin oxide as the first isolation layer 32 has no or little influence on the transmittance of the array substrate 100 .

一方面，厚度范围为

的第二缓冲层33能够为像素驱动电路40的形成提供平坦的表面，对阵列基板100整体的厚度影响较小，另一方面，还能进一步阻挡外界的水分和氧气通过第二缓冲层33进入到像素驱动电路40中，避免对像素驱动电路40的性能造成影响。Optionally, referring to FIG. 6 , the thickness of the second buffer layer 33 provided in the embodiment of the present application is D2,

On the one hand, the thickness range is

The second buffer layer 33 can provide a flat surface for the formation of the pixel driving circuit 40, which has little effect on the overall thickness of the array substrate 100. On the other hand, it can further block the entry of external moisture and oxygen through the second buffer layer 33. into the pixel driving circuit 40 to avoid affecting the performance of the pixel driving circuit 40 .

具体地，本申请在引入第一隔离层32后，由于后续制程中需要形成像素驱动电路40中的薄膜晶体管41，薄膜晶体管41中的半导体有源层35形成在平坦的缓冲层上时有利于提升晶化效果，因此在第一隔离层32远离第一缓冲层31的一侧引入了第二缓冲层33。此外，第一缓冲层31和第二缓冲层33还可对外界的水分和氧气起到双重的阻隔作用，有效避免外界的水分和氧气进入到像素驱动电路40中，避免对像素驱动电路40的性能造成影响。Optionally, referring to FIG. 6 , in the array substrate 100 provided by the embodiment of the present application, the total thickness of the first buffer layer 31 , the first isolation layer 32 and the second buffer layer 33 is D3 , wherein,

Specifically, after the first isolation layer 32 is introduced in the present application, since the thin film transistor 41 in the pixel driving circuit 40 needs to be formed in the subsequent process, the semiconductor active layer 35 in the thin film transistor 41 is formed on the flat buffer layer. To improve the crystallization effect, the second buffer layer 33 is introduced on the side of the first isolation layer 32 away from the first buffer layer 31 . In addition, the first buffer layer 31 and the second buffer layer 33 can also act as a double barrier to external moisture and oxygen, effectively preventing external moisture and oxygen from entering the pixel driving circuit 40 and preventing the pixel driving circuit 40 from causing damage to the pixel driving circuit 40 . performance is affected.

Based on the same inventive concept, referring to FIG. 7 , the present application further provides a method for preparing an array substrate 100 . FIG. 7 shows a flowchart of a method for preparing an array substrate 100 provided by an embodiment of the present application, wherein the array substrate 100 1 and 2, the array substrate 100 is provided with a display area 11 and a non-display area 12, the display area 11 includes an opening area 21 and a non-opening area 22, and the above-mentioned preparation method includes:

Step 101, providing a base substrate 20;

Step 102 , fabricating a first buffer layer 31 , so that the first buffer layer 31 covers the first surface of the base substrate 20 , see FIG. 8 , which shows the preparation of an array substrate 100 according to an embodiment of the present application A schematic diagram of forming the first buffer layer 31 on the base substrate 20 in the method;

Step 103 , fabricating a first isolation layer 32 so that the first isolation layer 32 covers the surface of the first buffer layer 31 away from the base substrate 20 . Referring to FIG. 9 , FIG. 9 shows an array provided by an embodiment of the present application. A schematic diagram of forming the first isolation layer 32 in the preparation method of the substrate 100;

Step 104 , fabricating a second buffer layer 33 so that the second buffer layer 33 covers the surface of the first isolation layer 32 away from the base substrate 20 . Referring to FIG. 10 , FIG. 10 shows an array provided by an embodiment of the present application A schematic diagram of forming the second buffer layer 33 in the preparation method of the substrate 100;

In step 105, the pixel driving circuit 40 is fabricated on the side of the second buffer layer 33 away from the base substrate 20, and the opening area 21 and the digging area 23 are formed by step-by-step etching, and the digging area 23 is located in the non-opening area 22, Make the orthographic projections of the first isolation layer 32 and the second buffer layer 33 on the base substrate 20 overlap with the digging region 23 , and make the first isolation layer 32 and the second buffer layer 33 on the base substrate 20 . The orthographic projections do not overlap with the opening area 21 . Referring to FIG. 11 , FIG. 11 shows a structural diagram of an array substrate 100 formed by using the method for fabricating an array substrate provided by an embodiment of the present application.

Specifically, with reference to FIGS. 7 to 11 , in a method for preparing an array substrate 100 provided by an embodiment of the present application, in the process of preparing the array substrate 100 , the above-mentioned digging area 23 and the above-mentioned opening area 21 will be respectively performed. The trenching design, after the first isolation layer 32 is introduced in the embodiment of the present application, the trenching and etching process of the trenching area 23 and the opening area 21 can be carried out separately, so that the trenching area 23 and the opening area 21 are trenched The etching time can be precisely controlled respectively, which effectively avoids the problem of over-etching or under-etching in the prior art process of etching the two, thereby helping to improve the precision of trench etching in the array substrate 100 . In addition, during the preparation process of the array substrate 100, the first isolation layer 32 at the corresponding position of the opening area 21 and many film layers located on the side of the first isolation layer 32 away from the base substrate 20 will all be removed during the trench etching process. is etched away, so that the structure of the film layer corresponding to the final opening area 21 is simple, which is beneficial to improve the penetration rate of the opening area 21 of the array substrate 100 , and is further beneficial to improve the penetration rate of the entire array substrate 100 . Moreover, after the first isolation layer is introduced into the present application, it is beneficial to protect the first buffer layer 31 and prevent the first buffer layer 31 from being damaged during the etching process, thereby helping to ensure the first buffer layer. 31 integrity.

Optionally, please refer to FIG. 12 . FIG. 12 shows a schematic diagram after the color resist layer 60 and the planarization layer 50 are formed on the basis of FIG. 11 , the preparation of an array substrate 100 provided by the embodiment of the present application The method further includes: forming a color resist layer 60 in the opening area 21, so that the color resist layer 60 is located on the surface of the first buffer layer 31 away from the base substrate 20;

A planarization layer 50 is formed on the surface of the color resist layer 60 and the pixel driving circuit 40 away from the base substrate 20 .

Specifically, please continue to refer to FIG. 12 , the groove area corresponding to the opening area 21 is filled with color resists. In the array substrate 100 provided by the embodiment of the present application, the sub-pixel unit 15 may include a red sub-pixel unit 15 and a green sub-pixel unit. 15 and the blue sub-pixel unit 15, correspondingly, the red sub-pixel unit 15 is filled with red color resistance, the green sub-pixel unit 15 is filled with green color resistance, and the blue sub-pixel unit 15 is filled with blue color resistance. The surface of the color resist layer 60 and the pixel driving circuit 40 away from the base substrate 20 is filled with the planarization layer 50 to form the subsequent layer structure of the array substrate 100 (for example, the common electrode 71 layer and the pixel electrode 72 layer shown in FIG. 6 , etc. ) provides a flattened surface.

Optionally, please refer to FIG. 13. FIG. 13 shows a flowchart of forming the opening area 21 and the digging area 23 by using a step-by-step etching method. In the above step 105, the second buffer layer 33 is far away from the substrate. The pixel driving circuit 40 is fabricated on one side of the substrate 20, and the opening area 21 and the digging area 23 are formed by step-by-step etching, and further:

Step 201 , forming a semiconductor active layer 35 , a gate insulating layer 36 , a gate metal layer 37 and an interlayer insulating layer 38 in sequence on the side of the second buffer layer 33 away from the base substrate 20 , see FIG. 14 , as shown in FIG. 14 . A process diagram of forming the array substrate 100 in the method for preparing the array substrate 100 provided by the embodiment of the present application is shown;

Step 202 , performing a first etching process, referring to FIG. 15 , removing the interlayer insulating layer 38 , the gate insulating layer 36 and the second buffer layer 33 located in the first region 91 , exposing the first isolation layer located in the first region 91 Layer 32, the first region 91 and the semiconductor active layer 35 do not overlap, and FIG. 15 shows a schematic diagram of using the first etching process to remove the interlayer insulating layer 38 and the gate insulating layer 36 located in the first region 91;

Step 203, performing a second etching process, referring to FIG. 16, removing the interlayer insulating layer 38 and the gate insulating layer 36 located in the second region 92, exposing the semiconductor active layer 35 located in the second region 92, and forming a hole Region 23, the second region 92 overlaps with the semiconductor active layer 35 and does not overlap with the gate metal layer 37, as shown in FIG. 16, the second etching process is used to remove the interlayer insulating layer 38 in the second region 92 and a schematic diagram of the gate insulating layer 36;

Step 204 , performing a third etching process, referring to FIG. 17 , removing the first isolation layer 32 located in the first region 91 , forming the opening region 21 in the first region 91 ; the digging region 23 and the interlayer insulating layer 38 are far away A source-drain metal layer is formed on one side of the base substrate 20 . FIG. 17 is a schematic diagram of removing the first isolation layer 32 located in the first region 91 by the third etching process.

Specifically, with reference to FIGS. 13 to 17 , the processes of forming the opening area 21 and the digging area 23 in the embodiments of the present application are respectively formed through three etching processes. 91 of the interlayer insulating layer 38, the gate insulating layer 36 and the second buffer layer 33; in the second etching process, the interlayer insulating layer 38 and the gate insulating layer 36 located in the second region 92 are removed to form Digging the hole region 23 ; in the third etching process, the first isolation layer 32 located in the first region 91 is removed, thereby forming the opening region 21 . It can be seen that the etching processes of the digging region 23 and the opening region 21 are performed separately, and the formation of the opening region 21 is formed by two etching processes (the first etching process and the third etching process), In this way, the execution processes of the first etching process and the second etching process are completely independent and will not affect each other, so the etching time of the first etching process and the second etching process can be controlled independently. It is beneficial to improve the etching precision and avoid the phenomenon of over-etching or under-etching. In addition, in the first etching process, in the process of etching the interlayer insulating layer 38 and the gate insulating layer 36 of the first region 91, due to the protective effect of the first isolation layer 32, the first buffer is not affected The layer 31 is damaged, and the process of separately etching the first isolation layer 32 by the third etching process can also be controlled by the etching process so that the etching process does not affect the first buffer layer 31. Therefore, the present application The preparation method of the array substrate 100 provided by the embodiment is beneficial to ensure the integrity of the first buffer layer 31 .

Optionally, before performing the first etching process, that is, before performing the foregoing step 202, the method further includes:

A photoresist 90 is coated on the side of the interlayer insulating layer 38 away from the base substrate 20, see FIG. 18, and a semi-transmissive mask is used to expose and develop the photoresist 90, see FIG. 19, and the photoresist 90 is removed. The photoresist 90 in the first region 91 exposes the interlayer insulating layer 38 in the first region 91, and removes part of the photoresist 90 in the second region 92, which is shown on the interlayer insulating layer 38 in FIG. 18 A schematic diagram of coating the photoresist 90, and FIG. 19 is a schematic diagram of exposing and developing the photoresist 90 in FIG. 18;

It should be noted that when the first etching process is performed, the interlayer insulating layer 38 , the gate insulating layer 36 and the second buffer layer 33 in the corresponding first region 91 in FIG. 19 are etched, and the etching The resulting structure can be seen in FIG. 20 , wherein FIG. 20 shows a schematic diagram after etching the interlayer insulating layer 38 , the gate insulating layer 36 and the second buffer layer 33 corresponding to the first region 91 in FIG. 19 ;

Before performing the second etching process, that is, before performing the above step 203, the method further includes:

Perform ashing treatment on the photoresist 90 on the side of the interlayer insulating layer 38 away from the base substrate 20, remove the photoresist 90 in the second area 92 and a part of the photoresist 90 around the second area 92, and expose the The interlayer insulating layer 38 located in the second region 92 is shown in FIG. 21 . FIG. 21 is a schematic diagram after ashing of the photoresist 90 in FIG. 20 . It should be noted that the ashing process of the photoresist is to etch away the photoresist 90 as the target to be etched. As the target to be etched, the composition of the photoresist 90 can be composed of C, H, O The organic matter composed of , N can generally be reacted with oxygen to generate volatile substances such as CO, CO ₂ , H ₂ O, N ₂ , etc. The application can control the need to be etched by controlling the ashing rate and ashing time. The thickness of the removed photoresist 90 is reduced, so as to achieve the effect shown in FIG. 20 and expose the interlayer insulating layer 38 located in the second region 92 .

On the basis of the structure shown in FIG. 21 , the interlayer insulating layer 38 and the gate insulating layer 36 corresponding to the second region 92 can be etched by a second etching process, thereby forming the digging as shown in FIG. 22 . The hole region 23 region, FIG. 22 is a schematic diagram after etching the interlayer insulating layer 38 and the gate insulating layer 36 corresponding to the second region 92 . After the second etching process is completed, under the structure shown in FIG. 22 , the first isolation layer 32 located in the first region 91 is etched by the third etching process, thereby forming the structure shown in FIG. 23 , wherein FIG. 23 is a schematic diagram of etching the first isolation layer 32 by the third etching process. It should be noted that the step of removing the photoresist 90 shown in FIG. 23 is also included before the source-drain metal layer 39 is formed, and finally the structure shown in FIG. 24 is formed. A schematic diagram of the semiconductor active layer 39 formed after all the photoresist 90 is removed.

Optionally, the first etching process and the second etching process are dry etching, and the third etching process is wet etching.

Specifically, the gate insulating layer 36 and the interlayer insulating layer 38 are usually composed of silicon oxide or silicon nitride, and the gate insulating layer 36 and the interlayer insulating layer can be separated by dry etching, such as gas CF4 _. The layer 38 is etched away, and in the process of dry etching, the gas CF ₄ will not affect the first isolation layer 32, so the existence of the first isolation layer 32 can protect the first buffer layer 31 from the first isolation layer 31. Influence of etching process and second etching process. The third etching process is wet etching, that is, a specific solution (such as hydrochloric acid solution, etc.) is used to etch the first isolation layer 32. The etching rate can usually be controlled by the concentration and temperature of the solution. The concentration can change the rate at which the reactant reaches and leaves the surface of the object to be etched. Generally speaking, when the concentration of the solution increases, the etching rate will increase. Increasing the solution temperature can accelerate the chemical reaction rate, which in turn can speed up the etching rate. When the first isolation layer 32 is etched by wet etching, the first buffer layer 31 will not be affected, so the integrity of the first buffer layer 31 can be ensured.

Based on the same inventive concept, the present application further provides a display panel 400, referring to FIG. 25, including an array substrate 100, the array substrate 100 is the array substrate 100 provided by the above-mentioned embodiment, wherein, FIG. 25 shows the embodiment of the present application. A schematic diagram of a display panel 400 is provided. In addition to the array substrate 100, the display panel 400 also includes a color filter substrate 200 disposed opposite to the array substrate 100 and a liquid crystal liquid crystal located between the array substrate 100 and the color filter substrate 200. For the layer 300, the embodiments of the display panel 400 can be referred to the above-mentioned embodiments of the array substrate 100, and repeated descriptions will not be repeated.

Based on the same inventive concept, the present application further provides a display device 500, see FIG. 26, including a display panel 400, the display panel 400 is the display panel 400 provided by the above-mentioned embodiment, wherein FIG. 26 shows the display panel 400 provided by the embodiment of the present application A schematic diagram of a display device 500 shown in FIG. The display device 500 provided in this application can be any product or component with real functions, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator. For the embodiments of the display device 500 in the present application, reference may be made to the above-mentioned embodiments of the display panel 400 , and repeated descriptions will not be repeated here.

It can be seen from the above embodiments that the array substrate and the preparation method thereof, the display panel and the display device provided by the present invention at least achieve the following beneficial effects:

In the array substrate and its preparation method, the display panel and the display device provided by the present application, the first isolation layer and the second buffer layer are introduced on the side of the first buffer layer away from the base substrate, and the holes in the pixel driving circuit are dug holes. The opening area is arranged on the side of the second buffer layer away from the base substrate and overlaps with the first isolation layer and the second buffer layer, and the opening area does not overlap with the first isolation layer and the second buffer layer. In the process of opening the area, the design of the groove needs to be carried out. After the first isolation layer is introduced in the present application, the groove etching process in the opening area and the groove etching process in the hole drilling area can be carried out separately. The etching time corresponding to the opening area is beneficial to improve the etching accuracy of the digging area and the opening area, thereby effectively avoiding the over-etching of the digging area due to the large difference between the areas of the digging area and the opening area. Or the problem of under-etching of the opening area.

Although some specific embodiments of the present invention have been described in detail by way of examples, those skilled in the art should understand that the above examples are provided for illustration only and not for the purpose of limiting the scope of the present invention. Those skilled in the art will appreciate that modifications may be made to the above embodiments without departing from the scope and spirit of the present invention. The scope of the invention is defined by the appended claims.

Claims (15)

1. An array substrate, characterized in that, a display area and a non-display area are provided, the display area includes an open area and a non-open area, and the array substrate includes: substrate substrate; a first buffer layer covering the first surface of the base substrate; a first isolation layer, disposed on the surface of the first buffer layer away from the base substrate; a second buffer layer covering the surface of the first isolation layer away from the base substrate; a pixel driving circuit located in the non-opening area, the pixel driving circuit is disposed on the side of the second buffer layer away from the base substrate, and includes a digging area; Wherein, the orthographic projections of the first isolation layer and the second buffer layer on the base substrate both overlap with the digging region, and the first isolation layer and the second buffer layer are in the The orthographic projections on the base substrate do not overlap with the opening area. 2. The array substrate according to claim 1, further comprising: a color resist layer, disposed on the surface of the first buffer layer away from the base substrate and located in the opening area; and, A planarization layer covers the surface of the color resist layer and the pixel driving circuit away from the base substrate. 3 . The array substrate according to claim 2 , wherein the pixel driving circuit comprises a thin film transistor, and the height difference between the source and drain metal layers of the thin film transistor and the color resist layer is h, h 3 . ≤0.6μm. 4 . The array substrate according to claim 2 , wherein the thickness of the color resist layer is D0 , and 1.5 μm≦D0≦3 μm. 5 . 5 . The array substrate of claim 1 , wherein the first isolation layer is indium tin oxide. 6 . 6. The array substrate according to claim 1, wherein the thickness of the first isolation layer is D1,

7. The array substrate according to claim 1, wherein the thickness of the second buffer layer is D2,

8 . The array substrate according to claim 1 , wherein the total thickness of the first buffer layer, the first isolation layer and the second buffer layer is D3 , wherein,

9. A method for preparing an array substrate, wherein the array substrate is provided with a display area and a non-display area, the display area includes an open area and a non-open area, and the preparation method comprises: Provide a base substrate; making a first buffer layer, so that the first buffer layer covers the first surface of the base substrate; making a first isolation layer, so that the first isolation layer covers the surface of the first buffer layer away from the base substrate; forming a second buffer layer, so that the second buffer layer covers the surface of the first isolation layer away from the base substrate; A pixel driving circuit is fabricated on the side of the second buffer layer away from the base substrate, and the opening area and the digging area are formed by step-by-step etching, and the digging area is located in the non-opening area. The orthographic projections of the first isolation layer and the second buffer layer on the base substrate are both overlapped with the digging region, and the first isolation layer and the second buffer layer are in The orthographic projections on the base substrate do not overlap with the opening area. 10. The method for preparing an array substrate according to claim 9, further comprising: forming a color resist layer in the opening area, so that the color resist layer is located on the surface of the first buffer layer away from the base substrate; A planarization layer is formed on the surface of the color resist layer and the pixel driving circuit away from the base substrate. 11 . The method for fabricating an array substrate according to claim 9 , wherein the fabricating the pixel driving circuit on the side of the second buffer layer away from the base substrate is formed by step-by-step etching. 12 . The opening area and the digging area are further: A semiconductor active layer, a gate insulating layer, a gate metal layer and an interlayer insulating layer are sequentially formed on the side of the second buffer layer away from the base substrate; performing a first etching process, removing the interlayer insulating layer, the gate insulating layer and the second buffer layer located in the first region, exposing the first isolation layer located in the first region, the first region does not overlap the semiconductor active layer; performing a second etching process, removing the interlayer insulating layer and the gate insulating layer in the second region, exposing the semiconductor active layer in the second region, and forming a hole region, the second a region overlapping the semiconductor active layer and not overlapping the gate metal layer; performing a third etching process, removing the first isolation layer located in the first region, and forming the opening region in the first region; A source-drain metal layer is formed on a side of the digging region and the interlayer insulating layer away from the base substrate. 12 . The method for preparing an array substrate according to claim 11 , wherein before the performing the first etching process, the method further comprises: 12 . A photoresist is coated on the side of the interlayer insulating layer away from the base substrate, and a semi-transmissive mask is used to expose and develop the photoresist to remove the photoresist, exposing the interlayer insulating layer in the first region, and removing part of the photoresist in the second region; Before performing the second etching process, the method further includes: performing ashing treatment on the photoresist located on the side of the interlayer insulating layer away from the base substrate, and removing the photoresist located in the second area and a part of the photoresist located around the second area, The interlayer insulating layer in the second region is exposed. 13. The method for preparing an array substrate according to claim 11, wherein the first etching process and the second etching process are dry etching, and the third etching process is dry etching. for wet etching. 14 . A display panel, comprising an array substrate, the array substrate being the array substrate of any one of claims 1 to 8 . 15 . 15 . A display device, comprising a display panel, the display panel being the display panel of claim 14 . 16 .

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