CN108933113A - Circuit board with electric isolator and base plate, its semiconductor assembly and its making method - Google Patents

Abstract

The circuit board of the present invention includes an electrical isolator laterally surrounded by a substrate and a molding compound. The electric isolating piece is inserted in a through opening of the substrate plate, and the thickness of the electric isolating piece is larger than that of the substrate plate. The mold seal covers the top side of the base plate and the sidewalls of the electrical isolators and provides a reliable interface for routing circuitry to be deposited thereon. The base plate can be used as a positioning piece when the isolating piece is placed, or/and provides another route so as to improve the flexibility of the electrical wiring of the circuit board.

Description

Circuit board provided with electric isolator and base board, semiconductor assembly thereof and method for manufacturing the same

technical field

The present invention relates to a circuit board, its semiconductor assembly and its manufacturing method, in particular to a circuit board provided with an electrical isolator and a base plate, its semiconductor assembly and its manufacturing method.

Background technique

High-voltage or high-current applications, such as power modules or light-emitting diodes (LEDs), typically require the use of high-performance circuit boards to interconnect the signals. However, when the power is increased, the large amount of heat generated by the semiconductor chip will degrade the performance of the device and also cause thermal stress to the chip. Accordingly, ceramic materials such as alumina or aluminum nitride are often considered suitable materials for such applications because they are thermally conductive and electrically insulating, and have a low coefficient of thermal expansion (CTE). US Patent Nos. 8,895,998 and 7,670,872 have disclosed various interconnection structures, which use ceramics as the die pad material to achieve better reliability. In addition, direct bond copper (DBC) boards have become the preferred circuit board for many high power module applications. The DBC board is usually composed of ceramic spacers, such as Al ₂ O ₃ (aluminum oxide), A1N (aluminum nitride) or Si ₃ N ₄ (silicon nitride), and through a high-temperature sintering diffusion process, copper is bonded to both sides of the ceramic Floor. However, bonding thick copper plates to spacers usually requires very high sintering temperatures, and specific materials or conditions are required to obtain a reliable copper/ceramic interface, which will lead to lower yield and more complicated process. Furthermore, the metallization process in the direct copper clad technology usually requires sintering copper plates of the same thickness on both sides to avoid warping of the ceramic plate. The thick copper on the bottom side can be used as a heat sink, but the thickness of the copper on the top side will cause poor etching resolution and severely limit the ability of circuit routing. Therefore, existing DBC boards are not suitable for flip-chip or surface mount attachment technologies suitable for power module assemblies.

Contents of the invention

The main purpose of the present invention is to provide a circuit board, which embeds a low CTE high thermal conductivity spacer in the molding material to solve the problem of thermal expansion coefficient mismatch between the chip and the circuit board, and the molding material can provide reliable The interface for routing circuits to be deposited on, thus improving the mechanical reliability and thermal characteristics of the semiconductor assembly.

Another object of the present invention is to provide a circuit board, which inserts the spacer into the through opening of the base plate, so that the base plate can be used as a positioning member when placing the spacer, and avoids the displacement of the spacer during the molding process. Moreover, the flexibility of electrical wiring of the circuit board can be improved.

According to the above and other objects, the present invention provides a circuit board provided with electrical isolators and vertical connectors, which includes: a base board including a top side, a bottom side, and a plurality of tops at the top side a contact pad, and a through opening, wherein the inner sidewall of the through opening extends from the top side to the bottom side; an electrical spacer, which is arranged in the through opening of the base plate, wherein the bottom surface of the electrical spacer is in contact with the bottom side The bottom side of the base plate is substantially coplanar and the thickness of the electrical isolator is greater than the thickness of the base plate; a molding material covering the top side of the base plate and extending into the electrical isolator a gap between the peripheral edge and the inner sidewall of the through opening, wherein the outer surface of the molding material is substantially coplanar with the top surface of the electrical isolator; a routing circuit is disposed on the molding material the outer surface; and a plurality of vertical connectors disposed on the top side of the base plate, embedded in the molding compound, and electrically coupled to the routing circuit and the base plate Top contact pad. In addition, the present invention also provides a semiconductor assembly, which includes a semiconductor element connected to the top surface of the electrical isolator of the circuit board and electrically connected to the routing circuit.

In another solution, the present invention provides a method for manufacturing a circuit board provided with an electrical isolator, which includes the following steps: providing a base plate, which includes a top side, a bottom side and a through opening, wherein the through The inner sidewall of the opening extends from the top side to the bottom side; an electrical isolator is inserted into the through opening of the base plate, and the peripheral edge of the electrical isolator is close to the inner sidewall of the through opening, and the electrical isolator The bottom surface of the member is substantially coplanar with the bottom side of the base plate, wherein the thickness of the electrical isolator is greater than the thickness of the base plate; a molding material is provided on the top side of the base plate, and the molding a material extending into a gap between the peripheral edge of the electrical isolator and the inner sidewall of the through opening, wherein the outer surface of the molding material is substantially coplanar with the top surface of the electrical isolator; and forming A routing circuit is on the outer surface of the molding material.

Unless specifically described or steps that must occur sequentially, the order of the above steps is not limited to that listed above and may be changed or rearranged according to the desired design.

The circuit board, the semiconductor assembly and the manufacturing method thereof of the present invention have many advantages. For example, it is particularly advantageous to insert the electrical isolator into the through-opening of the base plate, because the base plate can ensure that the electrical isolator is placed exactly and/or the base plate can provide a direct response to the Routing circuits provide further routing. Depositing vertical connectors on the substrate provides vertical connection channels for interconnecting routing circuits on the molding compound to the substrate. Bonding the molding compound to the electrical isolator provides a platform on which high-resolution circuitry can be deposited, enabling components with fine pad pitches such as flip chips and surface mount components ), to be assembled on the circuit board.

The above and other features and advantages of the present invention can be more clearly understood through the detailed description of the following preferred embodiments.

Description of drawings

With reference to the accompanying drawings, the present invention will be more clearly understood by the following detailed description of the preferred embodiments, wherein:

1 and 2 are respectively a schematic cross-sectional view and a top perspective view of a base plate in the first embodiment of the present invention;

Figures 3 and 4 are respectively a schematic cross-sectional view and a top perspective view of vertical connectors provided in the structures of Figures 1 and 2 in the first embodiment of the present invention;

5 and 6 are respectively a cross-sectional schematic diagram and a top perspective schematic diagram of a through opening formed in the structures of FIGS. 3 and 4 in the first embodiment of the present invention;

7 and 8 are respectively a schematic cross-sectional view and a top perspective view of an electrical isolator provided in the structures of FIGS. 5 and 6 in the first embodiment of the present invention;

9 is a schematic cross-sectional view of the molding material provided in the structure of FIG. 7 in the first embodiment of the present invention;

10 is a schematic cross-sectional view of removing the upper half of the molding compound in the structure of FIG. 9 in the first embodiment of the present invention;

11 and 12 are respectively a cross-sectional schematic diagram and a top perspective schematic diagram of providing a routing circuit and a bottom coating layer in the structure of FIG. 10 to complete the fabrication of a circuit board in the first embodiment of the present invention;

13 and 14 are respectively a schematic cross-sectional view and a top perspective view of a semiconductor element provided in the structures of FIGS. 11 and 12 in the first embodiment of the present invention;

Fig. 15 is a schematic cross-sectional view of a circuit board of another solution in the first embodiment of the present invention;

Fig. 16 is a schematic cross-sectional view of another scheme of the circuit board in the first embodiment of the present invention;

Fig. 17 is a schematic cross-sectional view of another scheme of the circuit board in the first embodiment of the present invention;

Fig. 18 is a schematic cross-sectional view of a circuit board of another solution in the first embodiment of the present invention;

19 is a schematic cross-sectional view of providing a top dielectric layer in the structure of FIG. 11 in a second embodiment of the present invention;

FIG. 20 is a schematic cross-sectional view of providing top wires in the structure of FIG. 19 to complete the circuit board fabrication in the second embodiment of the present invention;

21 is a schematic cross-sectional view of a semiconductor element provided in the structure of FIG. 20 in a second embodiment of the present invention;

22 is a schematic cross-sectional view of a circuit board in a third embodiment of the present invention;

Fig. 23 is a schematic cross-sectional view of a circuit board of another solution in the third embodiment of the present invention;

24 is a schematic cross-sectional view of semiconductor elements and passive elements provided in the structure of FIG. 22 in the third embodiment of the present invention;

25 is a schematic cross-sectional view of semiconductor elements, passive and sealing materials provided in the structure of FIG. 22 in the third embodiment of the present invention;

26 is a schematic cross-sectional view of semiconductor elements, passive and sealing materials provided in another circuit board in the third embodiment of the present invention;

27 is a schematic cross-sectional view of a semiconductor element, passive and sealing material provided in a circuit board of another solution in the third embodiment of the present invention;

28 is a schematic cross-sectional view of another circuit board in the fourth embodiment of the present invention;

29 is a schematic cross-sectional view of another circuit board in the fifth embodiment of the present invention;

30 is a schematic cross-sectional view of providing a bottom dielectric layer in the structure of FIG. 29 in the sixth embodiment of the present invention;

FIG. 31 is a schematic cross-sectional view of providing bottom wires in the structure of FIG. 30 to complete the circuit board fabrication in the sixth embodiment of the present invention.

【Symbol Description】

Circuit Board 100, 200, 300, 400, 500, 600

Semiconductor assembly 110, 120, 130, 140, 150, 210, 310, 320, 330, 340, 350

base plate 10

Top side 101, 201

bottom side 103

Through opening 105

Clearance 107

inner wall 109

core layer 12

Top Line Layer 13

Top Contact Pad 131

Bottom metal layer 15

Bottom line layer 16

Bottom Contact Pad 161

insulation 17

Metallized vias 18

Vertical link 20

metal post 21

Metal Filled Via 23

conductive ball 25

Galvanic isolation 30

top 301

Bottom 303

Molding compound 40

outer surface 401

Blind hole 41, 913, 933

routing circuit 50

Thermal Pad 51

Metallized vias 55

Bottom cladding 60

Semiconductor components 71, 72

passive components 73

Conductive bumps 81

Bonding wire 83

Sealant 89

Top Buildup Circuitry 91

top dielectric layer 911

Top wire 915

Metallized blind vias 917, 937

Bottom Buildup Circuitry 93

bottom dielectric layer 931

Bottom wire 935

Detailed ways

Hereinafter, examples will be provided to illustrate embodiments of the present invention in detail. The advantages and effects of the present invention will be more obvious through the contents disclosed in the present invention. The drawings accompanying this description are simplified and used for illustration purposes. The number, shape and size of the components shown in the drawings can be modified according to the actual situation, and the configuration of the components may be more complicated. Other aspects of practice or application can also be carried out in the present invention, and various changes and adjustments can be made without departing from the defined spirit and scope of the present invention.

[Example 1]

1-12 is a diagram of a manufacturing method of a circuit board in the first embodiment of the present invention, which includes an electrical isolator, a base plate, a plurality of vertical connectors, a molding material, a routing circuit and a bottom Covering layer.

1 and 2 are respectively a schematic cross-sectional view and a top perspective view of the base plate 10 . In this embodiment, the substrate 10 includes a top wiring layer 13 on the top side 101 , a bottom metal layer 15 on the bottom side 103 , and an insulating layer 17 between the top wiring layer 13 and the bottom metal layer 15 . The insulating layer 17 may be made of ceramics, glass, epoxy resin, molding compound, glass epoxy resin, polyimide, or the like. The top circuit layer 13 is usually a patterned copper layer and includes a plurality of top contact pads 131 (as shown in FIG. 2 ). The bottom metal layer 15 is an unpatterned copper layer, which completely covers the insulating layer 17 from below.

3 and 4 are respectively a cross-sectional schematic diagram and a top perspective schematic diagram of forming the vertical connecting member 20 on the top side 101 of the base plate 10 . The vertical connector 20 may be made of Cu, Sn, Ti, Ni, Au, Ag, Sn alloy or other suitable conductive materials, wherein the Sn alloy may contain Ag, Cu, Bi or a combination thereof. Here, metal pillars, solder balls, bonding wires or a combination thereof can be formed on the top circuit layer 13 of the base board 10 by vacuum sputtering, electroplating, soldering, wire bonding, welding or other suitable methods. , as the vertical connector 20. In addition, the vertical connecting member 20 can also be made into a joint structure. For example, the vertical connectors 20 may be bonded solder bumps or bonded copper pillars with bonding solder layers. The solders described herein may contain lead (eg Sn/Pb) or lead-free (eg Au/Sn or Sn/Ag/Cu). In this figure, the vertical connector 20 is a metal post 21 formed by electroplating, which is electrically connected to the top contact pad 131 of the top circuit layer 13 .

5 and 6 are respectively a cross-sectional view and a top perspective view of forming the through opening 105 in the base plate 10 . The inner wall 109 of the through opening 105 extends from the top side 101 of the base plate 10 to the bottom side 103 of the base plate 10, and the through opening 105 can be formed by various techniques, such as punching, drilling or laser cutting. .

7 and 8 are respectively a cross-sectional view and a top perspective view of the electrical isolator 30 inserted into the through opening 105 of the base plate 10 . The electrical isolator 30 usually has a high modulus of elasticity and a low coefficient of thermal expansion (for example, 2×10 ⁻⁶ K ⁻¹ to 10×10 ⁻⁶ K ⁻¹ ), and can be, for example, ceramic, silicon, glass or other electrical insulating materials with thermal conductivity. Material. In this embodiment, the electrical isolator 30 is a ceramic block, the thickness of which is substantially equal to the thickness of the base plate 10 plus the height of the vertical connector 20, and is accommodated in the through opening 105 of the base plate 10, wherein the base plate 10 The bottom side 103 of the electrical isolator 30 is substantially coplanar with the bottom surface 303 of the electrical isolator 30 . Since the size of the through opening 105 is larger than that of the electrical isolator 30 , there is a gap 107 inside the through opening 105 between the inner wall 109 of the base board 10 and the peripheral edge of the electrical isolator 30 . This gap 107 laterally surrounds the electrical isolator 30 and is at the same time surrounded laterally by the base plate 10 . In some examples, the inner sidewall 109 of the base board 10 can be used as a positioning member to ensure the accuracy of the electrical isolator 30 when placed. Accordingly, the electrical isolator 30 can be accurately restricted to a predetermined position, and the peripheral edge of the electrical isolator 30 will be close to the inner wall 109 of the through opening 105 of the base board 10 .

FIG. 9 is a schematic cross-sectional view of forming the molding compound 40 . The molding compound 40 can be formed by coating a molding material on the top side 101 of the base plate 10, on the top surface 301 of the electrical isolator 30, and in the gap 107 between the base plate 10 and the electrical isolator 30, wherein the mold The material can be coated by paste printing, compressive molding, transfer molding, liquid injection molding, spin coating or other suitable methods . Next, heat treatment (or thermosetting process) is performed to harden the molding material to convert the molding material into a solid molding compound. Accordingly, the molding material 40 will cover the base plate 10, the vertical connectors 20 and the electrical isolator 30 from above, and laterally cover, surround and conformally coat the inner side wall 109 of the base plate 10, the side walls of the vertical connector 20 and the electrical isolator. 30 side walls.

The molding compound 40 generally includes adhesive resin, filler, hardener, diluent and additives. The binder resin used in the present invention is not particularly limited. For example, the bonding resin may be selected from epoxy resin, phenol resin, polyimide resin, polyurethane resin, silicone resin, polyester resin, acrylic resin, bismaleimide ( Bismaleimide, BMI) resins and at least one of the group of equivalents thereof. Adhesive resin can provide a tight bond between the adhesive material and the filler material. The bonding resin can also be connected by chains of fillers to provide thermal conductivity. In addition, the bonding resin can also improve the physical and chemical stability of the molding compound 40 .

In addition, the filler used in the present invention is not particularly limited. For example, a thermally conductive filler selected from the group consisting of aluminum oxide, aluminum nitride, silicon carbide, tungsten carbide, boron carbide, silicon dioxide, and equivalents may be used. More specifically, the molding compound 40 can become thermally conductive or have a low coefficient of thermal expansion (CTE) if appropriate fillers are dispersed therein. For example, aluminum nitride (AlN) or silicon carbide (SiC) have relatively high thermal conductivity, relatively high electrical resistance, and relatively low coefficient of thermal expansion. Accordingly, when such materials are used as fillers in the molding compound 40, the molding compound 40 can exhibit better heat dissipation performance and electrical insulation performance, and its low CTE characteristics can avoid peeling or cracks in circuits or interfaces. . The maximum particle size of the thermally conductive filler may be 25 μm or less. The content of the filler can be in the range of 10 to 90 weight percent. If the content of the thermally conductive filler is less than 10% by weight, the thermal conductivity may be insufficient and the viscosity may be too low. Low viscosity means that the resin flows too easily from the tool during coating or molding, making the process difficult to handle and control. On the other hand, if the content of the filler is higher than 90% by weight, the bonding strength of the molding material may decrease and the viscosity may be too high. High-viscosity molding materials can cause poor workability because the material cannot flow out of the tool during coating or molding. In addition, the molding compound 40 may include more than one kind of filler. For example, polytetrafluoroethylene (PTFE) can be used as the second filler to further improve the electrical insulation properties of the molding compound 40 . In conclusion, the molding compound 40 preferably has an elastic modulus greater than 1.0 GPa and a linear thermal expansion coefficient in the range of about 5×10 ⁻⁶ K ⁻¹ to 15×10 ⁻⁶ K ⁻¹ .

FIG. 10 is a schematic cross-sectional view after removing the upper half of the molding compound 40 . Here, the upper half of the molding compound 40 may be removed through a planarization process, such as lapping/grinding, to expose the vertical connection member 20 and the electrical isolation member 30 from above. process or chemical mechanical polishing (CMP) process. After planarization, the thickness of the molding material 40 is in the range of 0.05 mm to 1 mm (preferably 0.1 to 0.4 mm), and the outer surface 401 of the molding material 40 is in contact with the top side 201 of the vertical connecting member 20 and the top side of the electrical isolation member 30 Faces 301 are substantially coplanar.

11 and 12 are respectively a cross-sectional schematic diagram and a top perspective schematic diagram of the routing circuit 50 fabricated by the patterned metal deposition method. First, the top surface of the structure can be metallized by various techniques such as electroplating, electroless plating, evaporation, sputtering, or combinations thereof to form a single or multilayer conductive layer (usually a copper layer). The conductive layer can be made of Cu, Ni, Ti, Au, Ag, Al, combinations thereof or other suitable conductive materials. Generally, a seed layer is formed on the topmost surface of the structure before electroplating the conductive layer to a desired thickness, wherein the seed layer may be composed of a diffusion resistance layer and a plating bus layer. The diffusion resistance layer is used to counteract the oxidation or erosion of the conductive layer (such as copper). In most cases, the diffusion barrier layer can also be used as an adhesion enhancement layer for the underlying material, and can be formed by physical vapor deposition (PVD), for example, Ti or TiW can be formed by sputtering with a thickness of about 0.01 μm to 0.1 μm Floor. However, the diffusion barrier layer can also be made of other materials, such as TaN or other suitable materials, and its thickness is not limited to the above range. The electroplating carrier layer is usually made of the same material as the conductive layer, and its thickness ranges from about 0.1 μm to 1 μm. For example, if the conductive layer is copper, the electroplating carrier layer is preferably a copper film made by physical vapor deposition or electroless plating. However, the electroplating carrier layer can also be made of other suitable materials, such as silver, gold, chromium, nickel, tungsten or combinations thereof, and its thickness is not limited to the above range.

After depositing the seed layer, a photoresist layer (not shown) is formed on the seed layer. The photoresist layer can be formed by a wet process (such as a spin-coating process) or a dry process (such as a laminated dry film). After the photoresist layer is formed, the photoresist layer is patterned to form openings, and then the openings are filled with coating metal (such as copper) to form the routing circuit 50 . After the metal is plated, an etching process is performed to remove the exposed seed layer, thereby forming conductive lines electrically isolated from each other. In this figure, the routing circuit 50 is a patterned metal layer, which extends laterally on the outer surface 401 of the molding material 40 and the top surface 301 of the electrical isolation member 30, and is in contact with and electrically coupled to the vertical connection member 20, while Thermal conduction to electrical isolator 30 . In addition, metallization may also be performed on the bottom surface of the structure to form a bottom cladding layer 60 , which contacts and completely covers the bottom metal layer 15 of the substrate 10 , the electrical isolator 30 and the molding compound 40 from below.

Accordingly, as shown in FIGS. 11 and 12 , the completed circuit board 100 includes a base plate 10, vertical connectors 20, an electrical isolator 30, a molding material 40, a routing circuit 50 and a bottom coating layer 60. . The electrical isolator 30 is disposed in the through opening 105 of the base board 10 , and the thickness of the electrical isolator 30 is greater than that of the base board 10 . The vertical connector 20 is disposed on the top circuit layer 13 of the base board 10 and is electrically coupled to the top circuit layer 13 . The molding material 40 covers and surrounds the sidewalls of the vertical connecting piece 20 and the sidewall of the electrical isolator 30 to provide a mechanical bonding force between the inner sidewall 109 of the base board 10 and the peripheral edge of the electrical isolator 30 . The routing circuit 50 extends laterally on the outer surface 401 of the molding material 40 and the top surface 301 of the electrical isolator 30 to provide horizontal routing, and is electrically coupled to the vertical connecting member 20 providing vertical routing. Therefore, the routing circuit 50 can be electrically connected to the top circuit layer 13 of the base board 10 through the vertical connection piece 20 . The bottom cladding layer 60 is a continuous and unpatterned metal layer, which is disposed under the base plate 10 and the electrical isolator 30 to provide a heat dissipation surface with an area larger than that of the electrical isolator 30 .

13 and 14 are respectively a cross-sectional view and a top perspective view of the semiconductor assembly 110 in which the semiconductor element 71 is electrically connected to the circuit board 100 shown in FIGS. 11 and 12 . The semiconductor device 71 (shown as a chip) is flip-chip mounted on the top surface of the electrical isolator 30 and is electrically coupled to the routing circuit 50 through the conductive bump 81 .

FIG. 15 is a schematic cross-sectional view of a circuit board of another solution in the first embodiment of the present invention. The circuit board 120 is similar to the structure shown in FIG. 11 , the difference is that it includes a metal filling hole 23 as the vertical connection piece 20 . Here, the metal filling hole 23 contacting the circuit layer 13 on the top of the base board 10 can be formed by depositing metal in the blind hole 41 of the molding material 40 .

FIG. 16 is a schematic cross-sectional view of a circuit board of another solution in the first embodiment of the present invention. The circuit board 130 is similar to the structure shown in FIG. 11 , the difference is that it includes conductive balls 25 (such as copper balls) as the vertical connectors 20 .

FIG. 17 is a schematic cross-sectional view of a circuit board of another solution in the first embodiment of the present invention. The circuit board 140 is similar to the structure shown in FIG. 11 , the difference is that it includes a metal filling hole 23 and a conductive ball 25 as the vertical connection piece 20 . Here, the metal filling hole 23 contacting the conductive ball 25 can be formed by depositing metal in the blind hole 41 of the molding material 40 .

FIG. 18 is a schematic cross-sectional view of a circuit board of another solution in the first embodiment of the present invention. The circuit board 150 is similar to the structure shown in FIG. 11 , the difference is that it further includes a passive element 73 embedded in the molding compound 40 . The passive element 73 is electrically coupled to the top circuit layer 13 of the base board 10 , and thus can be electrically connected to the routing circuit 50 through the vertical connection 20 .

[Example 2]

19-20 are diagrams of the fabrication method of the circuit board with the top build-up circuit in the second embodiment of the present invention.

For the purpose of brief description, any descriptions in the above-mentioned embodiment 1 that can be used for the same application are incorporated here, and it is not necessary to repeat the same descriptions.

19 is a schematic cross-sectional view of the top dielectric layer 911 and blind holes 913 formed on the structure of FIG. in the top dielectric layer 911. The top dielectric layer 911 can generally be deposited by lamination or coating methods, it contacts the electrical isolator 30, the molding material 40 and the routing circuit 50, and covers from above and extends laterally on the electrical isolator 30, the mold on the sealing material 40 and the routing circuit 50 . The top dielectric layer 911 typically has a thickness of 50 microns and can be made of epoxy, glass epoxy, polyimide, or the like. After depositing the top dielectric layer 911, the blind holes 913 can be formed by various techniques including laser drilling, plasma etching, and photolithography, and the blind holes 913 typically have a diameter of 50 microns. A pulsed laser can be used to increase laser drilling performance. Alternatively, a scanning laser beam can be used with a metal mask. Blind vias 913 extend through top dielectric layer 911 and are aligned with selected portions of routing circuitry 50 .

Referring to FIG. 20 , a top wire 915 is formed on the top dielectric layer 911 by metal deposition and metal patterning processes. The top wire 915 extends upward from the routing circuit 50 and fills the blind hole 913 to form a metallized blind hole 917 directly contacting the routing circuit 50 , while extending laterally on the top dielectric layer 911 . Therefore, the top wire 915 can provide horizontal signal routing in the X and Y directions and vertical routing through the blind hole 913 as an electrical connection to the routing circuit 50 .

The top lead 915 can be deposited as a single layer or multiple layers by various techniques, such as electroplating, electroless plating, evaporation, sputtering, or combinations thereof. For example, the top dielectric layer 911 is first catalyzed by electroless copper plating by immersing the structure in an activator solution, followed by electroless plating of a thin copper layer as a seed layer, and then electroplating. A second copper layer of desired thickness is formed on the seed layer. Alternatively, before depositing the electroplated copper layer on the seed layer, the seed layer can be sputtered to form a seed layer film such as titanium/copper. Once the desired thickness is achieved, the cladding layer can be patterned using various techniques to form the top wire 915, such as wet etching, electrochemical etching, laser-assisted etching, or a combination thereof, and using an etch mask (Fig. not shown) to define the top wire 915.

Accordingly, as shown in FIG. 20, the completed circuit board 200 includes a base plate 10, vertical connectors 20, an electrical isolator 30, a molding material 40, a routing circuit 50, a bottom coating layer 60 and a Top build-up circuitry 91 . In this figure, the top build-up circuit 91 is a multi-layer build-up circuit including a top dielectric layer 911 and top conductive lines 915 . Accordingly, the combination of the top wiring layer 13 , the vertical contacts 20 and the top build-up circuit 91 can provide routing/interconnection for semiconductor devices assembled on the wiring board 200 .

FIG. 21 is a schematic cross-sectional view of a semiconductor assembly 210 that electrically connects the semiconductor element 71 to the circuit board 200 of FIG. 20 . The semiconductor device 71 (shown as a chip) is aligned with the electrical isolator 30 and is flip-chip connected to the top build-up circuit 91 to be electrically coupled to the top lead 915 through the conductive bump 81 . Since the top build-up circuit 91 can be thermally connected to the electrical isolator 30 through the metallized blind hole 917 as a heat pipe, the heat generated by the semiconductor element can be conducted to the electrical isolator 30 and then dissipated.

[Example 3]

22 is a schematic cross-sectional view of a circuit board according to a third embodiment of the present invention, the routing circuit is electrically connected to the bottom circuit layer of the base board.

For the purpose of brief description, any descriptions in the above embodiments that can be used for the same application are incorporated here, and the same descriptions do not need to be repeated.

The circuit board 300 is similar to the structure shown in FIG. 11 , the difference is that the base board 10 is a multi-layer circuit board, and the bottom coating layer 60 is a patterned metal layer. In this figure, the base board 10 includes a core layer 12 , a top wiring layer 13 , a bottom wiring layer 16 and metallized vias 18 . The top wiring layer 13 and the bottom wiring layer 16 extend laterally on two sides of the core layer 12 respectively. The top circuit layer 13 includes top contact pads 131 for electrical connection to the vertical connectors 20 , and the bottom circuit layer 16 includes bottom contact pads 161 for next-level electrical connection. The metallized vias 18 extend through the core layer 12 to provide an electrical connection between the top contact pad 131 and the bottom contact pad 161 . Therefore, the routing circuit 50 on the top surface of the electrical isolator 30 and the outer surface of the molding material 40 can be electrically connected to the bottom circuit layer 16 of the base board 10 through the vertical connection 20 , the top circuit layer 13 and the metalized through hole 18 . In this embodiment, the base board 10 is not limited to a multilayer circuit board, and it can also be a co-fired ceramic, a molded interconnect substrate (MIS for short) or a build-up substrate.

FIG. 23 is a schematic cross-sectional view of a circuit board of another solution in the third embodiment of the present invention. The circuit board 310 is similar to the structure shown in FIG. 22 , the difference is that it further includes a metallized through hole 55 directly contacting the routing circuit 50 and the bottom circuit layer 16 . The metallized through hole 55 extends through the base board 10 and the molding material 40 , and provides an electrical connection between the routing circuit 55 and the circuit layer 16 at the bottom of the base board 10 .

FIG. 24 is a schematic cross-sectional view of the semiconductor assembly 320 in which the semiconductor element 71 and the passive element 73 are electrically connected to the circuit board 300 shown in FIG. 22 . The semiconductor element 71 is flip-chip mounted on the top surface of the electrical isolator 30 and electrically coupled to the routing circuit 50 through the conductive bump 81 . The passive element 73 is mounted on the top side of the molding compound 40 and electrically coupled to the routing circuit 50 .

FIG. 25 is a schematic cross-sectional view of a semiconductor assembly of another solution in the third embodiment of the present invention. The semiconductor assembly 330 is similar to the structure shown in FIG. 24 , the difference is that it further includes an additional semiconductor element 72 and a sealing material 89 . The additional semiconductor device 72 is mounted on the semiconductor device 71 and electrically coupled to the routing circuit 50 through the bonding wire 83 . The sealing material 89 covers the semiconductor elements 71 , 72 , the passive element 73 and the bonding wire 83 from above.

FIG. 26 is a schematic cross-sectional view of a semiconductor assembly in another solution of the third embodiment of the present invention. The semiconductor assembly 340 is similar to the structure shown in FIG. 24, the difference is that (i) the routing circuit 50 does not extend laterally to the electrical isolator 30, (ii) the semiconductor element 71 is connected to the electrical isolator 30, and passes through The bonding wire 83 is electrically coupled to the routing circuit 50 , (iii) a sealing material 89 is provided to cover the semiconductor element 71 , the passive element 73 and the bonding wire 83 from above.

FIG. 27 is a schematic cross-sectional view of another solution of the semiconductor assembly in the third embodiment of the present invention. The semiconductor assembly 350 is similar to the structure shown in FIG. 26 , the difference is that the routing circuit 50 extends laterally on the electrical isolator 30 to provide a thermal pad 51 between the electrical isolator 30 and the semiconductor element 71 . In this figure, the thermal pad 51 is electrically connected to the base board 10 through the vertical connector 20 to form a ground connection.

[Example 4]

28 is a schematic cross-sectional view of a circuit board according to a fourth embodiment of the present invention, in which no vertical connectors are embedded in the molding compound.

For the purpose of brief description, any descriptions in the above embodiments that can be used for the same application are incorporated here, and the same descriptions do not need to be repeated.

The circuit board 400 is similar to the structure shown in FIG. 11 , the difference is that the top circuit layer is not provided on the top side of the base board 10 , and no vertical connectors are deposited and formed on the top side of the base board 10 . In this embodiment, the inner wall 109 of the base plate 10 can control the accuracy of placing the electrical isolator 30 . Accordingly, the electrical isolator 30 can be precisely controlled at a predetermined position, and the peripheral edge of the electrical isolator 30 will be close to the inner wall 109 of the through opening 105 of the base plate 10 . In addition, the base plate 10 can also be a single-layer structure, and can be made of composite materials, such as FR-4 (woven glass fiber cloth impregnated with epoxy resin, which has flame resistance), bismaleimide-triazol Bismaleimide-triazine (BT) resin, molding compound, ceramic, glass, plastic, metal or other materials.

[Example 5]

29 is a schematic cross-sectional view of a circuit board according to a fifth embodiment of the present invention, which has a top build-up circuit electrically connected to a bottom circuit layer of a base board.

For the purpose of brief description, any descriptions in the above embodiments that can be used for the same application are incorporated here, and the same descriptions do not need to be repeated.

The circuit board 500 is similar to the structure shown in FIG. 22 , the difference is that it further includes a top build-up circuit 91 . In this figure, the top build-up circuit 91 is a multi-layer build-up circuit including a top dielectric layer 911 and top conductive lines 915 . The top dielectric layer 911 is in contact with the electrical isolator 30 , the molding compound 40 and the routing circuit 50 , covers from above and extends laterally on the electrical isolating member 30 , the molding material 40 and the routing circuit 50 . The top lead 915 extends laterally on the top dielectric layer 911 and includes a metallized blind via 917 in the top dielectric layer 911 . Therefore, the top build-up circuit 91 can be electrically connected to the routing circuit 50 through the metallized blind hole 917 contacting the routing circuit 50 , and thermally connected to the electrical isolator 30 .

[Example 6]

30-31 are schematic diagrams of a method of manufacturing a circuit board with a top build-up circuit and a bottom build-up circuit in the sixth embodiment of the present invention.

For the purpose of brief description, any descriptions in the above embodiments that can be used for the same application are incorporated here, and the same descriptions do not need to be repeated.

30 is a schematic cross-sectional view of forming a bottom dielectric layer 931 and a blind hole 933 on the structure of FIG. 29 , wherein the bottom dielectric layer 931 is located on the bottom cladding layer 60 , and the blind hole 933 is located in the bottom dielectric layer 931 . The bottom dielectric layer 931 contacts the bottom cladding layer 60 , covers from below and extends laterally on the bottom cladding layer 60 . The blind via 933 extends through the bottom dielectric layer 931 and is aligned with a selected portion of the bottom cladding layer 60 .

Referring to FIG. 31 , a bottom conductive line 935 is formed on the bottom dielectric layer 931 by metal deposition and metal patterning processes. The bottom wire 935 extends downward from the bottom cladding layer 60 and fills the blind hole 933 to form a metallized blind hole 937 directly contacting the bottom cladding layer 60 while extending laterally on the bottom dielectric layer 931 . In this stage, the bottom build-up circuit 93 is formed under the base board 10 and the electrical isolator 30 , and is electrically coupled to the bottom circuit layer 16 of the base board 10 through the metallized blind hole 937 and is thermally connected. to electrical isolation 30 . In this figure, the bottom build-up circuit 93 is a multi-layer build-up circuit, which includes a bottom dielectric layer 931 and a bottom conductive line 935 .

Accordingly, as shown in FIG. 31 , the completed circuit board 600 includes a base plate 10, vertical connectors 20, an electrical isolator 30, a molding material 40, a routing circuit 50, a bottom coating layer 60, a A top build-up circuit 91 and a bottom build-up circuit 93 . In this embodiment, the combination of the base board 10 , the vertical connector 20 and the routing circuit 50 can provide an electrical connection between the top build-up circuit 91 and the bottom build-up circuit 93 , so that the circuit board 600 has stackability. In addition, the metallized blind holes 917 of the top build-up circuit 91 and the metallized blind holes 937 of the bottom build-up circuit 97 can be used as heat pipes for heat dissipation.

As shown in the above embodiments, the present invention constructs a unique circuit board, which has an electrical isolator and a base plate, and has good reliability. Preferably, the circuit board mainly includes an electrical isolator, a base plate, a molding material and a routing circuit, wherein (i) the electrical isolator is inserted into the through opening of the base plate, and the thickness of the electrical isolator is greater than The thickness of the base plate; (ii) the molding material covers the top side of the base plate and the side wall of the electrical isolator, and fills the gap between the peripheral edge of the electrical isolator and the inner wall of the through opening; (iii) the routing circuit is deposited on the molding material The outer surface, and optionally further laterally extends on the top surface of the electrical isolator.

The circuit board may further include a plurality of vertical connectors, wherein (i) the top side of each vertical connector is not covered by the molding compound, and the bottom side contacts and is electrically coupled to the top contact pad of the base board, ( ii) The molding compound covers the sidewalls of the vertical connectors, and (iii) the routing circuit is contacted and electrically coupled to the top side of the vertical connectors.

The electrical isolation can provide a platform for attaching chips, and the optional vertical connection can provide a vertical signal conduction path, or provide a ground/power plane for energy transfer and return. More specifically, the electrical isolator can be made of a thermally conductive and electrically insulating material, and typically has a high modulus of elasticity and a low coefficient of thermal expansion (eg, 2x 10 ^-6 K ^-1 to 10x 10 ^-6 K ^-1 ). Therefore, the thermal expansion coefficient of the electrical isolator can match that of the semiconductor element connected thereon, so as to provide a CTE compensation platform for the semiconductor element, and can greatly compensate or reduce the internal stress caused by CTE mismatch. In addition, the electrical isolation element also provides a preliminary heat conduction path for the semiconductor element, so that the heat generated by the semiconductor element can be conducted away.

The substrate plate can be used to control the accuracy of the placement of the electrical isolation and/or provide a platform for the deposition of the vertical connectors. More specifically, the base plate can be a metal plate or a single-layer or multi-layer structure with an insulating layer, and the inner sidewall of the base plate can be used as a positioning member when placing the discharge separator. The inner side walls of the base plate can be laterally aligned with the four side surfaces of the electrical isolator to define a region with the same or similar shape as the electrical isolator, so as to avoid lateral displacement of the electrical isolator. Therefore, the inner sidewall of the base plate is close to the peripheral edge of the electrical isolation element, so as to control the placement precision of the electrical isolation element. And/or, the substrate board can be used to increase the routing flexibility of the circuit board. For example, the top side of the base board can be provided with a top circuit layer to provide additional routing, which can be electrically connected to the routing circuit on the molding compound through vertical connectors embedded in the molding compound. The bottom side of the routing circuit can further have a plurality of bottom contact pads electrically coupled to the top contact pads. Accordingly, the circuit board can provide electrical contacts at the top side and the bottom side. In a preferred embodiment, the bottom contact pads may be provided by the bottom wiring layer at the bottom side of the base board and electrically coupled to the top wiring layer through metallized vias in the base board.

The molding compound can be formed by paste printing, compressive molding, transfer molding, liquid injection molding, spin coating or other suitable methods , to interface with the electrical isolator and base plate. Preferably, the molding material has an elastic modulus greater than 1.0 GPa and a linear thermal expansion coefficient ranging from about 5x10 ^-6 K ^-1 to 15x 10 ^-6 K ^-1 , and the thickness of the molding material in contact with the base plate ranges from 0.05 to 1mm. Furthermore, in order to have sufficient thermal conductivity and proper viscosity, the molding compound may include 10 to 90 weight percent of a thermally conductive filler. For example, the thermally conductive filler can be made of aluminum nitride (AlN), aluminum oxide, silicon carbide (SiC), tungsten carbide, boron carbide, silicon dioxide, or the like, and preferably has relatively high thermal conductivity, relatively high resistivity and relatively low coefficient of thermal expansion. Accordingly, the molding compound can exhibit better heat dissipation performance and electrical insulation performance, and its low CTE characteristic can avoid peeling or cracks in routing circuits or interfaces. In addition, the maximum particle size of the thermally conductive filler may be 25 μm or less.

The routing circuitry on the outer surface of the molding compound may further extend to the top surface of the electrical isolator. Therefore, the routing circuit can provide electrical contacts on the electrical isolator for flip-chip connection of the semiconductor element on the electrical isolator, or the routing circuit can provide a thermal pad on the electrical isolator for the semiconductor element to face up. Connect on top. The routing circuit can be metal-deposited by a photolithography process. Preferably, the routing circuit is formed by sputtering followed by electroplating.

Before or after providing the molding compound, the vertical connectors electrically connected to the base board can be formed. Examples of vertical connectors include, but are not limited to, metal posts, conductive balls, bonding wires, metal vias, or combinations thereof. More specifically, the top side of the vertical connector can contact the routing circuit, while the bottom side contacts the top contact pad of the base board, thereby providing an electrical connection between the routing circuit and the base board. For example, the vertical connectors can contact and be electrically coupled to selected locations of the top wiring layer in the substrate board. Accordingly, the double-layer routing including the top wiring layer and the bottom wiring layer can improve the routing flexibility of the circuit board.

For further wiring, the circuit board may further include a top build-up circuit or/and a bottom build-up circuit, wherein the top build-up circuit is located on the routing circuit, and the bottom build-up circuit is located on the bottom surface of the electrical spacer and the bottom side of the base board below. The top build-up circuit can cover the top surface of the electrical isolator and the outer surface of the molding material, and is electrically coupled to the routing circuit and thermally connected to the electrical isolator. The bottom build-up circuit can cover the bottom surface of the electrical isolator and the bottom side of the base board, and is electrically coupled to the bottom contact pad of the base board while being thermally connected to the electrical isolator. Preferably, the top build-up circuit and the bottom build-up circuit are multilayer build-up circuits without a core layer, which respectively include at least one dielectric layer and wires, and the wires fill blind holes in the dielectric layer and extend laterally on the dielectric layer. The dielectric layer and the wires can be formed continuously and alternately, and can be formed repeatedly if necessary. Accordingly, the top build-up circuit and the bottom build-up circuit can be thermally connected to the electrical isolator through the metallized blind hole, and electrically coupled to the routing circuit and the base board respectively. In addition, the outermost wires of the top build-up circuit and the bottom build-up circuit can respectively be connected with conductive contacts, such as solder balls or bonding wires, for electrical transmission and mechanical connection with assemblies, electronic components or other components.

The present invention also provides a semiconductor assembly, wherein a semiconductor element (such as a chip) is placed on the top surface of the electrical isolator of the circuit board and electrically coupled to the routing circuit. More specifically, the semiconductor element can be electrically connected to the circuit board through various connection media, wherein the connection media can include conductive bumps (such as gold bumps or solder bumps) disposed on the routing circuit of the circuit board, or Bond wires connected to the board's routing circuitry. When the circuit board includes the top build-up circuit, the semiconductor device can be disposed on the top build-up circuit, and at the same time, the semiconductor device is aligned with the electrical isolation and electrically coupled to the top build-up circuit.

The assembly can be a primary or secondary single crystal or polycrystalline device. For example, the assembly may be a first level package including a single chip or multiple chips. Alternatively, the assembly may be a second level module comprising a single package or multiple packages, where each package may comprise a single or multiple chips. The semiconductor element can be a packaged chip or an unpackaged chip. In addition, the semiconductor element can be a bare chip, or a wafer-level packaged die, and the like.

The term "coverage" means incomplete as well as complete coverage in vertical and/or lateral directions. For example, the bottom build-up circuitry can cover the electrical isolator, molding compound, and substrate underneath, regardless of whether another component (such as a bottom coating) is located between the bottom build-up circuitry and the electrical isolator, or between the bottom build-up circuitry and the mold. between encapsulants, and between the bottom build-up circuitry and the substrate board.

The terms "connected to" and "connected to" include contact and non-contact with one or more elements. For example, a semiconductor device can be mounted on an electrical isolator, regardless of whether the semiconductor device is separated from the electrical isolator by routing circuits and conductive bumps.

The term "alignment" refers to the relative position of elements, whether the elements are spaced apart from each other or adjacent to each other, or one element is inserted and extends into another element. For example, when an imaginary horizontal line intersects the inner sidewall of the base plate and the peripheral edge of the electrical isolator, the inner sidewall of the base plate is laterally aligned with the peripheral edge of the electrical isolator, regardless of whether there is a gap between the inner sidewall of the base plate and the peripheral edge of the electrical isolator. Having other elements that intersect an imaginary horizontal line, with or without another imaginary element intersecting the peripheral edge of the electrical isolator but not the inner side of the base plate, or the inner side of the base plate but not the peripheral edge of the electrical isolator horizontal line. Likewise, in a preferred embodiment, partially metalized blind vias of the top and bottom build-up circuits are aligned with the electrical isolation.

The term "near" means that the width of the gap between elements does not exceed the maximum acceptable range. As in the prior art in the art, when the gap between the peripheral edge of the electrical isolator and the inner sidewall of the base plate is not narrow enough, the electrical isolator cannot be accurately restricted to a predetermined position. The maximum acceptable limit of the gap between the peripheral edge of the electrical isolator and the inner sidewall of the base plate can be determined according to the desired accuracy when the electrical isolator is disposed at the predetermined position. Therefore, the descriptions "the peripheral edge of the electrical isolator is close to the inner wall of the through-opening" and "the inner wall of the base plate is close to the outer peripheral edge of the electrical isolator" mean that the gap between the outer peripheral edge of the electrical isolator and the inner wall of the through-opening is narrow enough to prevent electrical isolation The position error of the part exceeds the maximum acceptable error limit. For example, the gap between the peripheral edge of the electrical isolator and the inner sidewall of the through opening may be in a range of approximately 25 μm to 100 μm.

The terms "electrically connected" and "electrically coupled" mean direct or indirect electrical connection. For example, the semiconductor device can be electrically connected to the routing circuit through the top build-up circuit, but the semiconductor device does not contact the routing circuit.

The circuit board of the present invention has many advantages. For example, the electrical isolator can provide a CTE-compensated platform for mounting semiconductor devices, and at the same time provide a heat dissipation path for dissipating heat generated by the semiconductor devices. The molding compound provides mechanical support and acts as a separator between the routing circuitry and the substrate, and between the electrical isolation and optional vertical connections. The routing circuit can provide a horizontal electrical routing of the circuit board, and the optional vertical connector can provide a vertical electrical routing to electrically connect the routing circuit on the molding compound with another horizontal electrical routing in the base board. The circuit board prepared by this method has high reliability, low price, and is very suitable for mass production.

The manufacturing method of the present invention has high applicability, and combines various mature electrical and mechanical connection technologies in a unique and progressive manner. In addition, the fabrication method of the present invention can be implemented without expensive tools. Therefore, compared with the traditional technology, this manufacturing method can greatly improve the yield, yield, efficiency and cost-effectiveness.

The embodiments described herein are for illustration purposes, and these embodiments may simplify or omit elements or steps known in the art so as not to obscure the characteristics of the present invention. Similarly, for clarity of the drawings, the drawings may also omit repeated or unnecessary components and component symbols.

Claims (22)

1. a kind of wiring board comprising：

One substrate plate runs through opening it includes a top side, a bottom side, positioned at multiple top contact pads of the top sides and one, In should through opening inner sidewall extend to the bottom side from the top side；

One is electrically isolated part, is set to should running through in opening for the substrate plate, wherein the bottom surface of the electric isolution part and the substrate plate The bottom side in coplanar, and the thickness of the electric isolution part is greater than the thickness of the substrate plate；

One molding material, covers the top side of the substrate plate, and extend into the peripheral edge of the electric isolution part with should be through opening A gap between the inner sidewall of mouth, wherein the outer surface of the molding material and the top surface of the electric isolution part are in coplanar；

One routing circuit is set on the outer surface of the molding material；And

Multiple vertical connections are set on the top side of the substrate plate, and are embedded into the molding material, and be electrically coupled to The top contact pads of the routing circuit and the substrate plate.

2. wiring board as described in claim 1, wherein the routing circuit is more extended laterally in the top surface of the electric isolution part On.

3. wiring board as described in claim 1, wherein the top contact pads are the selected position of a top line layer, and The top line layer is located at the top sides of the substrate plate.

4. wiring board as described in claim 1, wherein the substrate plate also includes multiple bottoms contact at the bottom side Pad is electrically coupled to the top contact pads by the metallization perforation in the substrate plate.

5. wiring board as described in claim 1 further includes a bottom coating, it is located at the bottom surface of the electric isolution part Place, and the hot conducting in the bottom side with the substrate plate.

6. wiring board as described in claim 1, wherein the electric isolution part is the electric insulation ceramics block for having thermal conductivity.

7. wiring board as described in claim 1, wherein the vertical connections are made of metal, the metal be selected from by Cu, Group composed by Ti, Ni, Au, Ag, Sn and Sn alloy, and the Sn alloy contains Ag, Cu, Bi or combinations thereof.

8. wiring board as described in claim 1 further includes a top build-up circuitry, is set on the routing circuit, and electricity Property is coupled to the routing circuit, and hot is conducted to the electric isolution part.

9. wiring board as claimed in claim 4 further includes a bottom build-up circuitry, is set to the bottom surface of the electric isolution part And the lower section of the bottom side of the substrate plate, and it is electrically coupled to the bottom engagement pad of the substrate plate, and hot be conducted to this It is electrically isolated part.

10. a kind of semiconductor group body, including：

The wiring board as described in claim 1；And

Semiconductor element is set on the top surface of the electric isolution part, and is electrically coupled to the routing circuit.

11. semiconductor group body as claimed in claim 10, wherein the semiconductor element is electrically coupled to this by closing line Routing circuit.

12. semiconductor group body as claimed in claim 10, wherein the routing circuit more extends laterally being somebody's turn to do in the electric isolution part On top surface, and the semiconductor element is electrically coupled to the routing circuit by conductive bump.

13. semiconductor group body as claimed in claim 10, wherein the substrate plate also includes to connect positioned at multiple bottoms of the bottom side Touch pad is electrically coupled to the top contact pads.

14. semiconductor group body as claimed in claim 10, wherein the wiring board further includes a top build-up circuitry, setting In on the routing circuit, and be electrically coupled to the routing circuit, and it is hot be conducted to the electric isolution part, and the semiconductor element is set It is placed in the top build-up circuitry, and by the top build-up circuitry, is electrically coupled to the routing circuit.

15. semiconductor group body as claimed in claim 13, wherein the wiring board further includes a bottom build-up circuitry, setting In the lower section of the bottom side of bottom surface and substrate plate of the electric isolution part, and the bottom for being electrically coupled to the substrate plate connects Touch pad, and hot it is conducted to the electric isolution part.

16. a kind of equipped with the method for manufacturing circuit board for being electrically isolated part comprising following step：

One substrate plate is provided, it includes a top side, a bottom side and one through opening, wherein should through opening inner sidewall from the top Side extends to the bottom side；

By one electric isolution part be inserted into the substrate plate should through opening, and the electric isolution part peripheral edge close to should through opening The inner sidewall, and the bottom side of the bottom surface of the electric isolution part and the substrate plate is in coplanar, wherein the thickness of the electric isolution part Degree is greater than the thickness of the substrate plate；

A molding material is provided on the top side of the substrate plate, and the molding material extends into the periphery sides of the electric isolution part Edge and the gap being somebody's turn to do between the inner sidewall of opening, wherein the outer surface of the molding material and the top surface of the electric isolution part are in It is coplanar；And

A routing circuit is formed on the outer surface of the molding material.

17. production method as claimed in claim 16 further includes a step：Multiple vertical connections are formed in the substrate plate On the top side, wherein the substrate plate also includes multiple top contact pads positioned at the top sides, and the vertical connections are electrical It is coupled to the routing circuit and the top contact pads of the substrate plate.

18. production method as claimed in claim 16, wherein the routing circuit is more extended laterally in the top of the electric isolution part On face.

19. production method as claimed in claim 17, wherein the substrate plate also includes that multiple bottoms at the bottom side connect Touch pad is electrically coupled to the top contact pads.

20. production method as claimed in claim 16, wherein forming the routing circuit in the step on the molding material includes One sputtering process.

21. production method as claimed in claim 16 further includes a step：A top build-up circuitry is formed in the routing circuit On, wherein the top build-up circuitry is electrically coupled to the routing circuit, and hot is conducted to the electric isolution part.

22. production method as claimed in claim 19 further includes a step：A bottom build-up circuitry is formed in the electric isolution part The bottom surface and the substrate plate the bottom side lower section, wherein the bottom build-up circuitry is electrically coupled to the bottom of the substrate plate Portion's engagement pad, and hot it is conducted to the electric isolution part.