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CN108878398B - 包括导电凸块互连的半导体器件 - Google Patents

包括导电凸块互连的半导体器件 Download PDF

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Publication number
CN108878398B
CN108878398B CN201710343078.7A CN201710343078A CN108878398B CN 108878398 B CN108878398 B CN 108878398B CN 201710343078 A CN201710343078 A CN 201710343078A CN 108878398 B CN108878398 B CN 108878398B
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Prior art keywords
die
semiconductor
conductive bumps
semiconductor device
substrate
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CN201710343078.7A
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CN108878398A (zh
Inventor
严俊荣
狄晓峰
陈治强
莫金理
吴明霞
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Shandi Trading Shanghai Co ltd
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SanDisk SemiConductor Shanghai Co Ltd
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Priority to CN201710343078.7A priority Critical patent/CN108878398B/zh
Priority to US15/617,867 priority patent/US10283485B2/en
Priority to KR1020180030301A priority patent/KR102044092B1/ko
Publication of CN108878398A publication Critical patent/CN108878398A/zh
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Abstract

公开了一种半导体器件，所述半导体器件包括以阶梯式偏移配置堆叠的半导体裸片，其中，不同层级上的半导体裸片的裸片键合焊盘使用一个或多个导电凸块而互连。

Description

包括导电凸块互连的半导体器件
背景技术
对便携式消费电子产品的需求的强劲增长正在驱动对高容量存储设备的需要。非易失性半导体存储器设备(比如闪存存储卡)正变得广泛用于满足对数字信息存储和交换的日益增长的需求。它们的便携性、多功能性和坚固的设计与其高可靠性和大容量一起使得此类存储器设备对用于许多电子设备是理想的，包括例如数码相机、数字音乐播放器、视频游戏控制台、PDA和蜂窝电话。
虽然已知许多不同的封装体配置，但是闪存存储卡一般可以被制造成系统级封装(SiP)或多芯片模块(MCM)，其中，多个裸片安装且互连在小占用面积衬底上。衬底总体上可以包括刚性电介质基底，刚性电介质基底具有在一侧或两侧上蚀刻出的导电层。裸片与(多个)导电层之间形成了电连接，并且(多个)导电层提供了用于将裸片连接至主机设备的电引线结构。一旦进行了裸片与衬底之间的电连接，组件将则通常被包入提供保护性封装的模制化合物中。
为了最高效地使用封装体占用面积(Footprint)，已知将半导体裸片堆叠在彼此顶部上。为了提供对半导体裸片上键合焊盘的访问，将裸片堆叠，或者利用相邻裸片之间的间隔层完全覆盖彼此，或者利用偏移。在偏移配置中，将裸片堆叠在另一裸片的顶部上，从而使得下部裸片的键合焊盘在左侧被暴露。
使用接线键合来互连裸片堆叠中的半导体裸片具有一些缺点。这些缺点包括接线摇摆(Wire Sweep)，其中，键合接线之间的间隔例如在处置或模制包封过程中发生变化。接线摇摆可能改变相邻接线的互感并且还可能导致电短路。另一个缺点为半导体封装体中的最上部键合接线的高度可增加所述封装体的整体高度。
附图说明
图1是根据本技术的实施例的半导体器件的整体制造过程的流程图。
图2是根据本技术的实施例的所述制造过程中第一步的半导体器件的侧视图。
图3是根据本技术的实施例的所述制造过程中第二步的半导体器件的顶视图。
图4是根据本技术的实施例的所述制造过程中第三步的半导体器件的侧视图。
图5是在本技术的半导体器件中使用的半导体裸片的透视图。
图6是根据本技术的实施例的所述制造过程中第四步的半导体器件的侧视图。
图7是根据本技术的实施例的所述制造过程中第五步的半导体器件的侧视图。
图8是根据本技术的实施例的所述制造过程中第五步的半导体器件的简化透视图，其中，所述裸片堆叠中的所述半导体裸片与导电凸块电互连。
图9是根据本技术的替代性实施例的半导体器件的侧视图，其中，所述裸片堆叠中的所述半导体裸片与导电凸块电互连。
图10是根据本技术的进一步替代性实施例的半导体器件的侧视图，其中，所述裸片堆叠中的所述半导体裸片与导电凸块电互连。
图11是根据本技术的实施例的完整半导体器件的侧视图。
图12和图13是根据本技术的替代性实施例的半导体器件的侧视图和透视图，其中，所述裸片堆叠中的所述半导体裸片与低高度接线键合电互连。
具体实施方式
现在将参考附图描述本技术，在实施例中，本技术涉及一种半导体器件，所述半导体器件包括以阶梯式偏移配置而堆叠的半导体裸片，其中，不同层级上的半导体裸片的裸片键合焊盘使用一个或多个导电凸块而互连。所使用的导电凸块的数量可以取决于所施加的凸块的高度以及裸片堆叠中的半导体裸片的高度。导电凸块堆叠在彼此的顶部上以便匹配或几乎匹配半导体裸片的高度。然后将上部导电凸块部分施加在凸块堆叠上并且部分施加在下一上部半导体裸片的裸片键合焊盘上。
要理解的是，本技术可以采用许多不同形式来实施并且不应解释为局限于在此阐述的所述实施例。相反，提供这些实施例使得本公开将是彻底和完整的，并且将本技术完全地传达给本领域技术人员。的确，本技术意在涵盖这些实施例的多种替代形式、修改形式以及等同形式，它们包括在所附权利要求书定义的本技术的范围和精神内。而且，在本技术的以下详细描述中，给出了很多具体细节以提供对本技术的透彻理解。然而，对于本领域的技术人员显而易见的是：可以在没有此类具体细节的情况下实施本技术。
如在此可使用的术语“顶部”和“底部”、“上部”和“下部”以及“竖直”和“水平”被举例并仅出于示意性目的，并且不意在限制本技术的描述，因为所引用的项在位置和取向上可以交换。同样，如在此所使用的，术语“基本上”、“几乎”和/或“约”意味着指定的尺寸或参数可以在给定应用的可接受制造容差内变化。在一个实施例中，所述可接受制造容差为±.25％。
现在将参照图1的流程图以及图2至图13的顶视图、侧视图和透视图解释本技术的实施例。虽然图2至图13各自示出了单独半导体器件100或其一部分，但要理解的是，所述器件100可以与衬底面板上的多个其他封装体一起被分批处理，从而实现规模经济。衬底面板上的器件100的行和列的数量可以不同。
用于制造半导体器件100的衬底面板以多个衬底102开始(再次，图2至图13中示出了一个这样的衬底)。衬底102可以是各种不同芯片承载介质，包括印刷电路板(PCB)、引线框或带式自动焊接(TAB)带。当衬底102是PCB时，所述衬底可以由如图2中所示具有顶部导电层105和底部导电层107的内核103形成。内核103可以由各种电介质材料形成，比如例如聚酰亚胺层压材料、环氧树脂(包括RF4和RF5)、双马来酰亚胺三嗪(BT)等。所述内核可以具有40微米(μm)至200μm之间的厚度，但是在替代性实施例中所述内核的厚度可以在这个范围之外变化。在替代性实施例中，内核103可以是陶瓷或有机的。
环绕内核的导电层105、107可以由铜或铜合金、镀铜或镀铜合金、合金42(42Fe/58Ni)、镀铜钢、或其他适用于衬底面板的金属和材料形成。所述导电层可以具有约10μm至25μm的厚度，但是在替代性实施例中所述层的厚度可以在这个范围之外变化。
图1是根据本技术的实施例的用于形成半导体器件180的制造过程的流程图。在步骤200中，可以对第一半导体器件100的衬底102进行钻孔以在衬底102中限定通孔过孔104。所示出的过孔104是举例而言，并且衬底102可以比附图中所示的包括更多的过孔104，并且它们与附图中所示的相比可以处于不同位置。接下来在步骤202中在顶部和底部导电层中的一者或两者上形成电导图案。所述(多个)电导图案可以包括电迹线106、衬底的顶表面上的接触焊盘109以及衬底的底表面上的接触焊盘108，如例如图3和图4中所示。迹线106和接触焊盘109、108(仅其中一部分在附图中编号)是举例而言的，并且衬底102可以比附图中所示的包括更多迹线和/或接触焊盘，并且它们与附图中所示的相比可以处于不同位置。在一个实施例中，衬底102可以包括处于衬底102的相对边缘的一行或多行接触焊盘109，如图3中所示。在进一步实施例中，接触焊盘109可以被设置为沿着衬底的一条边缘、三条边缘或全部四条边缘。进一步的实施例可以采用多层衬底，除了所述顶表面和/或底表面上的那些之外，所述多层衬底包括内部电导图案。
在各实施例中，成品半导体器件可以用作BGA(球栅阵列)封装体。衬底102的下表面可以包括如下文所解释的用于接收焊球的接触焊盘108。在各实施例中，成品半导体器件180可以是LGA(平面栅格阵列)封装体，所述LGA封装体包括用于将成品器件180可移除地耦合在主机设备内的触指。在此类实施例中，所述下表面可以包括触指，而非接收焊球的接触焊盘。衬底102的顶表面和/底表面上的电导图案可以通过各种适当工艺形成，包括例如各种光刻工艺。
再次参照图1，接下来在步骤204中可以对衬底102进行检查。此步骤可以包括自动光学检查(AOI)。一旦被检查，在步骤206中就可以将焊接掩模110(图4)施涂至衬底。在施涂阻焊掩模之后，在步骤208中，可以通过已知的电镀或薄膜沉积工艺为接触焊盘、以及电导图案上的任何其他有待焊接的区域镀上例如Ni/Au、合金42等。然后在步骤210中衬底102经历操作测试。在步骤212，可以在视觉上检查衬底，包括例如自动化视觉检查(AVI)和最终视觉检查(FVI)从而检查杂质、擦伤和变色。这些步骤中的一个或多个可以省略或以不同的顺序执行。
假定衬底102通过检查，接下来在步骤214中可以将无源部件112(图3)固定至衬底102。所述一个或多个无源部件可以包括例如一个或多个电容器、电阻器和/或电感器，但是可以考虑其他部件。所示的无源部件112仅是举例而言，并且在进一步的实施例中数量、类型和位置可以不同。
在步骤220中，接下来可以将许多半导体裸片堆叠在衬底102上。图5展示了可以使用的半导体裸片124的示例。半导体裸片124可以例如是存储器裸片(比如NAND闪存裸片)，但是可以使用其他类型的裸片124。这些其他类型的半导体裸片包括但不限于控制器裸片，比如ASIC、或RAM(比如SDRAM)。半导体裸片124可以进一步替代性地用于将器件100形成为功率半导体器件(比如例如开关或整流器)。
每个半导体裸片124可以包括多个裸片键合焊盘132，所述多个裸片键合焊盘形成以端接在半导体裸片124的边缘124a处。具体地，当来自半导体裸片124的半导体晶片的一部分仍被分割时，晶片刻线可以被限定以与每个半导体裸片的晶片的表面上限定的裸片键合焊盘132相交。当沿着所述刻线对所述晶片进行分割时，通过每个半导体裸片上的裸片键合焊盘进行切割，从而使裸片键合焊盘132端接在半导体裸片124的边缘处。在实施例中，每个裸片键合焊盘132可以具有大约70μm的长度和宽度，尽管在进一步的实施例中所述长度和宽度可以彼此成比例或不成比例地不同。可以具有比图5中示出的更多的裸片键合焊盘132，并且在进一步的实施例中所述裸片键合焊盘可以沿着半导体裸片124的多于一条边缘形成。
可以在研磨之前例如通过隐形划分从晶片划分半导体裸片124。在此技术中，激光器在晶片的表面下方制作定位孔以用于精确划分晶片，所述孔导致裂纹，所述裂纹传播至晶片的上表面和下表面(例如在晶片背磨步骤的过程中)。理解的是，在进一步的实施例中，可以在研磨之前通过隐形划分之外的方法(包括例如通过锯、激光器或水射流切割方法)对晶片进行划分以便产生半导体裸片124。
当包括多个半导体裸片124时，半导体裸片124可以以偏移阶梯式配置被堆叠在彼此顶部上从而形成如图6中所示的裸片堆叠120。图6至图12中的堆叠120中的裸片124的数量仅是举例而言，并且实施例可以包括堆叠120中的不同数量的半导体裸片，包括例如1、2、4、8、16、32或64个裸片。在进一步的实施例中，可以存在其他数量的裸片。可以存在不止一个裸片堆叠120，其中交替的堆叠在相反方向上呈阶梯式。在这种实施例中，内插层(未示出)可以设置在堆叠之间以便电连接相邻裸片堆叠的裸片键合焊盘。所述裸片可以使用裸片附接膜固定至衬底和/或彼此。作为一个示例，裸片粘贴膜可以是来自汉高股份有限公司(Henkel AG&Co.KGaA)的8988UV环氧基树脂，被固化至B级以初步固定堆叠120中的裸片124，并随后固化至最终C级以初步固定堆叠120中的裸片124。
在步骤224中，裸片堆叠120中的半导体裸片可以电连接至彼此以及至衬底102。根据本技术的方面，导电凸块可以用于电互连堆叠120中每个层级的半导体裸片124上的裸片键合焊盘。现在将参考图7至图10更详细地解释本技术的此特征。
通常，导电凸块138可以沉积在裸片124的衬底接触焊盘109和裸片键合焊盘132上以便电连接竖直对准的接触焊盘/裸片键合焊盘的对应列，向上达到裸片堆叠。例如，在图8中，导电凸块138电互连堆叠120中的每个裸片124的最左侧接触焊盘109和最左侧裸片键合焊盘132。导电凸块138电互连堆叠120中的每个裸片124的次最左侧接触焊盘109和次最左侧裸片键合焊盘132。并且跨接触焊盘109、裸片键合焊盘132依此类推。
可以通过不同的技术来形成导电凸块138，但是在一个示例中，可以例如通过凸焊法来形成所述导电凸块，其中，通过以其他方式用于形成接线键合的接线键合毛细管(未示出)来形成并沉积所述凸块。在这种实施例中，从最下部位置(在衬底102的接触焊盘109上)处开始，可以通过由电子火焰熄灭(EFO)在所述接线键合毛细管内的接线尖端处形成熔球来沉积第一导电凸块。然后可以使用升高温度和超声波振荡将所述熔球按压在所述接触焊盘109上并留下来以形成导电凸块138。在一个实施例中，可以使用120KHz的超声波频率在20g的压力下在145℃的温度下持续12ms形成导电凸块138。这些参数仅是举例而言，并且在进一步的实施例中每个参数可以不同。一旦导电凸块138被固定，则接线键合毛细管可以拉离开以便折断接线并且使所述导电凸块138保持在位。
在接触焊盘109上形成第一导电凸块138之后，接线键合毛细管可以继续在剩余接触焊盘109上水平形成类似的导电凸块。并且之后，水平导电凸块行一次一行地被建立在其上，向上达到裸片堆叠。可替代地，从初始导电凸块开始，附加导电凸块138可被竖直地建立向上达到裸片堆叠。并且之后，可以跨裸片堆叠一次一列地建立附加的竖直导电凸块列。在进一步的实施例中，可以按照其他顺序在接触焊盘109和裸片键合焊盘132上形成导电凸块138。
现在具体参考图7和图8，导电凸块138可以被施加到接触焊盘109和裸片键合焊盘132以便建立竖直导电凸块列，所述竖直导电凸块列与堆叠120中的半导体裸片124彼此电互连并且电互连衬底102。所需的导电凸块138的数量取决于导电凸块138的高度以及堆叠120中的半导体裸片124的高度。图7和图8示出了示例，其中，导电凸块138的高度至少大致与裸片堆叠中的半导体裸片124(包括DAF层)的高度相同。在一个实施例中，这个高度可以是20μm到35μm，并且更具体地大约25μm，尽管在进一步的实施例中半导体裸片124和/或导电凸块138的高度可以高于或低于这个高度。
当导电凸块138的高度至少大致与裸片堆叠中的半导体裸片124的高度相同时，单个导电凸块(在此被称为基底导电凸块138a)可以首先被施加到接触焊盘109。在那个点处，基底导电凸块138a的上表面至少大致与第一半导体裸片124上的裸片键合焊盘132齐平。接线键合毛细管然后可以朝向第一半导体裸片124偏移并且沉积另一导电凸块138(在此被称为偏移互连导电凸块138b)，所述另一导电凸块部分地置于基底导电凸块138a上并且部分地置于第一半导体裸片的裸片键合焊盘132上。偏移互连导电凸块138b将接触焊盘109与第一半导体裸片的裸片键合焊盘132电互连。在实施例中，基底导电凸块138a和偏移互连凸块138b具有相同的大小。然而，可想到的是，在进一步的实施例中，基底导电凸块138a大于偏移互连凸块138b，或反之亦然。
接线键合毛细管朝向第一裸片偏移的以便沉积偏移互连导电凸块138b的量至少取决于偏移互连导电凸块138b的直径以及基底导电凸块138a与第一半导体裸片124之间的间隔。在实施例中，偏移互连导电凸块138b和基底导电凸块138a可以具有大致30到70μm的直径，并且更具体地大约50μm，尽管在进一步的实施例中偏移互连导电凸块138b和/或基底导电凸块的直径可以大于或小于那个直径。基底导电凸块138a可以与下一相邻半导体裸片间隔20μm。因此，在一个示例中，在沉积基底导电凸块138a之后，接线键合毛细管可以朝向裸片堆叠偏移35μm。在此示例中，50μm直径的偏移互连导电凸块138b在基底导电凸块138a上可以具有15μm并且在下一层级的裸片键合焊盘132上具有15μm。应理解的是，所有这些尺寸是举例而言，并且在进一步的实施例中每个尺寸可以不同。
在图7和图8中示出的实施例中，基底导电凸块138a的高度至少大致与相邻半导体裸片124(包括DAF层)的高度相同。然而，应当理解的是，基底导电凸块138a的高度可以高于或低于半导体裸片(包括DAF层)的高度。在这种实施例中，偏移互连导电凸块138b可以仍被施加到基底导电凸块138a和相邻裸片的裸片键合焊盘132两者上以便形成电互连，即使基底导电凸块138a和裸片键合焊盘132的上表面彼此并不平齐。在实施例中，裸片键合焊盘132的表面可以比基底导电凸块138a的高度高或低达50％，尽管在进一步的实施例中此差异可以小于50％。
为了将堆叠120中的第二半导体裸片124与第一半导体裸片(沿着第一竖直裸片键合焊盘列)电互连，接下来通过接线键合毛细管将基底导电凸块138a施加到第一半导体裸片的裸片键合焊盘132。此基底导电凸块138a靠近现有的偏移互连导电凸块138b而被放置在裸片键合焊盘132上。然后施加下一互连导电凸块138b以便互连第一和第二半导体裸片的相应裸片键合焊盘132。此过程竖直地继续向上达到裸片堆叠120，直到裸片键合焊盘的竖直列中的所有裸片键合焊盘132通过基底导电凸块138a和偏移互连导电凸块138b电互连。如以上所指出的，导电凸块在移至下一层级之前在给定层级上可以代替地被施加到所有接触焊盘109/裸片键合焊盘132，而不是构建竖直导电凸块138列。
在图7和图8的实施例中，导电凸块138小于裸片键合焊盘132。然而，在进一步的实施例中，导电凸块138可以大于裸片键合焊盘132或者至少大致与裸片键合焊盘132的大小相同。图9的侧视图中示出了这种实施例。在这种实施例中，第一导电凸块138可以被施加到接触焊盘109。在此实施例中，导电凸块138的高度至少大致等于裸片堆叠120中的半导体裸片124(包括DAF层)的高度，例如大约25μm。然后可以在堆叠120中的第一半导体裸片的裸片键合焊盘132上施加第二导电凸块138。
具有比裸片键合焊盘132更大的直径的第二导电凸块部分地置于施加到接触焊盘109的第一导电凸块上，因此将堆叠120中的第一半导体裸片124上的裸片键合焊盘与接触焊盘109电互连。在一个示例中，裸片键合焊盘可以是45μm长，并且导电凸块可以具有50μm的直径。在沉积基底导电凸块138a之后，接线键合毛细管可以朝向裸片堆叠偏移35μm。在此示例中，50μm直径的偏移互连导电凸块138b在基底导电凸块138a上可以具有15μm并且在下一层级的裸片键合焊盘132上具有15μm。应理解的是，所有这些尺寸是举例而言，并且在进一步的实施例中每个尺寸可以不同。以与电互连竖直列中的所有裸片键合焊盘132相类似的方式施加随后的导电凸块向上达到竖直裸片键合焊盘132列。附加的竖直列可以随后以类似的方式与导电凸块电互连。
在上述实施例中，导电凸块138的高度至少大致等于半导体裸片124的高度。然而，在进一步的实施例中，导电凸块138的高度可以小于半导体裸片124的高度。图10的侧视图中示出了这种实施例。此处，基底导电凸块138a通过接线键合毛细管竖直地施加在彼此的顶部上，以便建立基底导电凸块138a的柱。将基底导电凸块138a施加到所述柱直到所述柱的高度至少大致等于下一相邻半导体裸片124的高度。之后，可以如上所述地将偏移互连导电凸块138b部分地施加到所述柱中的最上部基底导电凸块138a上并且部分地施加到半导体裸片的下一相邻层级的裸片键合焊盘上。
柱中的基底导电凸块138a的数量可以例如在两个与四个之间，尽管在进一步的实施例中可以具有更多个。可以如以上解释的例如通过凸焊法来形成每个基底导电凸块138a，即通过由EFO在接线键合毛细管内的接线的尖端处形成球并且然后固定键合焊盘132上的所述凸块138a或者更低的基底导电凸块138a。接线键合毛细管可以在焊盘109或132上形成第一基底导电凸块138a、拉离开、在所述第一基底导电凸块上形成第二基底导电凸块138a，并依此类推直到完成凸块138a的柱。可替代地，接线键合毛细管可以在每个焊盘109、132上跨层级水平沉积第一凸块138a，然后在每个焊盘上在所述第一凸块上沉积第二凸块138a，并依此类推直到完成所有凸块柱。
在实施例中，基底导电凸块138a的柱被堆叠并且仍保持为单独的、不同的凸块。然而，可想到的是，基底导电凸块的柱熔化在一起以便形成单个大凸块，所述单个大凸块具有凸块柱的高度。类似地，所述一个或多个基底导电凸块138a和偏移互连凸块138b仍保持为单独的、不同的凸块。然而，可想到的是，所述一个或多个基底导电凸块和偏移互连导电凸块熔化在一起以便形成单个凸块，所述单个凸块具有单独且偏移的基底导电凸块和偏移互连凸块的轮廓。
在上述实施例中，一个或多个基底导电凸块138a和偏移互连导电凸块138b在凸焊法过程中由金或金合金形成。在进一步的实施例中，导电凸块138a和/或138b中的一个或多个导电凸块可以由另一种金属形成，诸如例如铜或焊锡。此外，基底导电凸块138a中的至少一些可以在形成半导体裸片124(当仍然是半导体晶片的一部分时)的过程中形成在裸片键合焊盘132上，而非在形成半导体裸片堆叠120之后通过接线键合毛细管形成。
在通过导电凸块138将裸片124与彼此电连接以及与衬底102电连接之后，可以在步骤234中并且如图11所示将半导体器件100包封在模制化合物142中。可以将半导体器件放置在包括上模板和下模板的模套(未示出)内。然后可以将熔化的模制化合物142注入模套中以将半导体器件100的部件包入保护性壳体中，例如在压缩模塑工艺中。模制化合物142可以包括例如固态环氧树脂、酚树脂、熔融二氧化硅、结晶二氧化硅、碳黑和/或金属氢氧化物。此类模制化合物是例如从住友集团(Sumitomo公司)和日东电工集团(Nitto-Denko公司)(均在日本设立总部)可获得的。可以考虑来自其他制造商的其他模制化合物。可以根据其他已知工艺施涂所述模制化合物，包括通过FFT(无流薄膜)模塑、传递模塑或注射模塑技术。
在半导体器件100将永久地固定至主机设备(诸如印刷电路板)的实施例中，可以在步骤236中将焊球144(图11)固定至所述器件100的衬底102的下表面上的接触焊盘108上。可以在半导体器件100将被用作LGA(平面栅格阵列)半导体封装体的实施例中省略所述焊球144。
如上所指出的，半导体器件100可以形成于衬底的面板上。在形成和包封器件100之后，在步骤240中可以使器件100与彼此单片化开来，从而形成如图11中所示的成品半导体器件100。可以通过各种切割方法中的任何一种对半导体器件100进行单片化，包括锯切、水射流切割、激光切割、水引导激光切割、干介质切割、以及金刚石涂层线切割。虽然直线切割将限定基本上矩形或正方形的半导体器件100，但是要理解的是，在本技术的进一步实施例中，半导体器件100可以具有矩形和正方形以外的形状。
在上述实施例中，使用导电凸块来形成电互连。在进一步的实施例中，可以使用低高度接线键合来形成电互连。图12和图13中示出了这种实施例。所述低高度接线键合(在此被称为“零接线环路高度”键合170)使用最短的接线长度在裸片124到裸片124与裸片到衬底102的接触焊盘109之间进行连接。可以使用接线键合毛细管(未示出)来形成所述接线键合170。
虽然接线键合170可以通过各种技术形成，但在一个实施例中，接线键合170可以形成为球焊。可以在堆叠120中的最上部半导体裸片的裸片键合焊盘132上形成柱形凸块172。之后，接线键合毛细管可以在移动至下一更低层级的裸片的相应裸片键合焊盘132时送出接线。所述毛细管然后可以施加压力、热量和超声波能量以便折断接线并且使其缝合至更低层级的裸片上的键合焊盘。所述接线键合毛细管然后可以在缝合键合的顶部形成下一柱形凸块并且在裸片堆叠下以及到衬底102上的相应接触焊盘109重复以形成竖直接线键合行。在进一步的实施例中，接线键合170可以通过其他技术形成。
随着接线从第一层级被拉至下一更低层级，其可以抵靠所述第一层级上的半导体裸片的边缘124a。这对于在每一层级的半导体裸片124之间形成的每个接线键合170来说是真实的。这最小化接线高度并且防止接线摇摆，所述接线摇摆可能引起电噪声以及可能地发生电短路。
总而言之，在一个示例中，本技术涉及一种半导体器件，所述半导体器件包括：衬底；多个半导体裸片，所述多个半导体裸片中的每个半导体裸片包括沿着所述半导体裸片的边缘的多个裸片键合焊盘，所述多个半导体裸片形成以阶梯式偏移模式相对于彼此堆叠的半导体裸片的裸片堆叠，所述阶梯式偏移模式暴露每个半导体裸片中的所述多个裸片键合焊盘；以及多个导电凸块，所述多个导电凸块电互连所述裸片堆叠的不同层级上的半导体裸片的所述裸片键合焊盘。
在进一步的示例中，本技术涉及一种半导体器件，所述半导体器件包括：衬底；多个半导体裸片，所述多个半导体裸片中的每个半导体裸片包括：第一表面、与所述第一表面相反的第二表面、以及多个裸片键合焊盘，所述多个裸片键合焊盘在所述半导体裸片的所述第一表面上沿着所述半导体裸片的边缘，所述多个半导体裸片以阶梯式偏移模式相对于彼此而堆叠以便形成裸片堆叠，第一半导体裸片的所述第一表面安装在所述堆叠的相邻层级中的第二半导体裸片的所述第二表面，所述阶梯式偏移模式暴露每个半导体裸片中的所述多个裸片键合焊盘；多个焊料凸块，所述多个焊料凸块彼此堆叠并且电互连所述裸片堆叠中的所述第一和第二半导体裸片的所述裸片键合焊盘。
在另一示例中，本技术涉及一种半导体器件，所述半导体器件包括：衬底；多个半导体裸片，所述多个半导体裸片中的每个半导体裸片包括沿着所述半导体裸片的边缘的多个裸片键合焊盘，所述多个半导体裸片形成以阶梯式偏移模式相对于彼此而堆叠的多层级的半导体裸片的裸片堆叠，所述阶梯式偏移模式暴露每个半导体裸片中的所述多个裸片键合焊盘，在不同层级彼此对准的裸片键合焊盘形成竖直裸片键合路径；以及多个导电凸块，所述多个导电凸块形成在所述裸片键合焊盘上，所述多个导电凸块中的一个或多个导电凸块电互连所述竖直裸片键合路径的相邻层级中的裸片键合焊盘，并且裸片键合焊盘对被安装在所述裸片键合焊盘上的一对导电凸块进行电互连。
在进一步的示例中，本技术涉及一种半导体器件，所述半导体器件包括：衬底装置；多个半导体裸片，所述多个半导体裸片中的每个半导体裸片包括沿着所述半导体裸片的边缘的焊盘装置，所述多个半导体裸片形成以阶梯式偏移模式相对于彼此而堆叠的半导体裸片的裸片堆叠，所述阶梯式偏移模式暴露每个半导体裸片中的所述焊盘装置；以及凸块装置，所述凸块装置电互连所述裸片堆叠的不同层级上的半导体裸片的所述焊盘装置。
如以上还指出的，在实施例中，本技术可以涉及一种半导体器件，所述半导体器件具有零接线环路高度键合接线。这种实施例可以包括：衬底；多个半导体裸片，所述多个半导体裸片中的每个半导体裸片包括沿着所述半导体裸片的边缘的多个裸片键合焊盘，所述多个半导体裸片形成以阶梯式偏移模式相对于彼此堆叠的半导体裸片的裸片堆叠，所述阶梯式偏移模式暴露每个半导体裸片中的所述多个裸片键合焊盘；以及多个接线键合，所述多个接线键合电互连所述裸片堆叠的不同层级上的半导体裸片的所述裸片键合焊盘，所述接线键合接触所述半导体裸片的所述边缘。
以上对技术的详细描述是出于展示和说明的目的呈现的。其并不旨在穷举或将技术限制为所公开的精确形式。鉴于以上的教导内容，许多修改和变体都是可能的。选择所描述的所述实施例是为了最佳地说明技术原理及其实际应用，从而由此使得本领域其他技术人员能够以不同的实施例和具有适合于所考虑到的实际用途的不同修改来最佳地利用所述技术。旨在使技术范围由所附权利要求来限定。

Claims (16)

1.一种半导体器件，包括：
衬底；
多个半导体裸片，所述多个半导体裸片中的每个半导体裸片包括多个裸片键合焊盘，所述多个半导体裸片形成以阶梯式偏移模式相对于彼此堆叠的半导体裸片的裸片堆叠，所述阶梯式偏移模式暴露每个半导体裸片中的所述多个裸片键合焊盘；以及
多个导电凸块，所述多个导电凸块由其自身电互连所述裸片堆叠的不同层级上的半导体裸片的所述裸片键合焊盘；
其中，所述多个导电凸块包括：一个或多个基底导电凸块，所述一个或多个基底导电凸块在所述多个裸片键合焊盘的第一裸片键合焊盘上；以及偏移互连导电凸块，所述偏移互连导电凸块形成在所述一个或多个基底导电凸块的顶部上并且相对于所述一个或多个基底导电凸块偏移。
2.如权利要求1所述的半导体器件，其中，所述偏移互连导电凸块部分地形成在所述一个或多个基底导电凸块的顶部上并且部分地形成在与所述裸片堆叠中的所述第一裸片键合焊盘竖直对准的第二裸片键合焊盘上。
3.如权利要求1所述的半导体器件，其中，所述一个或多个基底导电凸块包括单个基底导电凸块。
4.如权利要求3所述的半导体器件，其中，所述单个基底导电凸块的高度至少大致等于所述半导体裸片的裸片堆叠中的半导体裸片的高度。
5.如权利要求1所述的半导体器件，其中，所述一个或多个基底导电凸块包括堆叠成竖直柱的多个基底导电凸块。
6.如权利要求5所述的半导体器件，其中，所述多个基底导电凸块的累积高度至少大致等于所述半导体裸片的裸片堆叠中的半导体裸片的高度。
7.如权利要求1所述的半导体器件，其中，所述多个半导体裸片是闪存半导体裸片。
8.一种半导体器件，包括：
衬底；
多个半导体裸片，所述多个半导体裸片中的每个半导体裸片包括：
第一表面，
第二表面，所述第二表面与所述第一表面相反，以及
多个裸片键合焊盘，所述多个裸片键合焊盘在所述半导体裸片的所述第一表面上；
所述多个半导体裸片以阶梯式偏移模式相对于彼此堆叠以便形成裸片堆叠，第一半导体裸片的所述第一表面安装至所述堆叠的相邻层级中的第二半导体裸片的所述第二表面，所述阶梯式偏移模式暴露每个半导体裸片中的所述多个裸片键合焊盘；
多个导电凸块，所述多个导电凸块上下叠置并且物理地电互连所述裸片堆叠中的所述第一和第二半导体裸片的所述裸片键合焊盘；
其中，所述多个导电凸块包括一个或多个基底导电凸块以及偏移互连导电凸块，所述一个或多个基底导电凸块包括物理地固定至所述第一半导体裸片的裸片键合焊盘上的第一基底导电凸块，所述偏移互连导电凸块具有物理地固定至基底导电凸块的第一部分以及物理地固定至所述第二半导体裸片的裸片键合焊盘上的第二部分。
9.如权利要求8所述的半导体器件，其中，所述多个导电凸块包括在所述第一半导体裸片的裸片键合焊盘上堆叠的第一和第二导电凸块，所述第一和第二导电凸块相对于彼此偏移堆叠。
10.如权利要求8所述的半导体器件，其中，所述一个或多个基底导电凸块包括在所述第一半导体裸片的所述裸片键合焊盘上堆叠成竖直柱的多个基底导电凸块。
11.如权利要求10所述的半导体器件，其中，所述多个基底导电凸块的累积高度至少大致等于所述第二半导体裸片的高度。
12.如权利要求11所述的半导体器件，其中，所述第二半导体裸片的所述高度包括所述半导体裸片的厚度加上所述第二半导体裸片的所述第二表面上的一层裸片附接膜。
13.一种半导体器件，包括：
衬底；
多个半导体裸片，所述多个半导体裸片中的每个半导体裸片包括多个裸片键合焊盘，所述多个半导体裸片形成以阶梯式偏移模式相对于彼此而堆叠的多层级的半导体裸片的裸片堆叠，所述阶梯式偏移模式暴露每个半导体裸片中的所述多个裸片键合焊盘；以及
多个导电凸块，所述多个导电凸块形成在所述裸片键合焊盘上，所述多个导电凸块包括一个或多个基底导电凸块，所述一个或多个基底导电凸块在第一半导体裸片的第一裸片键合焊盘上，所述多个导电凸块包括偏移互连导电凸块，所述偏移互连导电凸块形成在所述一个或多个基底导电凸块的顶部上并且相对于所述一个或多个基底导电凸块偏移。
14.如权利要求13所述的半导体器件，其中，所述一个或多个基底导电凸块包括在所述第一裸片键合焊盘上堆叠成竖直柱的多个基底导电凸块。
15.如权利要求13所述的半导体器件，其中，所述偏移互连导电凸块包括：第一部分，所述第一部分部分地位于所述一个或多个基底导电凸块的顶部上；以及第二部分，所述第二部分部分地安装在与所述裸片堆叠中的所述第一裸片键合焊盘竖直对准的第二半导体裸片的第二裸片键合焊盘上。
16.如权利要求15所述的半导体器件，其中，所述一个或多个基底导电凸块包括第一组一个或多个基底导电凸块，所述半导体器件进一步包括第二组一个或多个基底导电凸块，所述第二组一个或多个基底导电凸块安装在除所述偏移互连导电凸块的所述第一部分之外的所述第一裸片键合焊盘上。
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