CN108874458A - A kind of the firmware starting method and multicore SoC device of multicore SoC - Google Patents
A kind of the firmware starting method and multicore SoC device of multicore SoC Download PDFInfo
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- CN108874458A CN108874458A CN201710325202.7A CN201710325202A CN108874458A CN 108874458 A CN108874458 A CN 108874458A CN 201710325202 A CN201710325202 A CN 201710325202A CN 108874458 A CN108874458 A CN 108874458A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
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Abstract
The present invention relates to the firmwares of multicore SoC a kind of to start method, is applied to multicore SoC device, and the multicore SoC device includes at least two identical CPU, passes through system bus shared memory between CPU, and firmware starting method includes：Each CPU controls the reset signal of some other CPU, using chain type bootstrap technique when firmware starts, successively guides some other CPU one by one by CPU, until completing the starting of all CPU cores.Multicore SMP architecture easily can be realized in such a way that low side CPU is cumulative through the invention, greatly mitigate the burden of developer.
Description
Technical field
The invention belongs to the technical field of SoC design, start method and more more particularly to the firmware of multicore SoC a kind of
Core SoC device.
Background technique
With the development of design and manufacturing technology, the integrated collection that develops to logic gate of the IC design from transistor
At present to develop to the integrated of IP, i.e. SoC (System-on-a-Chip) designing technique again.SoC can be effectively reduced electricity
Son/information system product development cost shortens the development cycle, improves the competitiveness of product, is futurity industry circle by use
Most important product development mode.When carrying out SoC design, it is sometimes desirable to which multi-core CPU cooperates, to reach higher
Overall performance index.
Currently, CPU architecture can be divided into AMP (isomery) and two kinds of SMP (isomorphism) in multicore SoC, in the former AMP (isomery)
Multiple CPU it is different, and multiple CPU in SMP (isomorphism) are identical.From the point of view of SoC firmware development design, SMP architecture
Firmware generally only need portion, and the firmware of AMP framework not only needs to compile at least two parts, generally can also be related to difference
Translation and compiling environment, bring additional expense to the exploitation debugging and performance optimization of firmware, therefore the present invention selects the more of SMP architecture
Core SoC.
However, the firmware Starting mode of multicore SoC has very big influence to the hardware design of SoC and firmware design, it is typical
Multicore SoC SMP architecture have certain hardware requirement, have dedicated hardware controls in the communication of multicore and synchronization aspects
The Cache consistency of multicore may be implemented in Snoop Control Unit (SCU) under logic, such as ARM architecture；And it needs
Want to guarantee on hardware inside each core cpu there is CPU ID register to read for software, for example Linux kernel is starting
Stage can read CPU ID register by smp_processor_id () function.This specific hardware requirement is set to SoC
Meter brings certain challenge：
On the one hand, communication and synchronization module are designed to IC brings biggish difficulty；
On the other hand, for the SMP architecture using cumulative CPU stone, CPU ID is can not to write in the IC design phase
Enter the register inside CPU, then also just can not controllably distribute cpu resource.
In conclusion in the prior art for the firmware starting method of multicore SoC by CPU core innernal CPU ID register
Limitation the problem of can not controllably distributing cpu resource and IC design in synchronous and communication the problem of, still lack effective solution
Certainly scheme.
Summary of the invention
The present invention is posted for the firmware starting method of the SoC of multicore in the prior art overcome by CPU core innernal CPU ID
The limitation of storage can not controllably distribute the problem of synchronous and communication in the problem of cpu resource and IC design, and it is more to provide one kind
The firmware starting method and multicore SoC device of core SoC.The present invention effectively realizes multicore in such a way that low side CPU is cumulative
SMP architecture greatly mitigates the burden of developer.
To achieve the goals above, the present invention is using a kind of following technical solution：
A kind of firmware starting method of multicore SoC, is applied to multicore SoC device, the multicore SoC device includes at least
By system bus shared memory between two identical CPU, CPU, firmware starting method includes：Each CPU is controlled
The reset signal of some other CPU is successively guided some other one by one using chain type bootstrap technique when firmware starts by CPU
CPU, until completing the starting of all CPU cores.
Further, the firmware starting method of multicore SoC a kind of specifically includes following steps：
(1) Bootrom process：Firmware is moved into memory by starting CPU from external memory, and is shared between CPU
Memory in specific bit install one indicate allow start CPU execute firmware code flag bit, by storage address weight
It is mapped to 0 address, is jumped into firmware process；
(2) firmware is executed since starting CPU；
Firmware process：Judge whether its mark is set, if being set, carries out basic initial work, and be arranged and work as
The flag bit of designated position in memory is revised as before entering major cycle by the preceding specific stack pointer of CPU into major cycle
The mark of next CPU, the reset signal for releasing next CPU wake up next CPU；
All CPU sequentially enter firmware entrance compilation, repeat above-mentioned firmware process and successively wake up next CPU, until calling out
Wake up whole CPU, realizes the firmware starting of multicore SoC.
Further, in the step (1), only start CPU and execute Bootrom process, when SoC is powered on, except starting CPU
Except other CPU lived by hardware reset.
Further, Bootrom process specifically includes following steps in the step (1)：
(1-1) is resetted CPU is started；
(1-2) Bootrom process brings into operation from the reseting address of starting CPU；
(1-3) starting CPU is by firmware from the memory that external memory is moved into intra-sharing；
Specific bit, which installs one, in the memory that (1-4) shares between CPU indicates that allowing to start CPU executes firmware code
Flag bit, the flag bit be set as CPU_0_ALLOWED mark；
(1-5) remaps the memory shared between CPU to start the reseting address of CPU and jump to firmware process；
(1-6) starting CPU enters firmware entrance compilation.
Further, in the step (1), the reseting address of CPU is 0 address；In the step (1), starting CPU is
CPU_0。
Further, whole CPU is performed both by firmware process in the step (2), and firmware process specifically includes following step
Suddenly：
(2-1) executes firmware since starting CPU, judges whether the mark for starting CPU is set, if being set, into
The basic initial work of row, and the specific stack pointer of current CPU is set, it, will storage before entering major cycle into major cycle
The flag bit of designated position is revised as the mark of next CPU in device, and the reset signal wake-up for releasing next CPU is next
CPU；
(2-2) next CPU is used as current CPU after being waken up, and firmware is executed since 0 address, judges by starting CPU's
Mark starts successively to judge whether the mark of each CPU is set, only after the mark for determining current CPU is set, setting
The specific stack pointer of current CPU modifies the flag bit of designated position in memory before entering major cycle into major cycle
For the mark of next CPU, the reset signal for releasing next CPU wakes up next CPU；
(2-3) repeats step (2) and successively wakes up next CPU, until whole CPU is waken up, what the last one was waken up
CPU, determine current CPU mark be set after, the specific stack pointer of current CPU is set, into major cycle.
Further, in the step (2-2), judge the mark that each CPU is successively judged by the mark of starting CPU
Whether it is set, if the mark of each CPU is not set, the mark of starting CPU is set, and attempt the starting of starting CPU.
Further, in the step (2-1), it is initial including interruption .data that starting CPU carries out basic initial work
Change .bss sections of initialization or system initialization operate.
The present invention is posted for the firmware starting method of the SoC of multicore in the prior art overcome by CPU core innernal CPU ID
The limitation of storage can not controllably distribute the problem of synchronous and communication in the problem of cpu resource and IC design, and it is more to provide one kind
The firmware starting method and multicore SoC device of core SoC.The present invention effectively realizes multicore in such a way that low side CPU is cumulative
SMP architecture greatly mitigates the burden of developer.
To achieve the goals above, the present invention uses following another technical solution：
A kind of multicore SoC device, the multicore SoC device start method based on the firmware of above-mentioned multicore SoC a kind of, including
Pass through system bus shared memory between at least two identical CPU, CPU.
Further, memory uses SRAM.
Compared with prior art, beneficial effects of the present invention：
(1) the firmware starting method and multicore SoC device of a kind of multicore SoC of the invention, by multicore SoC device
Reseting signal line and shared drive the reliable starting firmware of multicore can be realized, IC designer need not be concerned about the synchronization of CPU
And communication issue；
(2) the firmware starting method and multicore SoC device of a kind of multicore SoC of the invention, gets rid of CPU core innernal CPU
The limitation of ID register, stone integrate simpler；
(3) the firmware starting method and multicore SoC device of a kind of multicore SoC of the invention, the side started using chain type
Method, 3. chain types starting, compared with common all modes started from CPU by host CPU, reduces same between master-slave cpu
Step waits, and each CPU need to only start the next of oneself：CPU_0 starts CPU_1, and CPU_1 starts CPU_2, with such
It pushes away；
(4) the firmware starting method and multicore SoC device of a kind of multicore SoC of the invention, firmware development is simple, in addition to
Outside the stack pointer of each CPU, all operation addresses are specified by compiler and linker, it is not necessary to arrange address manually.
Detailed description of the invention
The accompanying drawings constituting a part of this application is used to provide further understanding of the present application, and the application's shows
Meaning property embodiment and its explanation are not constituted an undue limitation on the present application for explaining the application.
Fig. 1 is the structural schematic diagram of multicore SoC device of the present invention；
Fig. 2 is that the firmware of multicore SoC of the present invention starts the method flow diagram of method.
Specific embodiment：
It is noted that following detailed description is all illustrative, it is intended to provide further instruction to the application.Unless another
It indicates, all technical and scientific terms used herein has usual with the application person of an ordinary skill in the technical field
The identical meanings of understanding.
It should be noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to the illustrative embodiments of the application.As used herein, unless the context clearly indicates otherwise, otherwise singular
Also it is intended to include plural form, additionally, it should be understood that, when in the present specification using term "comprising" and/or " packet
Include " when, indicate existing characteristics, step, operation, device, component and/or their combination.
In the absence of conflict, the features in the embodiments and the embodiments of the present application can be combined with each other.It ties below
Closing attached drawing, the invention will be further described with embodiment.
Embodiment 1：
As background technique is introduced, exist in the prior art the firmware starting method of multicore SoC by CPU core inside
The limitation of CPU ID register can not controllably distribute the problem of synchronous and communication in the problem of cpu resource and IC design, mention
Start method and multicore SoC device for the firmware of multicore SoC a kind of.The present invention is effectively in such a way that low side CPU is cumulative
It realizes multicore SMP architecture, greatly mitigates the burden of developer.
In a kind of typical embodiment of the application, adopt the following technical scheme that：
As shown in Figure 1,
A kind of multicore SoC device, the multicore SoC device start method based on the firmware of above-mentioned multicore SoC a kind of, including
Pass through system bus shared memory between at least two identical CPU, CPU.
In the present embodiment, memory uses SRAM.
Embodiment 2：
As background technique is introduced, exist in the prior art the firmware starting method of multicore SoC by CPU core inside
The limitation of CPU ID register can not controllably distribute the problem of synchronous and communication in the problem of cpu resource and IC design, mention
Start method and multicore SoC device for the firmware of multicore SoC a kind of.The present invention is effectively in such a way that low side CPU is cumulative
It realizes multicore SMP architecture, greatly mitigates the burden of developer.
In a kind of typical embodiment of the application, adopt the following technical scheme that：
As shown in Fig. 2,
A kind of firmware starting method of multicore SoC, the multicore SoC device being applied in embodiment 1, the firmware starting side
Method includes：Each CPU controls the reset signal of some other CPU, using chain type bootstrap technique when firmware starts, by CPU
Some other CPU is successively guided one by one, until completing the starting of all CPU cores.
The firmware starting method of multicore SoC a kind of specifically includes following steps：
(1) Bootrom process：Firmware is moved into memory by starting CPU from external memory, and is shared between CPU
Memory in specific bit install one indicate allow start CPU execute firmware code flag bit, by storage address weight
It is mapped to 0 address, is jumped into firmware process；
(2) firmware is executed since starting CPU；
Firmware process：Judge whether its mark is set, if being set, carries out basic initial work, and be arranged and work as
The flag bit of designated position in memory is revised as before entering major cycle by the preceding specific stack pointer of CPU into major cycle
The mark of next CPU, the reset signal for releasing next CPU wake up next CPU；
All CPU sequentially enter firmware entrance compilation, repeat above-mentioned firmware process and successively wake up next CPU, until calling out
Wake up whole CPU, realizes the firmware starting of multicore SoC.
In the step (1), only starts CPU and execute Bootrom process, when SoC is powered on, its in addition to starting CPU
His CPU is lived by hardware reset.
In the present embodiment, in the step (1), the reseting address of CPU is 0 address；In the step (1), starting
CPU is CPU_0.
Bootrom process specifically includes following steps in the step (1)：
(1-1) resets CPU_0；
(1-2) Bootrom process brings into operation from the reseting address of CPU_0；
(1-3) CPU_0 is by firmware from the memory that external memory is moved into intra-sharing；
Specific bit installs one and indicates that CPU_0 is allowed to execute firmware code in the memory that (1-4) shares between CPU
Flag bit, the flag bit are set as CPU_0_ALLOWED mark；
The memory shared between CPU is remapped the reseting address for CPU_0 and jumps to firmware process by (1-5)；
(1-6) CPU_0 enters firmware entrance compilation.
Whole CPU is performed both by firmware process in the step (2), and firmware process specifically includes following steps：
(2-1) executes firmware since CPU_0, judges whether the mark CPU_0_ALLOWED of CPU_0 is set, if
It is set, carries out basic initial work, and the specific stack pointer of CPU_0 is set, into major cycle, before entering major cycle
The flag bit of designated position in memory is revised as to the mark CPU_1_ALLOWED of CPU_1, releases the reset signal of CPU_1
Wake up CPU_1；
(2-2) CPU_1 is used as current CPU after being waken up, and firmware is executed since 0 address, judges to be opened by the mark of CPU_0
Beginning successively judges whether the mark of each CPU is set, only after the mark CPU_1_ALLOWED for determining CPU_1 is set,
The specific stack pointer of CPU_1 is set, into major cycle, is repaired the flag bit of designated position in memory before entering major cycle
It is changed to the mark CPU_N_ALLOWED of CPU_N, the reset signal for releasing CPU_N wakes up next CPU_N；N is more than or equal to 2；
(2-3) repeats step (2-2) and successively wakes up next CPU, until whole CPU is waken up, what the last one was waken up
CPU_N, determine current CPU_N mark CPU_N_ALLOWED be set after, the specific stack pointer of current CPU is set, enter
Major cycle.
In the step (2), judge successively to judge whether the mark of each CPU is set by the mark of CPU_0, if
The mark of each CPU is not set, then the mark of CPU_0 is arranged, and attempts the starting of CPU_0.
In the step (2-1), CPU_0 carries out basic initial work including at the beginning of interruption .data initialization .bss sections
Beginningization or system initialization operation.
Compared with prior art, beneficial effects of the present invention：
(1) the firmware starting method and multicore SoC device of a kind of multicore SoC of the invention, by multicore SoC device
Reseting signal line and shared drive the reliable starting firmware of multicore can be realized, IC designer need not be concerned about the synchronization of CPU
And communication issue；
(2) the firmware starting method and multicore SoC device of a kind of multicore SoC of the invention, gets rid of CPU core innernal CPU
The limitation of ID register, stone integrate simpler；
(3) the firmware starting method and multicore SoC device of a kind of multicore SoC of the invention, the side started using chain type
Method, 3. chain types starting, compared with common all modes started from CPU by host CPU, reduces same between master-slave cpu
Step waits, and each CPU need to only start the next of oneself：CPU_0 starts CPU_1, and CPU_1 starts CPU_2, with such
It pushes away；
(4) the firmware starting method and multicore SoC device of a kind of multicore SoC of the invention, firmware development is simple, in addition to
Outside the stack pointer of each CPU, all operation addresses are specified by compiler and linker, it is not necessary to arrange address manually.
Above-mentioned, although the foregoing specific embodiments of the present invention is described with reference to the accompanying drawings, and the foregoing is merely the application
Preferred embodiment, it is not intended to limit the protection scope of the present invention, and for those skilled in the art, the application can
To there is various modifications and variations.Those skilled in the art should understand that based on the technical solutions of the present invention, this field
Technical staff does not need to make the creative labor the various modifications that can be made, equivalent replacement or deformation still in protection of the invention
Within range.
Claims (10)
1. the firmware of multicore SoC a kind of starts method, it is applied to multicore SoC device, it is characterized in that：
The multicore SoC device includes at least two identical CPU, passes through system bus shared memory, the firmware between CPU
Starting method includes：Each CPU controls the reset signal of some other CPU, using chain type bootstrap technique when firmware starts,
Some other CPU is successively guided by CPU one by one, until completing the starting of all CPU cores.
2. a kind of firmware of multicore SoC as described in claim 1 starts method, it is characterized in that：A kind of multicore SoC's consolidates
Part starting method specifically includes following steps：
(1) Bootrom process：Firmware is moved into memory by starting CPU from external memory, and that shares between CPU deposits
Specific bit installs one and indicates to allow to start the flag bit that CPU executes firmware code in reservoir, and storage address is remapped
At 0 address, jump into firmware process；
(2) firmware is executed since starting CPU；
Firmware process：Judge whether its mark is set, if being set, carry out basic initial work, and current CPU is set
The flag bit of designated position in memory is revised as next into major cycle by specific stack pointer before entering major cycle
The mark of a CPU, the reset signal for releasing next CPU wake up next CPU；
All CPU sequentially enter firmware entrance compilation, repeat above-mentioned firmware process and successively wake up next CPU, until waking up complete
Portion CPU realizes the firmware starting of multicore SoC.
3. a kind of firmware of multicore SoC as claimed in claim 2 starts method, it is characterized in that：In the step (1), only open
Dynamic CPU executes Bootrom process, and when SoC is powered on, other CPU in addition to starting CPU are lived by hardware reset.
4. a kind of firmware of multicore SoC as claimed in claim 2 starts method, it is characterized in that：In the step (1)
Bootrom process specifically includes following steps：
(1-1) is resetted CPU is started；
(1-2) Bootrom process brings into operation from the reseting address of starting CPU；
(1-3) starting CPU is by firmware from the memory that external memory is moved into intra-sharing；
Specific bit installs one and indicates to allow to start the mark that CPU executes firmware code in the memory that (1-4) shares between CPU
Will position, the flag bit are set as CPU_0_ALLOWED mark；
(1-5) remaps the memory shared between CPU to start the reseting address of CPU and jump to firmware process；
(1-6) starting CPU enters firmware entrance compilation.
5. a kind of firmware of multicore SoC as claimed in claim 2 starts method, it is characterized in that：In the step (1), CPU's
Reseting address is 0 address；In the step (1), starting CPU is CPU_0.
6. a kind of firmware of multicore SoC as claimed in claim 5 starts method, it is characterized in that：In the step (2) all
CPU is performed both by firmware process, and firmware process specifically includes following steps：
(2-1) executes firmware since starting CPU, judges whether the mark for starting CPU is set, if being set, carries out base
This initial work, and the specific stack pointer of current CPU is set, it, will be in memory before entering major cycle into major cycle
The flag bit of designated position is revised as the mark of next CPU, and the reset signal for releasing next CPU wakes up next CPU；
(2-2) next CPU is used as current CPU after being waken up, and firmware is executed since 0 address, judges the mark by starting CPU
Start successively to judge whether the mark of each CPU is set, only after the mark for determining current CPU is set, setting is current
The specific stack pointer of CPU, into major cycle, in the case where being revised as the flag bit of designated position in memory before entering major cycle
The mark of one CPU, the reset signal for releasing next CPU wake up next CPU；
(2-3) repeats step (2-2) and successively wakes up next CPU, until whole CPU, the last one CPU being waken up are waken up,
Determine current CPU mark be set after, the specific stack pointer of current CPU is set, into major cycle.
7. a kind of firmware of multicore SoC as claimed in claim 6 starts method, it is characterized in that：In the step (2), judgement
Successively judge whether the mark of each CPU is set by the mark of starting CPU, if the mark of each CPU is not set,
The mark of starting CPU is then set, and attempts the starting of starting CPU.
8. a kind of firmware of multicore SoC as claimed in claim 7 starts method, it is characterized in that：In the step (2-1), open
It includes interruption .data initialization .bss sections of initialization or system initialization operation that dynamic CPU, which carries out basic initial work,.
9. a kind of multicore SoC device, the multicore SoC device is consolidated based on a kind of any multicore SoC's of claim 1-8
Part, which starts, passes through system bus shared memory between method, including at least two identical CPU, CPU.
10. a kind of multicore SoC device as claimed in claim 9, it is characterized in that：Memory uses SRAM.
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| CN109800032A (en) * | 2019-01-31 | 2019-05-24 | 深圳忆联信息系统有限公司 | BOOTROM multicore loading method and device |
| CN109901890A (en) * | 2019-03-07 | 2019-06-18 | 深圳忆联信息系统有限公司 | A kind of method, apparatus, computer equipment and the storage medium of controller loading multi-core firmware |
| CN112256338A (en) * | 2020-10-27 | 2021-01-22 | 记忆科技(深圳)有限公司 | SOC starting method and device, computer equipment and storage medium |
| CN112905522A (en) * | 2021-02-22 | 2021-06-04 | 深圳市显控科技股份有限公司 | Multi-core shared starting system, control method thereof and storage medium |
| CN113687868A (en) * | 2021-08-31 | 2021-11-23 | 联想(北京)有限公司 | Equipment firmware starting method and device and electronic equipment |
| CN114356445A (en) * | 2021-12-28 | 2022-04-15 | 山东华芯半导体有限公司 | Multi-core chip starting method based on large and small core architectures |
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| CN114356445A (en) * | 2021-12-28 | 2022-04-15 | 山东华芯半导体有限公司 | Multi-core chip starting method based on large and small core architectures |
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