CN101504618B - Multi-core processor oriented real-time thread migration method - Google Patents

Abstract

The invention discloses a multi-core processor-oriented real-time thread migration method. The present invention makes full use of the characteristics of the multi-core hardware system framework of shared secondary cache and memory, thereby effectively realizing the real-time thread migration method on the multi-core processor. The present invention realizes hardware-supported thread migration initialization and thread migration between processor cores, does not need to spend any time polling system variables when threads are running, reduces data transmission between processor cores during thread migration, and obviously Improved thread execution performance and shortened thread migration time. The present invention can be used on various multi-core processors.

Description

Real-time thread migration method for multi-core processors

technical field

The invention relates to a thread migration method between processor cores on a multi-core hardware architecture.

Background technique

Due to the increase of processor clock frequency, the continuous rise of processor power consumption and temperature has led to the limit of processor manufacturers' competition in speed. Faced with the limit of this growth, microprocessor manufacturers have turned to the embrace of multi-core processor technology. Multi-core processor technology has opened up a new prospect for processor performance improvement. Some companies claim that the processors they produce will use multi-core architecture in an all-round way.

Multi-core processor chips provide better concurrency and better system performance per watt than single-core processor chips. Concurrency provides higher performance scaling for control systems, network routing, and other devices. If these systems take full advantage of the concurrency provided by multi-core processor chips, they will be able to greatly improve their performance. However, most software designers and software engineers lack corresponding experience and technology accumulation for this concurrent programming mode, so this is a big obstacle for taking advantage of multi-core processor technology.

This technical obstacle is obvious. For example, the management of shared resources on a multi-core chip is a great technical challenge. In most cases, each core in a multicore chip has an independent L1 cache and shared L2 cache, memory subsystem, interrupt subsystem, and peripherals. Thus, system designers must ensure that each core has exclusive access to certain resources. This design consideration brings higher design complexity. For example, if programs running on different cores need to cooperate with each other, then a feasible inter-process communication mechanism, a shared memory mechanism and a synchronization primitive mechanism to guarantee shared resources are needed. All aspects of the operating system need to be modified for the multi-core system in order to take full advantage of the performance improvement brought by the multi-core technology.

Therefore, the operating system's support for multi-core can greatly reduce the design difficulty brought about by multi-core technology. An operating system that supports multi-core takes full advantage of the advantages of a multi-core hardware platform, the key lies in the support of the operating system for multi-core. The operating system's support for multi-core at the thread level can lead to better performance.

Thread migration has been extensively studied in distributed systems. Distributed systems work together to complete computing tasks by cooperating with each node. Load balancing is difficult to achieve by statically distributing load through prior task placement. During the computing process, the load of each node will change dynamically, and thread migration is one of the methods to achieve dynamic load balancing in distributed systems. Thread migration is to transfer the threads running on one node to run on another node. It can retain the results of the execution on the source node without re-executing the thread. Most of the currently implemented thread migration mechanisms are implemented based on the checkpoint saving and restarting mechanism, that is, before migrating the process, the state data of the process is saved to the checkpoint file, and then the checkpoint file is transferred to another node. After the target node receives the entire checkpoint file, the migration thread will be resumed according to the checkpoint file. Each node in a distributed system does not share local memory, and a large amount of data must be transferred for each thread migration.

Similarly, in order to realize the dynamic load balance of the multi-core processor, or to improve the performance of the multi-core processor and reduce the energy consumption of the multi-core processor, it is necessary to perform thread migration between processor cores.

Contents of the invention

The purpose of the present invention is to provide a multi-core processor-oriented real-time thread migration method.

The technical scheme that the present invention solves its technical problem adopts is as follows:

1) Perform thread migration between processor cores, all processor cores have private first-level cache, shared second-level cache and memory;

2) Thread migration initialization supported by hardware:

In the first step, when each thread starts running, all migration point addresses of this thread are recorded in the operating system;

In the second step, the operating system saves all migration point addresses into a data structure of each thread, and writes the migration point addresses of threads running on each processor core into the debug register on the core. When a context switch occurs, the operating system updates the data in the debug register;

In the third step, when the operating system decides to migrate a thread, the operating system sets the flag bit in the debug register on the processor core where the thread is located to activate the debug register;

In the fourth step, when the thread execution instruction reaches the migration point address of the thread, a hardware interrupt will be generated and the thread migration will start;

3) Thread migration method:

When thread migration starts, the operating system wakes up the target processor core for thread migration, and then trains the target processor core according to the instruction execution results of the source processor core; when the training process ends, the operating system first releases the thread and clear the pipeline of the source processor core, then write the data in the first-level cache of the source processor core back to the second-level cache, and then transfer the data in the registers of the source processor core to the target processor core through the bus . Finally, the target processor core stores the received data into registers, and then starts executing the threads generated on the target processor core.

Compared with prior art, the beneficial effect of the present invention is:

(1) Efficiency. The present invention implements a real-time thread migration method for multi-core processors. The checkpoint-based thread migration method needs to continuously poll system variables to determine whether to perform thread migration during the thread execution process, and the thread migration initialization supported by hardware The method does not need to spend any time polling system variables, thus significantly improving the performance of thread execution. Since the data transmission process during thread migration on a multi-core processor only needs to write the data in the first-level cache back to the second-level cache, and then transfer the data in the registers on the source processor core to the target processor core through the bus. Therefore, the time for thread migration is significantly shortened.

(2) Reliability. The present invention properly changes the process of thread migration by carefully analyzing the process of thread migration in a distributed system, and carefully designs the data between the source processor core and the target processor core during thread migration initialization and thread migration. The transmission process ensures that the thread can be normally migrated between processor cores, so that the thread can continue to run normally after being migrated to the target processor core.

(3) Practicality. A multi-core processor-oriented real-time thread migration method proposed by the present invention can be used on various multi-core processors.

Description of drawings

FIG. 1 is a schematic diagram of a thread migration initialization process supported by hardware.

FIG. 2 is a schematic diagram of a thread migration process.

Detailed ways

1) Thread migration between processor cores, all processor cores have private first-level cache, shared second-level cache and memory:

In most current multi-core processor architectures, processor cores have a private L1 cache and share L2 cache and memory. All processor cores share memory, so there is no need to transfer code and data in shared memory during thread migration. All processor cores share the second-level cache. When threads migrate, the data in the first-level cache of the source processor core only needs to be written back to the second-level cache instead of being written back to the memory.

2) Thread migration initialization supported by hardware:

Most modern processors contain a series of debug registers. The PowerPC 405 processor contains four 32-bit instruction address compare registers. A hardware interrupt is generated when the value in the program count register equals the value in the address compare register of an activated instruction. Likewise, on other processors, a hardware interrupt is generated when the value in the program counter register equals the value in an enabled debug register. The hardware-supported thread migration initialization method using this mechanism makes the thread do not need to spend any time polling the variables in the system during execution. The hardware-supported thread migration initialization method, as shown in Figure 1, includes the following four steps:

In the first step, when a thread starts running, all migration point addresses of this thread are recorded in the operating system;

In the second step, the operating system saves all migration point addresses into a data structure of each thread, and writes the migration point addresses of threads running on each processor core into the debug register on the core. When a context switch occurs, the operating system will update the data in the debug register with the migration point address of the thread to be executed;

In the third step, when the operating system decides to migrate a thread to another processor core according to the resource manager, the operating system sets the flag bit in the debug register on the processor core where the thread is located to activate the debug register;

In the fourth step, when the thread execution instruction reaches the migration point address in the activated debug register on the processor core where the thread is located, a hardware interrupt will be generated and the thread migration will start;

3) Thread migration method:

As shown in Figure 2, when the thread migration starts, if the target processor core of the thread migration is closed, the operating system needs to wake up the target processor core of the thread migration, and then execute the target processor according to the instruction execution result of the source processor core. The cache and predictor on the core are trained. When the training process is over, the operating system first releases the threads on the source processor core and clears the pipeline of the source processor core, and then writes the data in the primary cache of the source processor core back into the secondary cache. When the source processor core writes the data in the first-level cache back to the second-level cache, the target processor core can access the second-level cache to obtain the correct data. Then the operating system transfers and stores the data in the registers of the source processor core to the shared memory through the bus, so that the target processor core can access the data. Finally, the operating system creates a new thread on the target processor core of the thread migration. The target processor core obtains the data in the registers of the source processor core by accessing the shared memory, and stores these data in its own registers, and then the target processor core The processor core starts executing the newly created thread.

Claims (1)

1. real-time thread migration method towards polycaryon processor is characterized in that:

1) carry out thread migration between processor core, all processor cores all have privately owned one-level cache, shared secondary cache and internal memory;

2) the thread migration initialization of hardware supported:

The first step, after each thread brought into operation, all migration point addresses of this thread all were recorded in the operating system;

Second step, operating system is saved in all migration point addresses in each thread data structure separately, and the migration point address of the thread that is moving on each processor core write in the debug registers on the nuclear, when the context switching took place, operating system was just upgraded the data in the debug registers;

In the 3rd step, in the time of thread of operating system decision migration, the zone bit that operating system just is provided with in the debug registers on this thread place processor core activates debug registers;

In the 4th step, when the thread execution instruction arrives the migration point address of thread, will produce a hardware interrupts and begin thread migration;

3) thread migration method:

When the beginning thread migration, operating system is waken the target processor nuclear of thread migration up, then according to the instruction execution result of source processor nuclear cache and fallout predictor on the target processor nuclear is trained; After training process finishes, operating system is the thread on the source of release processor core and empty the streamline of source processor nuclear at first, then the data among the one-level cache of source processor nuclear are write back among the secondary cache, then the data in the source processor nuclear register are examined to target processor by bus transfer; The ideal processor core begins to carry out the thread that produces then receiving data storage in register on target processor nuclear.

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