CN101504618A - Multi-core processor oriented real-time thread migration method - Google Patents
Multi-core processor oriented real-time thread migration method Download PDFInfo
- Publication number
- CN101504618A CN101504618A CNA2009100959582A CN200910095958A CN101504618A CN 101504618 A CN101504618 A CN 101504618A CN A2009100959582 A CNA2009100959582 A CN A2009100959582A CN 200910095958 A CN200910095958 A CN 200910095958A CN 101504618 A CN101504618 A CN 101504618A
- Authority
- CN
- China
- Prior art keywords
- thread
- migration
- processor
- nuclear
- operating system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000013508 migration Methods 0.000 title claims abstract description 71
- 230000005012 migration Effects 0.000 title claims abstract description 71
- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000012546 transfer Methods 0.000 claims description 4
- 238000013500 data storage Methods 0.000 claims description 3
- 238000012549 training Methods 0.000 claims description 3
- 230000005540 biological transmission Effects 0.000 abstract description 3
- 238000005516 engineering process Methods 0.000 description 6
- 238000013461 design Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005265 energy consumption Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 210000000481 breast Anatomy 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007717 exclusion Effects 0.000 description 1
- 238000007726 management method Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
Images
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
Abstract
本发明公开了一种面向多核处理器的实时线程迁移方法。本发明是充分利用了共享二级cache和内存的多核硬件体系架构的特点从而有效地实现了多核处理器上的实时线程迁移方法。本发明实现了硬件支持的线程迁移初始化和处理器核之间的线程迁移，在线程运行时不需要花任何时间来轮询系统变量，减少了线程迁移时处理器核之间的数据传输，明显提高了线程执行时的性能和缩短了线程迁移的时间。本发明可以用在各种多核处理器上。
The invention discloses a multi-core processor-oriented real-time thread migration method. The present invention makes full use of the characteristics of the multi-core hardware system framework of shared secondary cache and memory, thereby effectively realizing the real-time thread migration method on the multi-core processor. The present invention realizes hardware-supported thread migration initialization and thread migration between processor cores, does not need to spend any time polling system variables when threads are running, reduces data transmission between processor cores during thread migration, and obviously Improved thread execution performance and shortened thread migration time. The present invention can be used on various multi-core processors.
Description
Technical field
The present invention relates to carry out between the processor core on the multinuclear hardware systems framework method of thread migration.
Background technology
Because the growth of processor clock frequency, constantly riseing of processor energy consumption and temperature caused the limit of processor manufacturer in the speed competition.Face the limit of this growth, microprocessor manufacturer has invested the bosom of polycaryon processor technology one after another.The polycaryon processor technology is that processor performance promotes the new prospect of having opened up.Some company just claims that the processor of its production will use multi-core system structure comprehensively.
The polycaryon processor chip provides than the better concurrency of single core processor chip, better unit watt system performance.Concurrency is a control system, and equipment such as network route provide higher performance expansion.If these systems make full use of the concurrency that the polycaryon processor chip provides, can on performance, have greatly improved.Yet most software developer and software engineer lack corresponding experience and technological accumulation for this concurrency programming pattern, so this is a very big obstacle for the advantage of utilizing the polycaryon processor technology.
This technical obstacle is clearly, such as the management of the shared resource on the multi core chip is exactly a very big technological challenge.In most cases, each nuclear in the multi core chip has independently a level cache and a shared L2 cache, and memory subsystem interrupts subsystem and peripherals.Like this, system designer just must be guaranteed some resource of visit of each nuclear mutual exclusion.Consideration in this design has just brought higher design complexity.Such as the program of moving on different nuclear cooperates with each other if desired, so just needs a feasible Inter-Process Communication mechanism, the synchronization primitives mechanism of shared drive mechanism and guarantee shared resource.The every aspect of operating system all need be transformed just at multi-core system can make full use of the performance boost that multi-core technology is brought.
Therefore, operating system can reduce the design difficulty that multi-core technology is brought to a great extent to the support of multinuclear.Support the operating system of multinuclear to make full use of the advantage of multinuclear hardware platform for one, key is the support of operating system to multinuclear.Operating system can be brought more performance in the thread rank to the support of multinuclear.
Thread migration has carried out a large amount of research in distributed system.Distributed system is to finish calculation task jointly by collaborative each node.Distribute load to be difficult to reach load balance statically by prior task placement.In computation process, the load meeting of each node dynamically changes, and thread migration is one of method that realizes the distributed system balancing dynamic load.Thread migration is the thread that moves on a node to be transferred on the other node move.It can be retained in the result who has carried out on the source node and needn't re-execute this thread.In the middle of the thread migration mechanism that has realized at present, major part is based on the checkpoint and preserves that the mechanism that restarts realizes, promptly before migrating processes, the state of a process data are saved in check point file, this check point file is transferred on the other node then, after treating that destination node is received whole check point file, recover to move thread again according to check point file again.Each node is not share local internal memory in the distributed system, and each thread migration all will transmit lot of data.
Equally, in order to realize the balancing dynamic load of polycaryon processor, or, reduce the energy consumption of polycaryon processor, be necessary between processor core, to carry out thread migration in order to improve the performance of polycaryon processor.
Summary of the invention
The object of the present invention is to provide a kind of real-time thread migration method towards polycaryon processor.
The technical scheme that the present invention solves its technical matters employing is as follows:
1) carry out thread migration between processor core, all processor cores all have privately owned one-level cache, shared secondary cache and internal memory;
2) the thread migration initialization of hardware supported:
The first step, after each thread brought into operation, all migration point addresses of this thread all were recorded in the operating system;
Second step, operating system is saved in all migration point addresses in each thread data structure separately, and the migration point address of the thread that is moving on each processor core write in the debug registers on the nuclear, when the context switching took place, operating system was just upgraded the data in the debug registers;
In the 3rd step, in the time of thread of operating system decision migration, the zone bit that operating system just is provided with in the debug registers on this thread place processor core activates debug registers;
In the 4th step, when the thread execution instruction arrives the migration point address of thread, will produce a hardware interrupts and begin thread migration;
3) thread migration method:
When the beginning thread migration, operating system is waken the target processor nuclear of thread migration up, then according to the instruction execution result of source processor nuclear target processor nuclear is trained; After training process finishes, operating system is the thread on the source of release processor core and empty the streamline of source processor nuclear at first, then the data among the one-level cache of source processor nuclear are write back among the secondary cache, then the data in the source processor nuclear register are examined to target processor by bus transfer.The ideal processor core begins to carry out the thread that produces then receiving data storage in register on target processor nuclear.
Compared with prior art, the invention has the beneficial effects as follows:
(1) high efficiency.The present invention has realized a kind of real-time thread migration method towards polycaryon processor, wanting continuous land wheel to ask system variable in the thread implementation based on the thread migration method of checkpoint determines whether to carry out thread migration, and the thread migration initial method of hardware supported does not need flower to come the polling system variable any time, the performance when therefore obviously having improved thread execution.Data transmission procedure during owing to thread migration on polycaryon processor only need write back to the data among the one-level cache among the secondary cache, then the data in the register on the source processor nuclear are examined to target processor by bus transfer, therefore obviously shortened the time of thread migration.
(2) reliability.The present invention carries out careful analysis by the process to thread migration in the distributed system, suitably changed the process of thread migration, data transmission procedure when carefully having designed thread migration initialization and thread migration between source processor nuclear and the target processor nuclear, guaranteed that thread can normally move between processor core, made thread migration after target processor nuclear is gone up, can continue normal operation.
(3) practicality.A kind of real-time thread migration method towards polycaryon processor that the present invention proposes can be used on the various polycaryon processors.
Description of drawings
Fig. 1 is the synoptic diagram of the thread migration initialization procedure of hardware supported.
Fig. 2 is the synoptic diagram of thread migration process.
Embodiment
1) carry out thread migration between processor core, all processor cores all have privately owned one-level cache, shared secondary cache and internal memory:
In the present most polycaryon processor architectural framework, processor core all has privately owned one-level cache, and shared secondary cache and internal memory.All processor cores are shared drive all, so does not need to transmit code and data in the shared drive during thread migration.All processor cores are all shared secondary cache, and the data during thread migration among the one-level cache of source processor nuclear only need write back among the secondary cache and need not write back in the internal memory.
2) the thread migration initialization of hardware supported:
Most of modern processors all contain a series of debug registers.The PowerPC405 processor comprises 4 32 instruction address comparand register.When equaling a value in the instruction address comparand register that is activated, the value in the program counter register will produce a hardware interrupts.Similarly, in other processor, when equaling a value in the debug registers that is activated, the value in the program counter register also can produce a hardware interrupts.Utilize the thread migration initial method of this machine-processed hardware supported to make thread not need the colored variable that comes any time in the polling system in the process of implementation.The thread migration initial method of hardware supported as shown in Figure 1, comprises following four steps:
The first step, after a thread brought into operation, all migration point addresses of this thread all were recorded in the operating system;
Second step, operating system is saved in all migration point addresses in each thread data structure separately, and the migration point address of the thread that is moving on each processor core write in the debug registers on the nuclear, when context taking place switch, the data in the debug registers are upgraded in the migration point address that operating system is just used the thread that will carry out;
The 3rd step, when operating system according to thread of explorer decision migration to the another one processor core the time, the zone bit that operating system just is provided with in the debug registers on this thread place processor core activates debug registers;
In the 4th step, when the migration point address in the debug registers that is activated on the processor core of thread execution instruction arrival thread place, will produce a hardware interrupts and begin thread migration;
3) thread migration method:
As shown in Figure 2, when the beginning thread migration, if the target processor of thread migration nuclear has been closed, operating system need be waken the target processor nuclear of thread migration up, then according to the instruction execution result of source processor nuclear cache and fallout predictor on the target processor nuclear is trained.After training process finished, operating system is the thread on the source of release processor core and empty the streamline of source processor nuclear at first, then the data among the one-level cache of source processor nuclear is write back among the secondary cache.When source processor nuclear writes back to the data among the one-level cache among the secondary cache, target processor nuclear visit secondary cache just can obtain correct data.Operating system stores the data in the source processor nuclear register in the shared drive into by bus transfer then, and target processor nuclear just can be visited these data like this.At last, operating system is created a new thread on the target processor nuclear of thread migration, target processor nuclear is by the data in the visit shared drive acquisition source processor nuclear register, and these data storage in the register of oneself, then target processor nuclear just begins to carry out the thread of new establishment.
Claims (1)
1. real-time thread migration method towards polycaryon processor is characterized in that:
1) carry out thread migration between processor core, all processor cores all have privately owned one-level cache, shared secondary cache and internal memory;
2) the thread migration initialization of hardware supported:
The first step, after each thread brought into operation, all migration point addresses of this thread all were recorded in the operating system;
Second step, operating system is saved in all migration point addresses in each thread data structure separately, and the migration point address of the thread that is moving on each processor core write in the debug registers on the nuclear, when the context switching took place, operating system was just upgraded the data in the debug registers;
In the 3rd step, in the time of thread of operating system decision migration, the zone bit that operating system just is provided with in the debug registers on this thread place processor core activates debug registers;
In the 4th step, when the thread execution instruction arrives the migration point address of thread, will produce a hardware interrupts and begin thread migration;
3) thread migration method:
When the beginning thread migration, operating system is waken the target processor nuclear of thread migration up, then according to the instruction execution result of source processor nuclear target processor nuclear is trained; After training process finishes, operating system is the thread on the source of release processor core and empty the streamline of source processor nuclear at first, then the data among the one-level cache of source processor nuclear are write back among the secondary cache, then the data in the source processor nuclear register are examined to target processor by bus transfer.The ideal processor core begins to carry out the thread that produces then receiving data storage in register on target processor nuclear.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100959582A CN101504618B (en) | 2009-02-26 | 2009-02-26 | Real-time thread migration method for multi-core processors |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100959582A CN101504618B (en) | 2009-02-26 | 2009-02-26 | Real-time thread migration method for multi-core processors |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101504618A true CN101504618A (en) | 2009-08-12 |
| CN101504618B CN101504618B (en) | 2011-04-27 |
Family
ID=40976873
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009100959582A Expired - Fee Related CN101504618B (en) | 2009-02-26 | 2009-02-26 | Real-time thread migration method for multi-core processors |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101504618B (en) |
Cited By (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102495762A (en) * | 2011-11-16 | 2012-06-13 | 华为技术有限公司 | Thread scheduling method, thread scheduling device and multi-core processor system |
| CN101751295B (en) * | 2009-12-22 | 2012-08-29 | 浙江大学 | Method for realizing inter-core thread migration under multi-core architecture |
| CN102981805A (en) * | 2012-11-02 | 2013-03-20 | 浪潮(北京)电子信息产业有限公司 | Serial software response method and system |
| CN105009086A (en) * | 2014-03-10 | 2015-10-28 | 华为技术有限公司 | Method for switching processors, computer, and switching apparatus |
| US9292450B2 (en) | 2013-03-05 | 2016-03-22 | Imagination Technologies Limited | Migration of data to register file cache |
| CN105868016A (en) * | 2015-01-20 | 2016-08-17 | 复旦大学 | Thread transfer distribution method capable of preventing local overheat of multi-core processor |
| CN105930218A (en) * | 2016-04-18 | 2016-09-07 | 深圳市万普拉斯科技有限公司 | Computing resource frequency adjustment method and system |
| WO2017049592A1 (en) * | 2015-09-25 | 2017-03-30 | Intel Corporation | Method and apparatus to improve shared memory efficiency |
| CN106776018A (en) * | 2016-12-01 | 2017-05-31 | 三星（中国）半导体有限公司 | Host node for distributed system and method for parallel processing and equipment from node |
| CN106850749A (en) * | 2016-12-26 | 2017-06-13 | 联想(北京)有限公司 | A kind of method and device, the electronic equipment of online updating kernel |
| CN106980492A (en) * | 2016-01-15 | 2017-07-25 | 英特尔公司 | System, method and apparatus for determining the work arrangement on processor core |
| CN107980118A (en) * | 2015-06-10 | 2018-05-01 | 无比视视觉技术有限公司 | Use the multi-nuclear processor equipment of multiple threads |
| CN108156207A (en) * | 2016-12-02 | 2018-06-12 | 航天星图科技（北京）有限公司 | A kind of data processing method of multi-node system |
| CN108885559A (en) * | 2016-03-29 | 2018-11-23 | 微软技术许可有限责任公司 | Fast transfer workload among multiple processors |
| CN109254849A (en) * | 2018-08-31 | 2019-01-22 | 北京小米移动软件有限公司 | The operation method and device of application program |
| CN109614220A (en) * | 2018-10-26 | 2019-04-12 | 阿里巴巴集团控股有限公司 | A kind of multiple nucleus system processor and data-updating method |
| CN111338577A (en) * | 2020-02-21 | 2020-06-26 | 苏州浪潮智能科技有限公司 | Multi-core thread migration method and system of storage system and related components |
| CN112395079A (en) * | 2019-08-19 | 2021-02-23 | 无锡江南计算技术研究所 | Operation core operation migration method under heterogeneous many-core architecture |
| CN112559176A (en) * | 2020-12-11 | 2021-03-26 | 广州橙行智动汽车科技有限公司 | Instruction processing method and device |
| CN115658569A (en) * | 2022-12-08 | 2023-01-31 | 井芯微电子技术(天津)有限公司 | Method, system and equipment for interrupting and sharing storage among AMP (amplifier) multi-core processors |
| CN116244229A (en) * | 2023-05-12 | 2023-06-09 | 苏州浪潮智能科技有限公司 | Access method and device of hardware controller, storage medium and electronic equipment |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8296768B2 (en) * | 2007-06-30 | 2012-10-23 | Intel Corporation | Method and apparatus to enable runtime processor migration with operating system assistance |
| CN101201753B (en) * | 2007-12-13 | 2012-12-26 | 浪潮通信信息系统有限公司 | Method for configuring and managing multimode machine supervising engine |
| CN100562854C (en) * | 2008-03-11 | 2009-11-25 | 浙江大学 | Implementation method of multi-core processor operating system load balancing |
-
2009
- 2009-02-26 CN CN2009100959582A patent/CN101504618B/en not_active Expired - Fee Related
Cited By (39)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101751295B (en) * | 2009-12-22 | 2012-08-29 | 浙江大学 | Method for realizing inter-core thread migration under multi-core architecture |
| CN102495762A (en) * | 2011-11-16 | 2012-06-13 | 华为技术有限公司 | Thread scheduling method, thread scheduling device and multi-core processor system |
| CN102495762B (en) * | 2011-11-16 | 2014-04-02 | 华为技术有限公司 | Thread scheduling method, thread scheduling device and multi-core processor system |
| CN102981805A (en) * | 2012-11-02 | 2013-03-20 | 浪潮(北京)电子信息产业有限公司 | Serial software response method and system |
| CN102981805B (en) * | 2012-11-02 | 2015-11-18 | 浪潮(北京)电子信息产业有限公司 | The response method of serialized software and system |
| US9292450B2 (en) | 2013-03-05 | 2016-03-22 | Imagination Technologies Limited | Migration of data to register file cache |
| US10678695B2 (en) | 2013-03-05 | 2020-06-09 | MIPS Tech, LLC | Migration of data to register file cache |
| US9612968B2 (en) | 2013-03-05 | 2017-04-04 | Imagination Technologies Limited | Migration of data to register file cache |
| US9858194B2 (en) | 2013-03-05 | 2018-01-02 | Imagination Technologies | Migration of data to register file cache |
| CN105009086A (en) * | 2014-03-10 | 2015-10-28 | 华为技术有限公司 | Method for switching processors, computer, and switching apparatus |
| CN105009086B (en) * | 2014-03-10 | 2019-01-18 | 华为技术有限公司 | A kind of method, computer and switching device for realizing processor switching |
| CN105868016A (en) * | 2015-01-20 | 2016-08-17 | 复旦大学 | Thread transfer distribution method capable of preventing local overheat of multi-core processor |
| CN105868016B (en) * | 2015-01-20 | 2019-04-02 | 复旦大学 | A kind of thread transfer distribution method avoiding multi-core processor hot-spot |
| US12130744B2 (en) | 2015-06-10 | 2024-10-29 | Mobileye Vision Technologies Ltd. | Fine-grained multithreaded cores executing fused operations in multiple clock cycles |
| CN107980118B (en) * | 2015-06-10 | 2021-09-21 | 无比视视觉技术有限公司 | Multi-core processor device using multi-thread processing |
| CN107980118A (en) * | 2015-06-10 | 2018-05-01 | 无比视视觉技术有限公司 | Use the multi-nuclear processor equipment of multiple threads |
| US11294815B2 (en) | 2015-06-10 | 2022-04-05 | Mobileye Vision Technologies Ltd. | Multiple multithreaded processors with shared data cache |
| WO2017049592A1 (en) * | 2015-09-25 | 2017-03-30 | Intel Corporation | Method and apparatus to improve shared memory efficiency |
| US11068401B2 (en) | 2015-09-25 | 2021-07-20 | Intel Corporation | Method and apparatus to improve shared memory efficiency |
| US10922143B2 (en) | 2016-01-15 | 2021-02-16 | Intel Corporation | Systems, methods and devices for determining work placement on processor cores |
| US11409577B2 (en) | 2016-01-15 | 2022-08-09 | Intel Corporation | Systems, methods and devices for determining work placement on processor cores |
| CN106980492B (en) * | 2016-01-15 | 2019-07-26 | 英特尔公司 | For the device of calculating, system, method, machine readable storage medium and equipment |
| CN106980492A (en) * | 2016-01-15 | 2017-07-25 | 英特尔公司 | System, method and apparatus for determining the work arrangement on processor core |
| CN108885559A (en) * | 2016-03-29 | 2018-11-23 | 微软技术许可有限责任公司 | Fast transfer workload among multiple processors |
| CN108885559B (en) * | 2016-03-29 | 2021-12-03 | 微软技术许可有限责任公司 | Fast transfer of workload between multiple processors |
| CN105930218A (en) * | 2016-04-18 | 2016-09-07 | 深圳市万普拉斯科技有限公司 | Computing resource frequency adjustment method and system |
| CN106776018A (en) * | 2016-12-01 | 2017-05-31 | 三星（中国）半导体有限公司 | Host node for distributed system and method for parallel processing and equipment from node |
| CN108156207A (en) * | 2016-12-02 | 2018-06-12 | 航天星图科技（北京）有限公司 | A kind of data processing method of multi-node system |
| CN106850749A (en) * | 2016-12-26 | 2017-06-13 | 联想(北京)有限公司 | A kind of method and device, the electronic equipment of online updating kernel |
| CN109254849A (en) * | 2018-08-31 | 2019-01-22 | 北京小米移动软件有限公司 | The operation method and device of application program |
| CN109614220B (en) * | 2018-10-26 | 2020-06-30 | 阿里巴巴集团控股有限公司 | Multi-core system processor and data updating method |
| US11106795B2 (en) | 2018-10-26 | 2021-08-31 | Advanced New Technologies Co., Ltd. | Method and apparatus for updating shared data in a multi-core processor environment |
| CN109614220A (en) * | 2018-10-26 | 2019-04-12 | 阿里巴巴集团控股有限公司 | A kind of multiple nucleus system processor and data-updating method |
| CN112395079A (en) * | 2019-08-19 | 2021-02-23 | 无锡江南计算技术研究所 | Operation core operation migration method under heterogeneous many-core architecture |
| CN111338577A (en) * | 2020-02-21 | 2020-06-26 | 苏州浪潮智能科技有限公司 | Multi-core thread migration method and system of storage system and related components |
| CN112559176A (en) * | 2020-12-11 | 2021-03-26 | 广州橙行智动汽车科技有限公司 | Instruction processing method and device |
| CN115658569A (en) * | 2022-12-08 | 2023-01-31 | 井芯微电子技术(天津)有限公司 | Method, system and equipment for interrupting and sharing storage among AMP (amplifier) multi-core processors |
| CN116244229A (en) * | 2023-05-12 | 2023-06-09 | 苏州浪潮智能科技有限公司 | Access method and device of hardware controller, storage medium and electronic equipment |
| CN116244229B (en) * | 2023-05-12 | 2023-08-04 | 苏州浪潮智能科技有限公司 | Access method and device of hardware controller, storage medium and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101504618B (en) | 2011-04-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101504618A (en) | Multi-core processor oriented real-time thread migration method | |
| TWI742032B (en) | Methods, apparatus, and instructions for user-level thread suspension | |
| EP3844620B1 (en) | Method, apparatus, and system for an architecture for machine learning acceleration | |
| JP7052170B2 (en) | Processor and system | |
| CN101788919B (en) | Chip multi-core processor clock precision parallel simulation system and simulation method thereof | |
| Ahn et al. | McSimA+: A manycore simulator with application-level+ simulation and detailed microarchitecture modeling | |
| CN103150264B (en) | Extension Cache Coherence protocol-based multi-level consistency simulation domain verification and test method | |
| JP6525286B2 (en) | Processor core and processor system | |
| US8661449B2 (en) | Transactional computation on clusters | |
| CN104835110B (en) | A kind of asynchronous diagram data processing system based on GPU | |
| CN101799750B (en) | Data processing method and device | |
| US10089259B2 (en) | Precise, efficient, and transparent transfer of execution between an auto-generated in-line accelerator and processor(s) | |
| DE102014003671A1 (en) | PROCESSORS, METHODS AND SYSTEMS FOR RELAXING THE SYNCHRONIZATION OF ACCESS TO A SHARED MEMORY | |
| CN104081315A (en) | Method, apparatus and system for energy efficiency and energy conservation including thread consolidation | |
| CN104412233B (en) | The distribution of aliasing register in pipeline schedule | |
| CN110647404A (en) | System, apparatus and method for barrier synchronization in a multithreaded processor | |
| CN107667358A (en) | For the coherent structure interconnection used in multiple topological structures | |
| TW201435734A (en) | System and method for hardware scheduling of conditional barriers and impatient barriers | |
| TW201342030A (en) | Instruction that specifies an application thread performance state | |
| US9733689B2 (en) | Hardware apparatuses and methods to perform transactional power management | |
| CN112580792B (en) | Neural network multi-core tensor processor | |
| Abellán et al. | Efficient hardware barrier synchronization in many-core cmps | |
| KR102279200B1 (en) | Floating-point supportive pipeline for emulated shared memory architectures | |
| Malhotra et al. | ParTejas: A parallel simulator for multicore processors | |
| KR20160010580A (en) | Memory unit for emulated shared memory architectures |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110427 Termination date: 20120226 |