CN108847264A - Word line voltage controller and control circuit - Google Patents
Word line voltage controller and control circuit Download PDFInfo
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- CN108847264A CN108847264A CN201810536870.9A CN201810536870A CN108847264A CN 108847264 A CN108847264 A CN 108847264A CN 201810536870 A CN201810536870 A CN 201810536870A CN 108847264 A CN108847264 A CN 108847264A
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/418—Address circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
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- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
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Abstract
The present invention relates to a kind of word line voltage controllers, are related to semiconductor integrated circuit, including：One control circuit, the control circuit connect a voltage source, to detect the voltage of the voltage source, and receive a clock signal clk, and one control signal of output, the control signal includes the first level and second electrical level；An and booster converter, connect the control circuit, to receive the control signal of the control circuit output, wherein the control signal of the first level controls the booster converter work to charge to the voltage source, the control signal of second electrical level controls the booster converter and does not charge to the voltage source, to improve the reliability of static random access memory.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit more particularly to a kind of word line voltages of static random access memory
Controller.
Background technique
In semiconductor integrated circuit, static random access memory (Static Random-Access Memory,
SRAM it) is widely used on the chip (system on a chip, SoC) and the cache of processor of integrated circuit.Please
Refering to fig. 1, Fig. 1 is the exemplary circuit configuration schematic diagram of static random access memory.As shown in Figure 1, static random-access is deposited
The phase inverter and transistor M5, M6 that phase inverter that reservoir is made of M1, M2, M3, M4 are formed form, and M1, M2, M3 and M4 are constituted
Latch is completed " reading " to static random access memory by control wordline WL and bit line BL and bit line BLB and " is write
Enter " work.
However, any device in static random access memory (Static Random-Access Memory, SRAM)
The bad equal minimum voltage Vmin that can reduce static random access memory, and then reduce static random access memory " reading "
The ability of " write-in ".
Summary of the invention
The purpose of the present invention is to provide a kind of word line voltage controllers, to improve static random-access in a low voltage state
The control ability of memory improves the minimum voltage Vmin of static random access memory；Will not make in high pressure it is static with
The gate dielectric compression that machine accesses transistor M5, M6 in memory is excessively high, and improves its reliability.
Word line voltage controller provided by the invention, including：One control circuit, the control circuit connect a voltage source,
To detect the voltage of the voltage source, and a clock signal clk is received, one control signal of output, the control signal includes the
One level and second electrical level；And a booster converter, the control circuit is connected, to receive the institute of the control circuit output
Control signal is stated, is worked wherein the control signal of the first level controls the booster converter to be filled to the voltage source
Electricity, the control signal of second electrical level control the booster converter and do not charge to the voltage source.
Further, when clock signal clk is low level, shown control signal controls shown booster converter not to institute
Show voltage source charging or charge to the voltage source, when clock signal clk is high level, shown control signal keeps previous moment
Clock signal clk be low level when control signal state.
Further, shown control circuit further include a voltage detecting circuit, a feedback circuit, one first phase inverter,
The input terminal of one second phase inverter, a third phase inverter and one the 4th phase inverter, first phase inverter receives clock signal
CLK, the output end of first phase inverter connect the voltage detecting circuit and the feedback circuit, output one first state letter
Number, the voltage detecting circuit includes a switching tube and resistance element bleeder circuit in series, the resistance element
First end connects the voltage source, and the second end of the resistance element connects the first end of the switching tube, the switching tube
Second end ground connection, the control terminal of the switching tube connect the output end of first phase inverter to receive the first state letter
Number, and the tie point of the switching tube and the resistance element constitutes the output end of the voltage detecting circuit to export a reaction
The detectable voltage signals of voltage source voltage, the feedback circuit include the first CMOS tube CMOS1 and the second CMOS tube CMOS2, the
The first end and second end of the first PMOS tube in one CMOS tube CMOS1 is separately connected the first end and second of the first NMOS tube
End, to constitute the input terminal and output end of the first CMOS tube CMOS1, the input terminal of the first CMOS tube CMOS1 connects the voltage
The output end of detection circuit, to receive the detectable voltage signals, the control terminal of first PMOS tube receives clock signal
CLK, the control terminal of first NMOS tube connect the output end of first phase inverter, to receive the first state signal,
The first end and second end of the second PMOS tube in the second CMOS tube CMOS2 be separately connected the second NMOS tube first end and
Second end, with constitute the second CMOS tube CMOS2 input terminal and output end, the second CMOS tube CMOS2 input terminal connection described in
The control terminal of the output end of second phase inverter, second NMOS tube receives clock signal clk, the control of second PMOS tube
End connects the output end of first phase inverter, to receive the first state signal, the output of the first CMOS tube CMOS1
End connects the output end of the second CMOS tube CMOS2, and connects the input terminal of the third phase inverter, the third phase inverter
Output end connect the input terminal of second phase inverter and the input terminal of the 4th phase inverter, and the 4th phase inverter
Output end connects the booster converter, to export the control signal.
Further, when clock signal clk is low level, if the detectable voltage signals are less than the third phase inverter
Threshold voltage, the control signal is low level, when clock signal clk is high level, when control signal holding is previous
Carve the state of control signal when clock signal clk is low level；If it is anti-that the detectable voltage signals are greater than the third
The threshold voltage of phase device, the control signal is high level, when clock signal clk is high level, before the control signal is kept
The state of control signal when one moment clock signal clk is low level.
Further, the control circuit includes a voltage detecting circuit, and the voltage detecting circuit includes a switch
Guan Yuyi resistance element bleeder circuit in series, the first end of the resistance element connects the voltage source, described resistive
The second end of element connects the first end of the switching tube, the second end ground connection of the switching tube, the control terminal of the switching tube
The output end of one first phase inverter is connected, the input terminal of first phase inverter receives clock signal clk, the switching tube and institute
The tie point for stating resistance element constitutes the output end of the voltage detecting circuit to export the detection of response voltage source voltage electricity
Signal is pressed, wherein the switching tube is NMOS tube.
Further, the resistance element is a resistance.
Further, the resistance element is a switching tube.
Further, the resistance element also passes through another resistance element and connect with the switching tube.
The present invention also provides a kind of control circuits, including：One voltage detecting circuit, a feedback circuit, one first phase inverter,
The input terminal of one second phase inverter, a third phase inverter and one the 4th phase inverter, first phase inverter receives clock signal
CLK, the output end of first phase inverter connect the voltage detecting circuit and the feedback circuit, output one first state letter
Number, the voltage detecting circuit includes a switching tube and resistance element bleeder circuit in series, the resistance element
First end connects the voltage source, and the second end of the resistance element connects the first end of the switching tube, the switching tube
Second end ground connection, the control terminal of the switching tube connect the output end of first phase inverter to receive the first state letter
Number, and the tie point of the switching tube and the resistance element constitutes the output end of the voltage detecting circuit to export a reaction
The detectable voltage signals of voltage source voltage, the feedback circuit include the first CMOS tube CMOS1 and the second CMOS tube CMOS2, the
The first end and second end of the first PMOS tube in one CMOS tube CMOS1 is separately connected the first end and second of the first NMOS tube
End, to constitute the input terminal and output end of the first CMOS tube CMOS1, the input terminal of the first CMOS tube CMOS1 connects the voltage
The output end of detection circuit, to receive the detectable voltage signals, the control terminal of first PMOS tube receives clock signal
CLK, the control terminal of first NMOS tube connect the output end of first phase inverter, to receive the first state signal,
The first end and second end of the second PMOS tube in the second CMOS tube CMOS2 be separately connected the second NMOS tube first end and
Second end, with constitute the second CMOS tube CMOS2 input terminal and output end, the second CMOS tube CMOS2 input terminal connection described in
The control terminal of the output end of second phase inverter, second NMOS tube receives clock signal clk, the control of second PMOS tube
End connects the output end of first phase inverter, to receive the first state signal, the output of the first CMOS tube CMOS1
End connects the output end of the second CMOS tube CMOS2, and connects the input terminal of the third phase inverter, the third phase inverter
Output end connect the input terminal of second phase inverter and the input terminal of the 4th phase inverter, the 4th phase inverter it is defeated
One control signal of outlet output, the control signal includes the first level and second electrical level.
Further, when clock signal clk is low level, if the detectable voltage signals are less than the third phase inverter
Threshold voltage, the control signal is low level, when clock signal clk is high level, when control signal holding is previous
Carve the state of control signal when clock signal clk is low level；If it is anti-that the detectable voltage signals are greater than the third
The threshold voltage of phase device, the control signal is high level, when clock signal clk is high level, before the control signal is kept
The state of control signal when one moment clock signal clk is low level.
Word line voltage controller provided by the invention, static random access memory start " to read " or " write-in " it is dynamic
Before work, the voltage on detection wordline WL first charges to it if the voltage on wordline WL is lower, this improves
The control ability of static random access memory under low-pressure state, improves the minimum voltage of static random access memory
Vmin；If the voltage on wordline WL is higher, do not charge to wordline WL, therefore, when high pressure will not be such that static random-access deposits
The gate dielectric compression of transistor M5, M6 in reservoir are excessively high, and improve its reliability.
Detailed description of the invention
Fig. 1 is the exemplary circuit configuration schematic diagram of static random access memory.
Fig. 2 is the structural schematic diagram of the word line voltage controller of one embodiment of the invention.
Fig. 3 is the working waveform figure of the control circuit shown in Fig. 2 of one embodiment of the invention.
Fig. 4 is the schematic diagram of the bleeder circuit of one embodiment of the invention.
The reference numerals are as follows for main element in figure：
110, control circuit；120, booster converter；114, voltage detecting circuit；116, feedback circuit.
Specific embodiment
Below in conjunction with attached drawing, clear, complete description is carried out to the technical solution in the present invention, it is clear that described
Embodiment is a part of the embodiments of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is general
Logical technical staff's all other embodiment obtained under the premise of not making creative work belongs to what the present invention protected
Range.
In an embodiment of the present invention, a kind of word line voltage controller is provided.Specifically, referring to Fig. 2, Fig. 2 is this hair
The structural schematic diagram of the word line voltage controller of a bright embodiment.As shown in Fig. 2, the word line voltage controller includes control circuit
110 and booster converter 120, control circuit 110 connects a voltage source Vcc, and (voltage of voltage source Vcc is deposited with static random-access
The voltage of wordline WL is identical in reservoir, therefore can represent the voltage of wordline WL in static random access memory), to detect voltage
The voltage of source Vcc, and a clock signal clk is received, one control signal Cs of output, control signal Cs includes the first level and second
Level；Booster converter 120 connects control circuit 110, receives the control signal Cs that control circuit 110 exports, wherein the first electricity
The flat control signal Cs control work of booster converter 120 is to charge to voltage source Vcc (namely wordline WL), the control of second electrical level
Signal Cs control booster converter 120 processed does not charge to voltage source Vcc (namely wordline WL).
Specifically, as shown in Fig. 2, control circuit 110 includes voltage detecting circuit 114, feedback circuit 116, the first reverse phase
Device INV1, the second phase inverter INV2, third phase inverter INV3 and the 4th phase inverter INV4.The input of first phase inverter INV1 terminates
Receive clock signal clk, the output end connection voltage detecting circuit 114 and feedback circuit 116 of the first phase inverter INV1, output 1 the
One status signal D1.Voltage detecting circuit 114 includes switching tube S1 and bleeder circuit resistance element R1 in series, resistive member
The first end of part R1 connects voltage source Vcc, the first end of the second end connection switch pipe S1 of resistance element R1, and the of switching tube S1
Two ends ground connection, the control terminal of switching tube S1 connects the output end of the first phase inverter INV1 to receive first state signal D1, and opens
The tie point for closing pipe S1 and resistance element R1 constitutes the output end of voltage detecting circuit 114, and the of resistance element R1 as shown in Figure 2
Two ends are the output end of voltage detecting circuit 114, to export the detectable voltage signals Tv1 of a response voltage source Vcc voltage.Feedback
Circuit 116 includes the of the first CMOS tube CMOS1 and the first PMOS tube in the second CMOS tube CMOS2, the first CMOS tube CMOS1
One end and second end are separately connected the first end and second end of the first NMOS tube, to constitute the input terminal of the first CMOS tube CMOS1
And output end, the output end of the input terminal connection voltage detecting circuit 114 of the first CMOS tube CMOS1, to receive detection voltage letter
Number Tv1, the control terminal of the first PMOS tube receive clock signal clk, and the control terminal of the first NMOS tube connects the first phase inverter INV1
Output end, to receive first state signal D1；The first end and second end of the second PMOS tube in second CMOS tube CMOS2 point
Do not connect the first end and second end of the second NMOS tube, with constitute the second CMOS tube CMOS2 input terminal and output end, second
The input terminal of CMOS tube CMOS2 connects the output end of the second phase inverter, and the control terminal of the second NMOS tube receives clock signal clk,
The control terminal of second PMOS tube connects the output end of the first phase inverter INV1, to receive first state signal D1, the first CMOS tube
The output end of CMOS1 connects the output end of the second CMOS tube CMOS2, and connects the input terminal of third phase inverter INV3, and third is anti-
The output end of phase device INV3 connects the input terminal of the second phase inverter INV2 and the input terminal of the 4th phase inverter INV4, and the 4th reverse phase
The output end output of device INV4 controls signal Cs to booster converter 120.
In an embodiment of the present invention, switching tube S1 is a NMOS tube.In an embodiment of the present invention, resistance element R1 is
One resistance.In an embodiment of the present invention, voltage detecting circuit 114 further includes a PMOS tube, and PMOS tube is connected on resistance element
Between R1 and switching tube S1, the first end of the control terminal connection switch pipe S1 of PMOS tube, the second of resistance element R1 as shown in Figure 2
End is the output end of voltage detecting circuit 114.
In an embodiment of the present invention, the control signal Cs of the first level is high level, the control signal Cs of second electrical level
For low level.
Specifically, referring to Fig. 3, Fig. 3 is the working waveform figure of the control circuit shown in Fig. 2 of one embodiment of the invention.
Assuming that the input terminal of third phase inverter INV3 is the second status signal D2, the output end of third phase inverter INV3 is third state letter
The threshold voltage of number D3, third phase inverter INV3 are Vtrip.As shown in figure 3, the t0 moment, when clock signal clk is low level,
Static random access memory off position, the high level of the first state signal D1 after the first phase inverter INV1 reverse phase,
Then switching tube S1 is connected, PMOS tube conducting, and to detect the voltage in voltage source Vcc, output represents the work of voltage detecting circuit 114
The detectable voltage signals Tv1 of the voltage of voltage source Vcc, and the control terminal of the first PMOS tube receives low level clock signal clk
And it is connected or the control terminal of the first NMOS tube receives the first state signal D1 of high level and is connected namely the first CMOS tube
CMOS1 conducting, then the output end of third phase inverter INV3 receives detectable voltage signals Tv1, then the second status signal D2 is equal to inspection
Voltage signal Tv1 is surveyed, if detectable voltage signals Tv1 is greater than the threshold voltage Vtrip of third phase inverter INV3, third phase inverter
INV3 reversion, the low level 0 of the third state signal D3 of the output end output of third phase inverter INV3, then through the 4th phase inverter
The control signal Cs exported after INV4 is high level, namely control booster converter 120 works, to voltage source Vcc (namely wordline
WL it) charges.Meanwhile second PMOS tube control terminal receive high level first state signal D1, the control terminal of the second NMOS tube
It receives low level clock signal clk and turns off namely the second CMOS tube CMOS2 is not turned on, then third phase inverter INV3 is inputted
The second status signal D2 at end remains detectable voltage signals Tv1, and control signal Cs remains high level, namely control boosting becomes
Parallel operation 120 works, and charges to voltage source Vcc.If selector makes, resistance R1=1 Ω, equivalent impedance Rp when PMOS tube is connected
When=0.8 Ω, voltage source Vcc=0.8V, equivalent impedance Rs1=0.3 Ω when switching tube S1 is connected, then detectable voltage signals
Tv1=0.419V, Vtrip=Vcc/2=0.4V (voltage of the voltage source of third phase inverter INV3 and the voltage of voltage source Vcc
It is identical), i.e. Tv1>Vtrip, detectable voltage signals Tv1 are greater than the threshold voltage Vtrip of third phase inverter INV3, control signal Cs
It works for high level, namely control booster converter 120, charges to voltage source Vcc.To the t1 moment, clock signal clk becomes high
Level, then first state signal D1 becomes low level, and switching tube S1 shutdown, voltage detecting circuit 114 stops working, and first
CMOS tube CMOS1 shutdown, the control terminal of the second PMOS tube receive low level first state signal D1, and the first of the second PMOS tube
End receives 1 signal of high level that the second phase inverter INV2 is exported, and (third state signal D3 of low level 0 is through the second phase inverter INV2
Obtain afterwards) and be connected, then the input terminal of the output of high level 1 that the second phase inverter INV2 is exported to third phase inverter INV3, then
Second status signal D2 is high level 1, then third state signal D3 is low level 0, in this way, third state signal D3 is anti-through second
The circuit that phase device INV2, the second CMOS tube CMOS2 and third phase inverter INV3 are constituted remains low level 1, then controls signal Cs
It remains high level (namely state of the control signal Cs when clock signal clk of previous moment being kept to be low level), namely
It controls booster converter 120 to work, charge to voltage source Vcc, and when clock signal clk becomes high level, wordline WL becomes
High level, then static random access memory can work in the state of " reading " or " write-in ".Namely clock signal clk is high electricity
Usually, the state (high level) of control signal Cs when control signal Cs keeps the clock signal clk of previous moment to be low level.
When clock signal clk is low level, such as the t2 moment, the second status signal D2 is equal to detectable voltage signals Tv1, if inspection
Survey the threshold voltage Vtrip that voltage signal Tv1 is less than third phase inverter INV3, the of the output end output of third phase inverter INV3
The high level 1 of tri-state signal D3, then the control signal Cs exported after the 4th phase inverter INV4 are low level, namely control rises
Buckling parallel operation 120 does not work, and does not charge to voltage source Vcc.The second CMOS tube CMOS2 is not turned on simultaneously, then third phase inverter
Second status signal D2 of INV3 input terminal remains detectable voltage signals Tv1, and control signal Cs remains low level, namely control
Booster converter 120 processed does not charge to voltage source Vcc.Such as, resistance R1=1 Ω, equivalent impedance Rp=0.8 when PMOS tube is connected
Equivalent impedance Rs1=0.1 Ω, then detectable voltage signals Tv1=when Ω, voltage source Vcc=1V, when switching tube S1 is connected
0.474V, Vtrip=Vcc/2=0.5V, i.e. Tv1<Vtrip, detectable voltage signals Tv1 are less than the threshold of third phase inverter INV3
Voltage Vtrip, control signal Cs are low level, namely control booster converter 120 does not work, and does not charge to voltage source Vcc.It arrives
T3 moment, clock signal clk become high level, then first state signal D1 becomes low level, switching tube S1 shutdown, voltage inspection
Slowdown monitoring circuit 114 stops working, and the first CMOS tube CMOS1 is turned off, and the control terminal of the second NMOS tube receives the clock letter of high level
Number CLK, the first end of the second NMOS tube receive the low level 0 signal (third state of high level 1 of the second phase inverter INV2 output
Signal D3 is obtained after the second phase inverter INV2) and be connected, the third state signal D3 of high level 1 is through the second phase inverter INV2
After become low level 0, and export to the input terminal of third phase inverter INV3, then the second status signal D2 is low level 0, then third
Status signal D3 is high level 1, and such third state signal D3 is through the second phase inverter INV2, the second CMOS tube CMOS2 and third
The circuit that phase inverter INV3 is constituted remains high level 1, then controls signal Cs and remain low level, namely control booster converter
120 do not charge to voltage source Vcc, and when clock signal clk becomes high level, wordline WL becomes high level, then static random
Access memory can work in the state of " reading " or " write-in ".Namely clock signal clk be high level when, control signal Cs protect
The state (low level) of control signal Cs when the clock signal clk for holding previous moment is low level.
That is, control signal Cs is high level or low level when clock signal clk is low level, clock signal clk is height
When level, the state of control signal Cs when control signal Cs keeps the clock signal clk of previous moment to be low level.Such as Fig. 3
It is shown, when clock signal clk is low level, if detectable voltage signals Tv1 is less than the threshold voltage of third phase inverter INV3
Vtrip, control signal Cs are low level, and when clock signal clk is high level, it is low that control signal Cs, which keeps clock signal clk,
The state of control signal Cs when level (Cs is low level)；If detectable voltage signals Tv1 is greater than the door of third phase inverter INV3
Sill voltage Vtrip, control signal Cs are high level, and when clock signal clk is high level, control signal Cs keeps clock signal
The state of control signal Cs when CLK is low level (Cs is high level).
In this way, static random access memory start " to read " or the movement of " write-in " before, detection wordline WL first
On voltage charge if the voltage on wordline WL is lower to it, this improves static randoms under low-pressure state to deposit
The control ability of access to memory improves the minimum voltage Vmin of static random access memory；If voltage on wordline WL compared with
Height does not charge to wordline WL then, and therefore, when high pressure will not make the lock of transistor M5, M6 in static random access memory
Dielectric compression in pole is excessively high, and improves its reliability.
Certainly, the present invention does not limit the specific structure of control circuit 110.Referring to Fig. 4, Fig. 4 is that the present invention one is implemented
The schematic diagram of the bleeder circuit of example.It is a resistance relative to the resistance element R1 in Fig. 2.As shown in figure 4, resistance element R1 is one
Switching tube.Another resistance element R1 can also be connect by another resistance element with switching tube S1, as shown in Fig. 2, resistance element R1 is logical
A PMOS tube is crossed to connect with switching tube S1；As shown in figure 4, resistance element R1 is connect by a resistance with switching tube S1.
Booster converter 120 can be the booster converter (such as Flyback converter) or non-isolated boosting inverter of isolation
Device (such as boost converter).
In an embodiment of the present invention, it also provides just like control circuit shown in Fig. 2, is opened in static random access memory
Begin to detect the voltage of voltage source Vcc (namely wordline WL) first, and export control signal before the movement of " reading " or " write-in "
Cs so improves the reliability of static random access memory to control the voltage on voltage source Vcc (namely wordline WL).
In conclusion static random access memory start " to read " or the movement of " write-in " before, detection electricity first
Voltage on potential source Vcc (namely wordline WL) charges to it if the voltage on wordline WL is lower, and this improves low
The control ability of static random access memory under pressure condition improves the minimum voltage Vmin of static random access memory；
If the voltage in voltage source Vcc (namely wordline WL) is higher, do not charge to voltage source Vcc (namely wordline WL), therefore, high pressure
When that the gate dielectric of transistor M5, M6 in static random access memory will not be made to be pressurized is excessively high, and it is reliable to improve it
Property.
Finally it should be noted that：The above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Present invention has been described in detail with reference to the aforementioned embodiments for pipe, those skilled in the art should understand that：Its according to
So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into
Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (10)
1. a kind of word line voltage controller, which is characterized in that including：
One control circuit, the control circuit connect a voltage source, to detect the voltage of the voltage source, and receive clock letter
Number CLK, one control signal of output, the control signal includes the first level and second electrical level；And
One booster converter connects the control circuit, to receive the control signal of the control circuit output, wherein the
The control signal of one level controls the booster converter work to voltage source charging, the control of second electrical level
Signal processed controls the booster converter and does not charge to the voltage source.
2. word line voltage controller according to claim 1, which is characterized in that shown when clock signal clk is low level
It controls signal and controls shown booster converter not to the charging of shown voltage source or to voltage source charging, clock signal clk is
When high level, the state of control signal when shown control signal keeps the clock signal clk of previous moment to be low level.
3. word line voltage controller according to claim 1, which is characterized in that shown control circuit further includes voltage inspection
Slowdown monitoring circuit, a feedback circuit, one first phase inverter, one second phase inverter, a third phase inverter and one the 4th phase inverter, described
The input terminal of one phase inverter receives clock signal clk, the output end of first phase inverter connect the voltage detecting circuit and
The feedback circuit, exports a first state signal, and the voltage detecting circuit includes that a switching tube is connected with a resistance element
The bleeder circuit of composition, the first end of the resistance element connect the voltage source, and the second end of the resistance element connects institute
The first end of switching tube, the second end ground connection of the switching tube are stated, the control terminal of the switching tube connects first phase inverter
Output end to receive the first state signal, and the tie point of the switching tube and the resistance element constitutes the voltage
For the output end of detection circuit to export the detectable voltage signals of a response voltage source voltage, the feedback circuit includes the first CMOS
The first end and second end of pipe CMOS1 and the first PMOS tube in the second CMOS tube CMOS2, the first CMOS tube CMOS1 connects respectively
The first end and second end of the first NMOS tube is connect, to constitute the input terminal and output end of the first CMOS tube CMOS1, the first CMOS tube
The input terminal of CMOS1 connects the output end of the voltage detecting circuit, to receive the detectable voltage signals, the first PMOS
The control terminal of pipe receives clock signal clk, and the control terminal of first NMOS tube connects the output end of first phase inverter, with
The first state signal is received, the first end and second end of the second PMOS tube in the second CMOS tube CMOS2 connects respectively
The first end and second end of the second NMOS tube is connect, to constitute the input terminal and output end of the second CMOS tube CMOS2, the second CMOS tube
The input terminal of CMOS2 connects the output end of second phase inverter, and the control terminal of second NMOS tube receives clock signal
CLK, the control terminal of second PMOS tube connect the output end of first phase inverter, to receive the first state signal,
The output end of the first CMOS tube CMOS1 connects the output end of the second CMOS tube CMOS2, and connects the third reverse phase
The input terminal of device, the output end of the third phase inverter connect the input terminal and the 4th phase inverter of second phase inverter
Input terminal, and the output end of the 4th phase inverter connects the booster converter, to export the control signal.
4. word line voltage controller according to claim 3, which is characterized in that when clock signal clk is low level, if institute
The threshold voltage that detectable voltage signals are less than the third phase inverter is stated, the control signal is low level, and clock signal clk is
When high level, the state of the control signal when control signal holding previous moment clock signal clk is low level；If
The detectable voltage signals are greater than the threshold voltage of the third phase inverter, and the control signal is high level, clock signal clk
When for high level, the state for the control signal that the control signal keeps previous moment clock signal clk when being low level.
5. word line voltage controller according to claim 1, which is characterized in that the control circuit includes a voltage detecting
Circuit, the voltage detecting circuit include a switching tube and resistance element bleeder circuit in series, the resistance element
First end connect the voltage source, the second end of the resistance element connects the first end of the switching tube, the switching tube
Second end ground connection, the control terminal of the switching tube connects the output end of one first phase inverter, the input of first phase inverter
The tie point of end reception clock signal clk, the switching tube and the resistance element constitutes the output of the voltage detecting circuit
It holds to export the detectable voltage signals of a response voltage source voltage, wherein the switching tube is NMOS tube.
6. word line voltage controller according to claim 5, which is characterized in that the resistance element is a resistance.
7. word line voltage controller according to claim 5, which is characterized in that the resistance element is a switching tube.
8. according to the described in any item word line voltage controllers of claim 5-7, which is characterized in that the resistance element also passes through
Another resistance element is connect with the switching tube.
9. a kind of control circuit, which is characterized in that including：One voltage detecting circuit, a feedback circuit, one first phase inverter, one
The input terminal of second phase inverter, a third phase inverter and one the 4th phase inverter, first phase inverter receives clock signal clk,
The output end of first phase inverter connects the voltage detecting circuit and the feedback circuit, exports a first state signal,
The voltage detecting circuit includes a switching tube and resistance element bleeder circuit in series, and the first of the resistance element
End connects the voltage source, and the second end of the resistance element connects the first end of the switching tube, and the second of the switching tube
End ground connection, the control terminal of the switching tube connect the output end of first phase inverter to receive the first state signal, and
The tie point of the switching tube and the resistance element constitutes the output end of the voltage detecting circuit to export a response voltage
The detectable voltage signals of source voltage, the feedback circuit include the first CMOS tube CMOS1 and the second CMOS tube CMOS2, and first
The first end and second end of the first PMOS tube in CMOS tube CMOS1 is separately connected the first end and second end of the first NMOS tube,
To constitute the input terminal and output end of the first CMOS tube CMOS1, the input terminal of the first CMOS tube CMOS1 connects the voltage detecting
The output end of circuit, to receive the detectable voltage signals, the control terminal of first PMOS tube receives clock signal clk, institute
The control terminal for stating the first NMOS tube connects the output end of first phase inverter, to receive the first state signal, described
The first end and second end of the second PMOS tube in two CMOS tube CMOS2 is separately connected the first end and second of the second NMOS tube
End, to constitute the input terminal and output end of the second CMOS tube CMOS2, the input terminal connection described second of the second CMOS tube CMOS2
The output end of phase inverter, the control terminal of second NMOS tube receive clock signal clk, and the control terminal of second PMOS tube connects
The output end of first phase inverter is connect, to receive the first state signal, the output end of the first CMOS tube CMOS1 connects
Connect the output end of the second CMOS tube CMOS2, and connect the input terminal of the third phase inverter, the third phase inverter it is defeated
Outlet connects the input terminal of second phase inverter and the input terminal of the 4th phase inverter, the output end of the 4th phase inverter
One control signal of output, the control signal includes the first level and second electrical level.
10. control circuit according to claim 9, which is characterized in that when clock signal clk is low level, if the inspection
The threshold voltage that voltage signal is less than the third phase inverter is surveyed, the control signal is low level, and clock signal clk is high electricity
Usually, the state of the control signal when control signal holding previous moment clock signal clk is low level；If described
Detectable voltage signals are greater than the threshold voltage of the third phase inverter, and the control signal is high level, and clock signal clk is height
When level, the state of the control signal when control signal holding previous moment clock signal clk is low level.
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Application publication date: 20181120 |