CN108831379A - Pixel circuit and display panel - Google Patents

Abstract

A pixel circuit includes a driving transistor, a first switch, a storage capacitor, and a light emitting unit. The driving transistor has a first terminal for receiving a system high voltage, a second terminal coupled to the first node, and a control terminal coupled to the second node. The first switch has a first terminal coupled to the first node, a second terminal coupled to the third node, and a control terminal for receiving a first control signal. The first terminal of the storage capacitor is coupled to the second node and is used for receiving the data voltage, and the second terminal is directly coupled to the third node and is used for receiving the reference voltage. The anode terminal of the light emitting unit is coupled to the third node, and the cathode terminal is used for receiving a system low voltage. A display panel is also provided.

Description

Pixel circuits and display panels

technical field

The disclosure document relates to a pixel circuit and a display panel, and in particular to a pixel circuit and a display panel that use a feedback method to compensate a critical voltage.

Background technique

Low temperature poly-silicon thin-film transistor (low temperature poly-silicon thin-film transistor) has the characteristics of high carrier mobility and small size, and is suitable for display panels with high resolution, narrow frame and low power consumption. Excimer laser annealing (excimer laser annealing) technology is widely used in the industry at present to form polysilicon thin films of low temperature polysilicon thin film transistors. However, since the scanning power of each shot of the excimer laser is not stable, the polysilicon film in different regions will have differences in grain size and quantity. Therefore, in different regions of the display panel, the characteristics of the LTPS TFTs will be different. For example, low-temperature polysilicon thin film transistors in different regions have different threshold voltages, and this phenomenon is called threshold voltage variation.

The conventional pixel circuit detects and compensates the threshold voltage variation of its drive transistor through the circuit operation before emitting light. However, this compensation method requires a complex circuit structure and a large number of control signals, and additional operation stages are required to generate the compensation voltage. Therefore, the traditional pixel circuit cannot meet many requirements such as narrow bezel, high resolution and high PPI (pixels per inch) of today's displays.

In view of this, how to provide a simple pixel circuit that can be operated with a small number of control signals and does not require additional operation stages is a problem to be solved in the industry.

Contents of the invention

The disclosed document provides a pixel circuit. The pixel circuit includes a driving transistor, a first switch, a storage capacitor and a light emitting unit. The drive transistor includes a first terminal, a second terminal and a control terminal, wherein the first terminal of the drive transistor is used to receive the system high voltage, the second terminal of the drive transistor is coupled to the first node, and the control terminal of the drive transistor is coupled to the second node. Two nodes. The first switch includes a first terminal, a second terminal and a control terminal, wherein the first terminal of the first switch is coupled to the first node, the second terminal of the first switch is coupled to the third node, and the control terminal of the first switch Used to receive the first control signal. The storage capacitor includes a first end and a second end, wherein the first end of the storage capacitor is coupled to the second node for receiving the data voltage, and the second end of the storage capacitor is directly coupled to the third node for receiving reference voltage. The light emitting unit includes an anode terminal and a cathode terminal, wherein the anode terminal is coupled to the third node, and the cathode terminal is used for receiving the low voltage of the system.

The disclosure document further provides a display panel. The display panel includes a gate driving circuit, a source driving circuit and a plurality of pixel circuits. The gate driving circuit is used for providing the first control signal. The source driving circuit is used to provide data voltage. A plurality of pixel circuits are coupled to the gate driving circuit and the source driving circuit. Each pixel circuit includes a driving transistor, a first switch, a storage capacitor and a light emitting unit. The drive transistor includes a first terminal, a second terminal and a control terminal, wherein the first terminal of the drive transistor is used to receive the system high voltage, the second terminal of the drive transistor is coupled to the first node, and the control terminal of the drive transistor is coupled to the second node. Two nodes. The first switch includes a first terminal, a second terminal and a control terminal, wherein the first terminal of the first switch is coupled to the first node, the second terminal of the first switch is coupled to the third node, and the control terminal of the first switch Used to receive the first control signal. The storage capacitor includes a first end and a second end, wherein the first end of the storage capacitor is coupled to the second node for receiving the data voltage, and the second end of the storage capacitor is directly coupled to the third node for receiving reference voltage. The light emitting unit includes an anode terminal and a cathode terminal, wherein the anode terminal is coupled to the third node, and the cathode terminal is used for receiving the low voltage of the system.

The above-mentioned pixel circuit and display panel have the advantages of simple structure, fewer operating signals, fewer operating stages, and the like.

Description of drawings

In order to make the above and other purposes, features, advantages and embodiments of the disclosed document more obvious and understandable, the description of the accompanying drawings is as follows:

FIG. 1 is a simplified functional block diagram of a display panel according to an embodiment of the disclosure.

FIG. 2 is a schematic circuit diagram of the pixel circuit in FIG. 1 according to an embodiment of the disclosure.

FIG. 3 is an operation timing diagram of the pixel circuit in FIG. 1 according to an embodiment of the disclosure.

FIG. 4 is a driving schematic diagram of an equivalent circuit of the pixel circuit in FIG. 1 in a writing phase.

FIG. 5 is a driving schematic diagram of an equivalent circuit of the pixel circuit in FIG. 1 in a light emitting stage.

Explanation of reference signs:

100: display panel

110: Pixel circuit

112: drive transistor

114: write circuit

116: Lighting unit

120: Source drive circuit

130: Gate drive circuit

N1～N3: first node～third node

SW1～SW3: the first switch～the third switch

Cs: storage capacitor

Idri: drive current

CT1～CT2: first control signal～second control signal

T1: Write phase

T2: Luminous stage

VDD: system high voltage

VSS: System Low Voltage

Vdata: data voltage

Vref: reference voltage

V1～V3: first node voltage to third node voltage

Va: anode terminal voltage

Detailed ways

Embodiments of the disclosure will be described below with reference to the accompanying drawings. In the drawings, the same reference numerals represent the same or similar elements or method flows.

The specific embodiments of the pixel circuit of the present invention will be described in detail below with reference to the accompanying drawings, but the provided embodiments are not intended to limit the scope of the present invention.

FIG. 1 is a simplified functional block diagram of a display panel 100 according to an embodiment of the disclosure. The display panel 100 includes a plurality of pixel circuits 110 , a source driving circuit 120 and a gate driving circuit 130 , and the plurality of pixel circuits 110 are coupled to the source driving circuit 120 and the gate driving circuit 130 . In order to make the drawing concise and easy to explain, other elements and connections in the display panel 100 are not shown in FIG. 1 .

Each pixel circuit 110 receives the data voltage Vdata from the source driving circuit 120, and receives the first control signal CT1 and the second control signal CT2 from the gate driving circuit 130, and according to the data voltage Vdata, the first control signal CT1 and the second control signal CT1 The control signal CT2 operates.

FIG. 2 is a schematic circuit diagram of the pixel circuit 110 in FIG. 1 according to an embodiment of the disclosure. The pixel circuit 110 includes a driving transistor 112 , a writing circuit 114 , a first switch SW1 , a storage capacitor Cs and a light emitting unit 116 . The driving transistor 112 includes a first terminal, a second terminal and a control terminal, wherein the first terminal of the driving transistor 112 is used to receive the system high voltage VDD, the second terminal of the driving transistor 112 is coupled to the first node N1, and the driving transistor 112 The control terminal is coupled to the second node N2.

The first switch SW1 includes a first terminal, a second terminal and a control terminal, wherein the first terminal of the first switch SW1 is coupled to the first node N1, the second terminal of the first switch SW1 is coupled to the third node N3, and the second terminal of the first switch SW1 is coupled to the third node N3. A control terminal of a switch SW1 is used for receiving a first control signal CT1 from the gate driving circuit 130 .

The storage capacitor Cs includes a first terminal and a second terminal, wherein the first terminal of the storage capacitor Cs is coupled to the second node N2 for receiving the data voltage Vdata. The second terminal of the storage capacitor Cs is directly coupled to the third node N3 for receiving the reference voltage Vref.

The light emitting unit 116 includes an anode terminal and a cathode terminal, the anode terminal is coupled to the third node N3, and the cathode terminal is used for receiving the system low voltage VSS.

In other words, the anode terminal of the light emitting unit 116 is directly coupled to the second terminal of the storage capacitor Cs and the second terminal of the first switch SW1.

The writing circuit 114 is coupled to the second node N2 and the third node N3 and is used for receiving the data voltage Vdata from the source driving circuit 120 . The writing circuit 114 is also used to determine whether to provide the data voltage Vdata to the second node N2 and whether to provide the reference voltage Vref to the third node N3 according to the operation state of the pixel circuit 110 .

In this embodiment, the writing circuit 114 includes a second switch SW2 and a third switch SW3. The second switch SW2 includes a first terminal, a second terminal and a control terminal, wherein the first terminal of the second switch SW2 is used to receive the data voltage Vdata from the source driving circuit 120, and the second terminal of the second switch SW2 is coupled to The second node N2.

The third switch SW3 includes a first terminal, a second terminal and a control terminal, the first terminal of the third switch SW3 is used for receiving the reference voltage Vref, and the second terminal of the third switch SW3 is coupled to the third node N3. Wherein, both the control terminal of the second switch SW2 and the control terminal of the third switch SW3 are used for receiving the second control signal CT2 from the gate driving circuit 130 .

In this embodiment, the driving transistor 112 is used to provide the driving current Idri to the anode terminal of the light emitting unit 116 . Moreover, the driving transistor 112 can determine the magnitude of the driving current Idri, so that the light emitting unit 116 can generate brightness of a specific gray scale.

In practice, the driving transistor 112 , the first switch SW1 , the second switch SW2 and the third switch SW3 can be realized by P-type thin film transistors or other suitable transistors. The light-emitting unit 116 can be realized by light-emitting materials such as organic light-emitting diodes or micro light-emitting diodes, but the present invention is not limited thereto.

FIG. 3 is an operation timing diagram of the pixel circuit 110 in FIG. 1 according to an embodiment of the disclosure. The operation of the pixel circuit 110 will be further described below with reference to FIG. 2 and FIG. 3 . As shown in FIG. 3, in the writing phase T1, the first control signal CT1 is at a disable level (for example, a high voltage level), and the second control signal CT2 is at an enable level (for example, a low voltage level ). Therefore, the first switch SW1 is in an off state, and the second switch SW2 and the third switch SW3 are in an on state.

FIG. 4 is a schematic diagram of driving the equivalent circuit of the pixel circuit 110 in FIG. 1 in the writing phase T1. As shown in FIG. 4 , the data voltage Vdata is transmitted to the second node N2 through the second switch SW2 , so that the second node voltage V2 of the second node N2 is equal to the data voltage Vdata. The reference voltage Vref is transmitted to the third node N3 through the third switch SW3, so that the third node voltage V3 of the third node N3 is equal to the reference voltage Vref.

In this embodiment, the reference voltage Vref is lower than the system low voltage VSS, so the light emitting unit 116 can be kept in the off state in the writing phase T1 to increase the contrast of the display panel 100 .

Next, in the light-emitting phase T2, the first control signal CT1 is at an enable level, and the second control signal CT2 is at a disable level. Therefore, the first switch SW1 is in the on state, and the second switch SW2 and the third switch SW3 are in the off state.

In the light-emitting phase T2 of this embodiment, the second control signal CT2 is switched from the enable level to the disable level first, and then the first control signal CT1 is switched from the disable level to the enable level. However, the present disclosure is not limited thereto. In some embodiments, when the first control signal CT1 switches from the disabled level to the enabled level, the second control signal CT2 switches from the enabled level to the disable level.

FIG. 5 is a schematic diagram of driving the equivalent circuit of the pixel circuit 110 in FIG. 1 in the light-emitting phase T2. As shown in FIG. 5 , the driving transistor 112 provides a driving current Idri to the third node N3 to turn on the light emitting unit 116 . Therefore, the third node voltage V3 changes from the reference voltage Vref to the anode terminal voltage Va of the light emitting unit 116 .

Since the second node N2 is in a floating state (floating), the variation of the third node voltage V3 will be transferred to the second node N2 through the capacitive coupling effect of the storage capacitor Cs, so that the second node voltage V2 can be obtained by The following "Formula 1" expresses:

V2＝Vdata+Va-Vref "Formula 1"

Therefore, the driving current Idri can be expressed by the following "Formula 2":

Wherein, k represents the product of the carrier mobility of the driving transistor 112 , the unit capacitance of the gate oxide layer, and the gate width-to-length ratio, and Vth represents the threshold voltage of the driving transistor 112 .

It can be seen from "Formula 2" that the magnitude of the driving current Idri is related to the threshold voltage of the driving transistor 112 . In addition, the anode terminal voltage Va of the light emitting unit 116 will vary with the magnitude of the driving current Idri flowing through the light emitting unit 116 .

Therefore, when the threshold voltage of the driving transistor 112 includes the threshold voltage variation ΔVth so that the magnitude of the driving current Idri changes, the third node voltage V3 will generate a node voltage variation ΔVa. In this case, the third node voltage V3 needs to be expressed by the following "Formula 3" in the light-emitting phase T2:

V3＝Va+ΔVa "Formula 3"

The node voltage variation ΔVa is also transmitted to the second node N2 through the capacitive coupling effect of the storage capacitor Cs, so that the second node voltage V2 needs to be expressed by the following "Formula 4" in the light-emitting phase T2:

V2＝Vdata+Va-Vref+ΔVa "Formula 4"

In summary, when the threshold voltage of the driving transistor 112 varies, the driving current Idri needs to be expressed by the following "Formula 5" in the light-emitting phase T2:

"Formula 5"

In this embodiment, the node voltage variation ΔVa is directly related to the magnitude of the driving current Idri flowing through the light emitting unit 116 . Moreover, it can be seen from "Formula 5" that the magnitude of the driving current Idri is negatively related to the threshold voltage variation ΔVth. Therefore, the node voltage variation ΔVa is negatively correlated with the critical voltage variation ΔVth, and the corresponding relationship between the node voltage variation ΔVa and the critical voltage variation ΔVth can be used to compensate the influence of the critical voltage variation ΔVth on the driving current Idri.

For example, when the driving transistor 112 has a larger threshold voltage variation ΔVth and the driving current Idri is lower, the node voltage variation ΔVa will be smaller. At this time, the smaller node voltage variation ΔVa is fed back to the second node N2 via the storage capacitor Cs, so that the driving transistor 112 has a larger source/gate voltage difference, thereby increasing the driving current Idri.

For another example, when the driving transistor 112 has a smaller threshold voltage variation ΔVth and the driving current Idri is higher, the node voltage variation ΔVa will be larger. At this time, the larger node voltage variation ΔVa is fed back to the second node N2 via the storage capacitor Cs, so that the driving transistor 112 has a smaller source/gate voltage difference, thereby reducing the driving current Idri.

In other words, even though the driving transistors 112 located in different regions of the display panel 100 have different threshold voltages, the driving current Idri provided by these driving transistors 112 still has a nearly fixed corresponding relationship with the data voltage Vdata.

In some embodiments, the first switch SW1 , the second switch SW2 and the third switch SW3 are implemented with N-type transistors. In this case, the enabling levels of the first control signal CT1 and the second control signal CT2 are high voltage levels, and the disabling levels are low voltage levels.

Table 1 shows the actual luminance measurement results of the display panel implemented by the display panel 100 according to the above-mentioned embodiment, wherein the display panel is divided into a total of nine different regions, and each region contains a plurality of pixel circuits 110 according to the above-mentioned embodiment Realized pixel circuit. As shown in Table 1, nine different regions on the display panel have their respective luminance measurement values, where the unit of the luminance measurement values is nit.

507.9 502.4 504.8 493.5 500.6 501.3 527.6 527.9 532.7

Table I

It can be seen from Table 1 that the display panel 100 and the pixel circuit 110 can provide roughly similar luminance in different subregions of the display panel 100 under high grayscale.

Table 2 shows another actual luminance measurement result of the display panel implemented according to the display panel 100 of the above-mentioned embodiment. Compared with the measurement example in Table 1, in the measurement example in Table 2, the display panel is set to have a lower gray scale.

362.4 360.2 354.9 350.6 352.6 358.9 360.3 361.2 364.9

Table II

Table 3 shows another actual luminance measurement result of the display panel implemented according to the display panel 100 of the above-mentioned embodiment. Compared with the measurement example in Table 2, in the measurement example in Table 3, the display panel is set to have a lower gray scale.

152.7 150.3 149.6 146.3 150.9 151.5 148.3 150.6 151.8

Table three

Table 4 shows another actual luminance measurement result of the display panel implemented according to the display panel 100 of the above-mentioned embodiment. Compared with the measurement example in Table 3, in the measurement example in Table 4, the display panel is set to have a lower gray scale.

29.6 29.5 29.3 28.7 30.1 29.7 28.6 28.9 29.5

Table four

From Table 1 to Table 4, it can be known that the display panel 100 and the pixel circuit 110 can provide uniform display images with similar brightness in different partitions of the display panel 100 under different gray scales.

To sum up, the circuit structure of the pixel circuit 110 is simple, and the variation of the threshold voltage of the driving transistor 112 can be compensated with a small number of operation signals and at least two operation stages. Therefore, the display panel 100 can meet requirements such as narrow frame, high PPI, and high resolution.

Certain terms are used in the description and claims to refer to particular elements. However, those skilled in the art should understand that the same element may be called by different terms. The specification and claims do not use the difference in name as the way to distinguish components, but the difference in function of the components as the basis for distinction. The "comprising" mentioned in the specification and claims is an open term, so it should be interpreted as "including but not limited to". In addition, "coupled" herein includes any direct and indirect connection means. Therefore, if it is described that the first element is coupled to the second element, it means that the first element can be directly connected to the second element through electrical connection or signal connection means such as wireless transmission or optical transmission, or through other elements or connections. The means are indirectly electrically or signally connected to the second element.

In addition, unless otherwise specified in the specification, any singular term also includes plural meanings.

The above are only preferred embodiments of the disclosure, and all equivalent changes and modifications made in accordance with the claims of the disclosure shall fall within the scope of the disclosure.

Claims (10)

1. A pixel circuit, comprising: A driving transistor, including a first terminal, a second terminal and a control terminal, wherein the first terminal of the driving transistor is used to receive a system high voltage, and the second terminal of the driving transistor is coupled to a first a node, the control terminal of the driving transistor is coupled to a second node; A first switch, including a first terminal, a second terminal and a control terminal, wherein the first terminal of the first switch is coupled to the first node, and the second terminal of the first switch is coupled to a third node, the control end of the first switch is used to receive a first control signal; A storage capacitor, including a first terminal and a second terminal, wherein the first terminal of the storage capacitor is coupled to the second node and is used to receive a data voltage, and the second terminal of the storage capacitor is directly coupled to the connected to the third node, and used to receive a reference voltage; and A light emitting unit includes an anode terminal and a cathode terminal, wherein the anode terminal is coupled to the third node, and the cathode terminal is used for receiving a system low voltage. 2. The pixel circuit as claimed in claim 1, further comprising a writing circuit for providing the data voltage to the second node and providing the reference voltage to the third node. 3. The pixel circuit according to claim 2, wherein the writing circuit comprises: A second switch, including a first terminal, a second terminal and a control terminal, wherein the first terminal of the second switch is used to receive the data voltage, and the second terminal of the second switch is coupled to the the second node; and A third switch, including a first terminal, a second terminal and a control terminal, wherein the first terminal of the third switch is used to receive the reference voltage, and the second terminal of the third switch is coupled to the third node; Wherein, the control terminal of the second switch and the control terminal of the third switch are used for receiving a second control signal. 4. The pixel circuit as claimed in claim 3, wherein, in a writing phase, the first control signal is at a disable level, and the second control signal is at an enable level. 5. The pixel circuit as claimed in claim 4, wherein, in a light-emitting phase, the first control signal is the enable level, and the second control signal is the disable level. 6. A display panel, comprising: a gate drive circuit, used to provide a first control signal; a source driving circuit for providing a data voltage; A plurality of pixel circuits, coupled to the gate drive circuit and the source drive circuit, wherein each pixel circuit includes: A driving transistor, including a first terminal, a second terminal and a control terminal, wherein the first terminal of the driving transistor is used to receive a system high voltage, and the second terminal of the driving transistor is coupled to a first a node, the control terminal of the driving transistor is coupled to a second node; A first switch, including a first terminal, a second terminal and a control terminal, wherein the first terminal of the first switch is coupled to the first node, and the second terminal of the first switch is coupled to a third node, the control terminal of the first switch is used to receive the first control signal; A storage capacitor, including a first terminal and a second terminal, wherein the first terminal of the storage capacitor is coupled to the second node and is used to receive the data voltage, and the second terminal of the storage capacitor is directly coupled to the connected to the third node, and used to receive a reference voltage; and A light emitting unit includes an anode terminal and a cathode terminal, wherein the anode terminal is coupled to the third node, and the cathode terminal is used for receiving a system low voltage. 7. The display panel as claimed in claim 6, wherein the pixel circuit further comprises a write circuit for providing the data voltage to the second node and providing the reference voltage to the third node . 8. The display panel as claimed in claim 7, wherein the gate driving circuit is further used to provide a second control signal, and the writing circuit comprises: A second switch, including a first terminal, a second terminal and a control terminal, wherein the first terminal of the second switch is used to receive the data voltage, and the second terminal of the second switch is coupled to the the second node; and A third switch, including a first terminal, a second terminal and a control terminal, wherein the first terminal of the third switch is used to receive the reference voltage, and the second terminal of the third switch is coupled to the third node; Wherein, the control terminal of the second switch and the control terminal of the third switch are used to receive the second control signal. 9. The display panel as claimed in claim 8, wherein, in a writing phase, the first control signal is at a disable level, and the second control signal is at an enable level. 10. The display panel as claimed in claim 9, wherein, in a light-emitting phase, the first control signal is the enable level, and the second control signal is the disable level.