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CN115376466B - Pixel circuit, driving method thereof, display panel and display device - Google Patents

Pixel circuit, driving method thereof, display panel and display device Download PDF

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Publication number
CN115376466B
CN115376466B CN202211169548.XA CN202211169548A CN115376466B CN 115376466 B CN115376466 B CN 115376466B CN 202211169548 A CN202211169548 A CN 202211169548A CN 115376466 B CN115376466 B CN 115376466B
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node
control
circuit
transistor
sub
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CN115376466A (en
Inventor
孙拓
赵西玉
刘利宾
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BOE Technology Group Co Ltd
Beijing BOE Technology Development Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Technology Development Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The invention discloses a pixel circuit and a driving method thereof, a display panel and a display device, wherein the pixel circuit comprises a first control sub-circuit, a second control sub-circuit, a writing sub-circuit, a driving sub-circuit, a voltage regulation sub-circuit and a light emitting device, the first control sub-circuit is connected with a first control end, a second control end, a reference signal end, a reset signal end, a first node and a second node, the second control sub-circuit is connected with a third control end, a first power end and a third node, the writing sub-circuit is connected with a fourth control end, a data signal end and the first node, the voltage regulation sub-circuit is connected with a fifth control end and the first node, the driving sub-circuit is connected with the first node, the second node and the third node, and the light emitting device is connected with the second node and the second power end. According to the invention, the voltage of the first node is regulated and controlled in the light-emitting stage through the voltage regulation and control sub-circuit, so that the potential of the first node is positively correlated with the threshold voltage of the driving transistor, and the voltage difference between the first node and the second node is ensured to be stable.

Description

Pixel circuit, driving method thereof, display panel and display device
Technical Field
The present invention relates generally to the field of display technologies, and in particular, to a pixel circuit, a driving method thereof, a display panel, and a display device.
Background
Organic light-emitting diode (OLED) is increasingly used in high-performance displays. The OLED can be classified into a passive matrix driving (PassiveMatrixOLED, PMOLED) and an active matrix driving (ActiveMatrixOLED, AMOLED) according to the driving manner. The passive matrix driving has the defects of cross talk, high power consumption, low service life and the like, and can not meet the requirement of high-resolution large-size display although the process is simple and the cost is low. In contrast, the active matrix driving is characterized in that a thin film transistor (ThinFilmTransistor, TFT) is added on the panel, so that the pixel unit can emit light within one frame time, the required driving current is small, the power consumption is low, the service life is longer, and the requirements of high-resolution and multi-gray-scale large-size display can be met.
At present, metal oxide thin film transistors (NMOSTFT) are mostly adopted in AMOLED display products, and compared with low temperature polysilicon thin film transistors (LTPS) or low temperature polysilicon-oxide thin film transistors (LTPOTFT), the AMOLED display products are suitable for manufacturing large-scale lines, relatively good in uniformity, low in leakage current and relatively suitable for designing medium-large-size AMOLEDs. But due to its lower mobility, the compensated charge rate is lower with conventional designs and requires optimization to accommodate higher refresh rates.
Disclosure of Invention
In view of the above-described drawbacks or shortcomings in the related art, it is desirable to provide a pixel circuit, a driving method thereof, a display panel, and a display device.
In a first aspect, the present invention provides a pixel circuit comprising a first control sub-circuit, a second control sub-circuit, a writing sub-circuit, a driving sub-circuit, a voltage regulation sub-circuit, and a light emitting device;
The first control sub-circuit is connected with a first control end, a second control end, a reference signal end, a reset signal end, a first node and a second node, and is used for transmitting signals of the reference signal end to the first node under the control of the first control end and transmitting signals of the reset signal end to the second node under the control of the second control end in a reset stage; and in the compensation stage, under the control of the first control end, continuing to transmit the signal of the reference signal end to the first node;
The second control sub-circuit is connected with a third control end, a first power end and a third node and is used for transmitting signals of the first power end to the third node under the control of the third control end in a compensation stage and a light-emitting stage;
The writing sub-circuit is connected with a fourth control end, a data signal end and the first node and is used for transmitting signals of the data signal end to the first node under the control of the fourth control end in a data writing stage;
The voltage regulation sub-circuit is connected with a fifth control end and the first node and is used for keeping the voltage difference between the first node and the second node stable under the control of the fifth control end in a light-emitting stage;
the driving sub-circuit is connected with the first node, the second node and the third node, the light emitting device is connected with the second node and the second power end, and the driving sub-circuit is used for conducting the third node and the second node according to the voltage of the first node so that the light emitting device emits light according to the potential of the second node and the potential of the second power end.
In some examples, the first control sub-circuit includes a first sub-control circuit and a second sub-control circuit;
The first sub-control circuit is connected with the first control end, the reference signal end and the first node and is used for transmitting signals of the reference signal end to the first node under the control of the first control end in the reset stage so as to reset the potential of the first node; and in the compensation stage, under the control of the first control end, continuing to transmit the signal of the reference signal end to the first node;
The second sub-control circuit is connected with the second control end, the reset signal end and the second node and is used for transmitting signals of the reset signal end to the second node under the control of the second control end in the reset stage so as to reset the potential of the second node.
In some examples, the first sub-control circuit includes a first transistor and the second sub-control circuit includes a second transistor;
the control electrode of the first transistor is connected with the first control end, the first electrode of the first transistor is connected with the reference signal end, and the second electrode of the first transistor is connected with the first node;
The control electrode of the second transistor is connected with the second control end, the first electrode of the second transistor is connected with the reset signal end, and the second electrode of the second transistor is connected with the second node.
In some examples, the voltage regulation sub-circuit includes a third transistor, a control electrode of the third transistor is connected to the fifth control terminal, a first electrode of the third transistor is connected to the first node or is floating, and a second electrode of the third transistor is connected to the first node.
In some examples, the first control sub-circuit further comprises a third sub-control circuit;
The third sub-control circuit is connected with a sixth control end, the second node and a fourth node and is used for transmitting a signal of the reset signal end to the fourth node under the control of the sixth control end in the reset stage and resetting the potential of the fourth node; the voltage of the second node is coupled to the fourth node under control of the sixth control terminal during the compensation phase and the data writing phase.
In some examples, the third sub-control circuit includes a fourth transistor having a control electrode connected to the sixth control terminal, a first electrode connected to the second node, and a second electrode connected to the fourth node.
In some examples, the voltage regulation subcircuit includes a third transistor and a first capacitor, the fifth control terminal being connected to the fourth node;
The control electrode of the third transistor is connected with the fifth control end, the first electrode of the third transistor is connected with the first node or is suspended, and the second electrode of the third transistor is connected with the first node;
The first end of the first capacitor is connected with the first power supply end, and the second end of the first capacitor is connected with the fourth node.
In some examples, the second control sub-circuit includes a fifth transistor having a control electrode connected to the third control terminal, a first electrode connected to the first power supply terminal, and a second electrode connected to the third node.
In some examples, the write sub-circuit includes a sixth transistor having a control electrode connected to the fourth control terminal, a first electrode connected to the data signal terminal, and a second electrode connected to the first node.
In some examples, the drive subcircuit includes a drive transistor and a second capacitance;
The control electrode of the driving transistor is connected with the first node, the first electrode of the driving transistor is connected with the third node, and the second electrode of the driving transistor is connected with the second node;
the first end of the second capacitor is connected with the first node, and the second end of the second capacitor is connected with the second node.
In a second aspect, the present invention provides a display panel, including the pixel circuit described above.
In a third aspect, the present invention provides a display device including the above display panel.
In a fourth aspect, the present invention provides a pixel driving method, applied to the above pixel circuit, comprising:
A reset stage, in which a signal of the reference signal terminal is transmitted to a first node under the control of a first control terminal, and a signal of the reset signal terminal is transmitted to a second node under the control of a second control terminal;
The compensation stage is used for continuously transmitting the signal of the reference signal end to the first node under the control of the first control end, transmitting the signal of the first power end to a third node under the control of a third control end, conducting the third node and the second node through a driving sub-circuit, and performing voltage compensation on the second node according to the potentials of the third node and the first node;
A data writing stage, stopping transmitting the signal of the first power supply end to the third node, and transmitting the signal of the data signal end to the first node under the control of the fourth control end;
A light-emitting stage, in which the signal of the data signal end is stopped from being transmitted to the first node, the signal of the first power end is transmitted to a third node under the control of the third control end, and the third node and the second node are conducted through the driving sub-circuit, so that the light-emitting device emits light according to the potential of the second node and the potential of the second power end; and the voltage difference between the first node and the second node is kept stable through a voltage regulation sub-circuit.
The technical scheme provided by the embodiment of the invention can comprise the following beneficial effects:
According to the scheme, the voltage regulation and control subcircuit is arranged at the first node, so that the voltage of the first node can be regulated and controlled in the light-emitting stage, the potential of the first node is positively correlated with the threshold voltage of the driving transistor, the voltage difference between the first node and the second node is ensured to be stable, the compensation effect is optimized, and the problem of uneven display brightness caused by the gate-source voltage loss of the driving transistor due to the parasitic capacitance of the first node in the light-emitting stage is solved; the compensation stage and the data writing stage are separated, so that the compensation time is not limited by the data writing time, and a good compensation effect can be realized on the threshold voltage of the driving sub-circuit.
Drawings
Other features, objects and advantages of the present invention will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the accompanying drawings in which:
FIG. 1 is a schematic diagram of a conventional 5T1C pixel circuit;
FIG. 2 is a schematic block diagram of a pixel circuit according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of FIG. 2 according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of the specific structure of FIG. 3 according to an embodiment of the present invention;
FIG. 5 is a timing diagram of the pixel circuit shown in FIG. 4 according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of another structure of FIG. 2 according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of the specific structure of FIG. 6 according to an embodiment of the present invention;
Fig. 8 is a timing diagram of the pixel circuit shown in fig. 7 according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be noted that, for convenience of description, only the portions related to the invention are shown in the drawings.
It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other. The invention will be described in detail below with reference to the drawings in connection with embodiments.
Referring to fig. 1, the conventional 5T1C pixel circuit includes four switching transistors, a driving transistor DTFT, a storage capacitor Cst, and an organic light emitting diode OLED, both ends of the storage capacitor Cst being connected to a first node N1 and a second node N2, respectively. During the pixel lighting process, the voltage of the anode of the OLED (the second node N2) is raised from Vref-vth+ (Vdt-Vref) (Cst/C N2) to V OLED (i.e., the anode voltage when the OLED is operated), and during the voltage transfer process, the parasitic capacitance of the first node N1 is not negligible, which results in Vgs loss (V OLED-Vc)*(CN1-Cst)/CN1) of the driving transistor DTFT, wherein vc=vref-vth+cst (Data-Vref)/C N2, thereby increasing Mura (display non-uniformity) risk.
In this regard, embodiments of the present invention provide a pixel circuit that has a simple structure and is capable of effectively compensating for the threshold voltage of an N-type driving transistor.
In any of the following embodiments of the present invention, the light emitting device 6 may be a current driven light emitting device including a Light Emitting Diode (LED) or an organic light emitting diode (OrganicLightEmittingDiode; OLED), and the light emitting device 6 is illustrated as an OLED in each example of the present invention.
The transistor used in the invention can be a thin film transistor or a field effect transistor or other devices with the same and similar characteristics, and the source electrode and the drain electrode of the transistor are not distinguished because the source electrode and the drain electrode of the transistor are symmetrical. In the present invention, in order to distinguish the source and drain of a transistor, one of the poles is called a first pole, the other pole is called a second pole, and the gate is called a control pole. In addition, the transistors can be classified into N-type and P-type according to their characteristics; for example, if the transistor is a P-type transistor, the first pole of the transistor is the source and the second pole is the drain; for example, if the transistor is an N-type transistor, the first pole of the transistor is the drain and the second pole is the source. When the N-type transistor is adopted, if the grid electrode inputs high level, the N-type transistor is turned on, and if the grid electrode inputs low level, the N-type transistor is turned off; when the P-type transistor is adopted, if the grid electrode inputs a high level, the P-type transistor is turned off, and if the grid electrode inputs a low level, the P-type transistor is turned on.
As shown in fig. 2, an embodiment of the present invention provides a pixel circuit including a first control sub-circuit 1, a second control sub-circuit 2, a writing sub-circuit 3, a driving sub-circuit 4, a voltage regulation sub-circuit 5, and a light emitting device 6;
The first control sub-circuit 1 is connected with a first control end S1, a second control end S2, a reference signal end Vref, a reset signal end Vint, a first node N1 and a second node N2; the first control sub-circuit 1 is configured to, in a reset phase, transmit a signal of the reference signal terminal Vref to the first node N1 under control of the first control terminal S1, and transmit a signal of the reset signal terminal Vint to the second node N2 under control of the second control terminal S2; in the compensation stage, under the control of the first control end S1, continuously transmitting the signal of the reference signal end Vref to the first node N1, and maintaining the potential of the first node N1;
The second control sub-circuit 2 is connected with the third control terminal S3, the first power supply terminal VDD and the third node N3; the second control sub-circuit 2 is configured to transmit, under control of the third control terminal S3, a signal of the first power supply terminal VDD to the third node N3 in the compensation phase and the light-emitting phase;
The write sub-circuit 3 is connected with the fourth control terminal S4, the Data signal terminal Data and the first node N1; the writing sub-circuit 3 is configured to transmit a signal of the Data signal terminal Data to the first node N1 under the control of the fourth control terminal S4 in the Data writing stage;
The voltage regulation sub-circuit 5 is connected with the fifth control terminal S5 and the first node N1, and is configured to, in a light emitting stage, make the voltage of the first node N1 positively correlated with the threshold voltage of the driving sub-circuit 4 under the control of the fifth control terminal S5, and keep the voltage difference between the first node N1 and the second node N2 stable;
The driving sub-circuit 4 is connected to the first node N1, the second node N2 and the third node N3, the light emitting device 6 is connected to the second node N2 and the second power terminal, and the driving sub-circuit 4 is configured to turn on the third node N3 and the second node N2 according to the voltage of the first node N1, so that the light emitting device 6 emits light according to the potential of the second node N2 and the potential of the second power terminal.
In this example, the voltage V DD provided by the first power supply terminal VDD is a high voltage, and the voltage V SS provided by the second power supply terminal VSS is a low voltage;
The reference signal end Vref and the reset signal end Vint respectively provide reset voltages;
The fifth control terminal S5 is connected to a dc high level signal, where the voltage of the dc high level signal is lower than the voltage provided by the first power supply terminal VDD;
The first pole of the light emitting device 6 is connected to the second node N2, the second pole of the light emitting device 6 is connected to the second power supply terminal, the first pole of the light emitting device 6 is an anode, and the second pole of the light emitting device 6 is a cathode.
If the voltage regulation sub-circuit 5 is not set at the first node N1, referring to the conventional 5T1C pixel circuit shown in fig. 1, in the process of turning on the light emitting device OLED, the initial potential of the second node N2 becomes smaller as the threshold voltage Vth of the driving sub-circuit 4 becomes larger;
Because the driving current of the light emitting device OLED is a constant value, the VSS difference is ignored, and the voltage of the anode (the second node N2) of the light emitting device OLED after the normal turn-on is completed is the same, the voltage jump amplitude of the second node N2 is V OLED-Vref+Vth-Cst*(Data-Vref)/CN2, and if Vth is larger, the jump amplitude is larger;
in fig. 1, the first node N1 is in a floating state, and in theory, the voltage variation at the first node N1 and the voltage variation at the second node N2 are the same, so that the gate-source voltage Vgs of the driving transistor DTFT is unchanged, the Vgs difference of the driving transistor DTFT in different pixel circuits is Vth difference, and the Vth compensation effect is unchanged;
However, because of the parasitic capacitance at the first node N1, the actual jump amplitude of the voltage at the first node N1 is (V OLED-Vref+Vth-Cst*(Data-Vref)/CN2)*(Cst/CN1), the Vgs difference of the driving transistor DTFT in the different pixel circuits is related to Vth, specifically-Vth ((C N1-Cst)/CN1), so that the Vth difference cannot be balanced, resulting in the brightness difference.
In this embodiment, the voltage regulation and control sub-circuit 5 is disposed at the first node, so that the voltage of the first node N1 can be regulated and controlled in the light-emitting stage, so that the potential of the first node N1 is positively correlated with the threshold voltage of the driving transistor DTFT, and the voltage difference between the first node N1 and the second node N2 is ensured to be stable, thereby solving the problem of uneven display brightness caused by the gate-source voltage loss of the driving transistor DTFT due to the parasitic capacitance of the first node N1; the compensation phase and the data writing phase are separated, so that the compensation time is not limited by the data writing time, and a good Vth compensation effect can be realized under the condition that the line time is very short (high resolution and high frame frequency); resetting of the DTFT can be achieved; a wide range of display frame rate variations can be accommodated.
Next, specific circuit configurations of the first control sub-circuit 1, the second control sub-circuit 2, the writing sub-circuit 3, the driving sub-circuit 4, and the voltage regulation sub-circuit 5 included in the pixel circuit provided by the embodiment of the present invention will be exemplarily described.
FIG. 3 is a schematic structural diagram of FIG. 2 according to an embodiment of the present invention; fig. 4 is a schematic structural diagram of fig. 3 according to an embodiment of the present invention.
As shown in fig. 3, the first control sub-circuit 1 includes a first sub-control circuit 11 and a second sub-control circuit 12;
The first sub-control circuit 11 is connected to the first control terminal S1, the reference signal terminal Vref, and the first node N1; the first sub-control circuit 11 is configured to, in a reset phase, under control of the first control terminal S1, transmit a signal of the reference signal terminal Vref to the first node N1, and reset a potential of the first node N1; in the compensation stage, under the control of the first control end S1, continuously transmitting the signal of the reference signal end Vref to the first node N1, and maintaining the potential of the first node N1;
the second sub-control circuit 12 is connected to the second control terminal S2, the reset signal terminal Vint, and the second node N2, and is configured to, in a reset stage, transmit a signal of the reset signal terminal Vint to the second node N2 under control of the second control terminal S2, and reset a potential of the second node N2.
As an achievable way, as shown in fig. 4, the first sub-control circuit 11 includes a first transistor T1, and the second sub-control circuit 12 includes a second transistor T2;
the control electrode of the first transistor T1 is connected with the first control end S1, the first electrode of the first transistor T1 is connected with the reference signal end Vref, and the second electrode of the first transistor T1 is connected with the first node N1;
The control electrode of the second transistor T2 is connected to the second control terminal S2, the first electrode of the second transistor T2 is connected to the reset signal terminal Vint, and the second electrode of the second transistor T2 is connected to the second node N2.
As an implementation manner, as shown in fig. 4, the voltage regulation sub-circuit 5 includes a third transistor T3, a control electrode of the third transistor T3 is connected to the fifth control terminal S5, a first electrode of the third transistor T3 is connected to the first node or is floating, a second electrode of the third transistor T3 is connected to the first node N1, and a capacitance between a gate electrode and the second electrode of the third transistor T3 is a part of a parasitic capacitance of the first node N1.
In this example, the signal provided by the fifth control terminal S5 is preferably a direct current signal, and the potential of the fifth control terminal S5 is a fixed potential.
As an implementation manner, as shown in fig. 4, the second control sub-circuit 2 includes a fifth transistor T5, a control electrode of the fifth transistor T5 is connected to the third control terminal S3, a first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, and a second electrode of the fifth transistor T5 is connected to the third node N3.
As an implementation manner, as shown in fig. 4, the write sub-circuit 3 includes a sixth transistor T6, a control electrode of the sixth transistor T6 is connected to the fourth control terminal S4, a first electrode of the sixth transistor T6 is connected to the Data signal terminal Data, and a second electrode of the sixth transistor T6 is connected to the first node N1.
As an implementation, as shown in fig. 4, the driving sub-circuit 4 includes a driving transistor DTFT and a second capacitor Cst;
The control electrode of the driving transistor DTFT is connected with the first node N1, the first electrode of the driving transistor DTFT is connected with the third node N3, and the second electrode of the driving transistor DTFT is connected with the second node N2;
The first end of the second capacitor Cst is connected to the first node N1, and the second end of the second capacitor Cst is connected to the second node N2.
Fig. 4 specifically shows exemplary structures of the first control sub-circuit 1, the second control sub-circuit 2, the writing sub-circuit 3, the driving sub-circuit 4, and the voltage regulation sub-circuit 5, respectively. It will be readily appreciated by those skilled in the art that the implementation of the first control sub-circuit 1 is not limited thereto, as long as it is capable of performing its function; the implementation of the second control sub-circuit 2 is not limited to this as long as it can realize its function; the implementation of the write sub-circuit 3 is not limited to this, as long as it can realize its function; the implementation of the driving sub-circuit 4 is not limited to this as long as it can realize its function; and the implementation of the voltage regulation sub-circuit 5 is not limited thereto as long as the functions thereof can be implemented.
The pixel circuit illustrated in fig. 4 is a 6T1C pixel circuit, and includes a first transistor T1, a second transistor T2, a third transistor T3, a fifth transistor T5, a sixth transistor T6, a driving transistor DTFT, and a second capacitor Cst, and the light emitting device 6 includes an OLED. The third transistor T3 and the driving transistor DTFT are both N-type transistors; the other transistors may be N-type transistors or P-type transistors. In this embodiment, all transistors are preferably N-type transistors.
FIG. 6 is a schematic diagram of another structure of FIG. 2 according to an embodiment of the present invention; fig. 7 is a schematic structural diagram of fig. 6 according to an embodiment of the present invention.
As shown in fig. 6, the first control sub-circuit 1 is connected to a first control terminal S1, a second control terminal S2, a reference signal terminal Vref, a reset signal terminal Vint, a first node N1, a second node N2, and a fourth node N4, and the first control sub-circuit 1 includes a first sub-control circuit 11, a second sub-control circuit 12, and a third sub-control circuit 13;
The first sub-control circuit 11 is connected with the first control end S1, the reference signal end Vref and the first node N1, and is configured to, in a reset stage, transmit a signal of the reference signal end Vref to the first node N1 under control of the first control end S1, and reset a potential of the first node N1; in the compensation stage, under the control of the first control end S1, continuously transmitting the signal of the reference signal end Vref to the first node N1, and maintaining the potential of the first node N1;
The second sub-control circuit 12 is connected to the second control terminal S2, the reset signal terminal Vint, and the second node N2, and is configured to, in a reset stage, transmit a signal of the reset signal terminal Vint to the second node N2 under control of the second control terminal S2, and reset a potential of the second node N2;
The third sub-control circuit 13 is connected to the sixth control terminal S6, the second node N2, and the fourth node N4, and is configured to, in a reset stage, transmit, under control of the sixth control terminal S6, a signal of the reset signal terminal Vint to the fourth node N4, and reset the potential of the fourth node N4; in the compensation stage, under the control of the sixth control end S6, continuously transmitting the signal of the reset signal end Vint to the fourth node N4, and maintaining the potential of the fourth node N4; and during the data writing phase, the voltage of the second node N2 is coupled to the fourth node N4 under the action of the sixth control terminal S6.
As an achievable way, as shown in fig. 7, the first sub-control circuit 11 includes a first transistor T1, the second sub-control circuit 12 includes a second transistor T2, and the third sub-control circuit 13 includes a fourth transistor T4;
the control electrode of the first transistor T1 is connected with the first control end S1, the first electrode of the first transistor T1 is connected with the reference signal end Vref, and the second electrode of the first transistor T1 is connected with the first node N1;
the control electrode of the second transistor T2 is connected with the second control end S2, the first electrode of the second transistor T2 is connected with the reset signal end Vint, and the second electrode of the second transistor T2 is connected with the second node N2;
The control electrode of the fourth transistor T4 is connected to the sixth control terminal S6, the first electrode of the fourth transistor T4 is connected to the second node N2, and the second electrode of the fourth transistor T4 is connected to the fourth node N4.
As an implementation manner, as shown in fig. 7, the voltage regulation sub-circuit 5 includes a third transistor T3 and a first capacitor C1, and the fifth control terminal S5 is connected to the fourth node N4;
The control electrode of the third transistor T3 is connected to the fifth control terminal S5, the first electrode of the third transistor T3 is connected to the first node or is floating, the second electrode of the third transistor T3 is connected to the first node N1, and the capacitance between the gate and the second electrode of the third transistor T3 is used as a part of the parasitic capacitance of the first node N1;
The first end of the first capacitor C1 is connected to the first power supply terminal VDD, and the second end of the first capacitor C1 is connected to the fourth node N4.
As an implementation manner, as shown in fig. 7, the second control sub-circuit 2 includes a fifth transistor T5, a control electrode of the fifth transistor T5 is connected to the third control terminal S3, a first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, and a second electrode of the fifth transistor T5 is connected to the third node N3.
As an implementation manner, as shown in fig. 7, the write sub-circuit 3 includes a sixth transistor T6, a control electrode of the sixth transistor T6 is connected to the fourth control terminal S4, a first electrode of the sixth transistor T6 is connected to the Data signal terminal Data, and a second electrode of the sixth transistor T6 is connected to the first node N1.
In some examples, the drive subcircuit 4 includes a drive transistor DTFT and a second capacitance Cst;
The control electrode of the driving transistor DTFT is connected with the first node N1, the first electrode of the driving transistor DTFT is connected with the third node N3, and the second electrode of the driving transistor DTFT is connected with the second node N2;
The first end of the second capacitor Cst is connected to the first node N1, and the second end of the second capacitor Cst is connected to the second node N2.
Fig. 7 specifically shows exemplary structures of the first control sub-circuit 1, the second control sub-circuit 2, the writing sub-circuit 3, the driving sub-circuit 4, and the voltage regulation sub-circuit 5, respectively. It will be readily appreciated by those skilled in the art that the implementation of the first control sub-circuit 1 is not limited thereto, as long as it is capable of performing its function; the implementation of the second control sub-circuit 2 is not limited to this as long as it can realize its function; the implementation of the write sub-circuit 3 is not limited to this, as long as it can realize its function; the implementation of the driving sub-circuit 4 is not limited to this as long as it can realize its function; and the implementation of the voltage regulation sub-circuit 5 is not limited thereto as long as the functions thereof can be implemented.
The pixel circuit illustrated in fig. 7 is a 7T2C pixel circuit, and includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a driving transistor DTFT, a first capacitor C1, and a second capacitor Cst, and the light emitting device 6 includes an OLED. The third transistor T3 and the driving transistor DTFT are both N-type transistors; the other transistors may be N-type transistors or P-type transistors. In this embodiment, all transistors are preferably N-type transistors.
Next, a pixel driving method will be described with reference to a timing chart shown in fig. 5, taking the pixel circuit shown in fig. 4 as an example. The 6T1C pixel circuit illustrated in fig. 4 includes a first transistor T1, a second transistor T2, a third transistor T3, a fifth transistor T5, a sixth transistor T6, a driving transistor DTFT and a second capacitor Cst, and the light emitting device 6 includes an OLED, and the connection manner of each element can be referred to the description of the corresponding parts above. The transistors are all N-type transistors.
The pixel driving method includes:
one frame period includes at least a reset phase, a compensation phase, a data writing phase, and a light emitting phase.
The reset phase includes a t1 phase and a t2 phase, and in the t1 and t2 phases, the second sub-control circuit 12 transmits a signal of the reset signal terminal Vint to the second node N2 under the control of the second control terminal S2; at the stage t2, the first sub-control circuit 11 sends the signal of the reference signal terminal Vref to the first node N1 under the control of the first control terminal S1 to reset the first node N1 and the second node N2.
For example, the first control terminal S1 and the second control terminal S2 output a high level signal, the first transistor T1 and the second transistor T2 are turned on, the remaining transistors are turned off, and the signal of the reference signal terminal Vref is input to the first node N1, V N1 =vref; the signal of the reset signal terminal Vint is input to the second node N2, V N2 =vint. An initial gate-source voltage vgs=vref-Vint is written to the driving transistor DTFT.
For example, the reset phase may be set to correspond to the t2 phase only, that is, the signal provided by the second control terminal S2 in the t1 phase in the timing diagram shown in fig. 5 is set to a low level signal, and the first node N1 and the second node N2 may both be reset in the t2 phase.
And in the compensation stage, under the control of the first control end S1, the signal of the reference signal end Vref is continuously transmitted to the first node N1, the potential of the first node N1 is maintained, and under the control of the third control end S3, the signal of the first power end VDD is transmitted to the third node N3, the third node N3 and the second node N2 are conducted through the driving sub-circuit 4, and the voltage compensation is performed on the second node N2 according to the potentials of the third node N3 and the first node N1.
For example, the first control terminal S1 continues to output the high level signal, the first transistor T1 is turned on, the third control terminal S3 outputs the high level signal, the fifth transistor T5 is turned on, the rest of the transistors are turned off, the signal of the reference signal terminal Vref continues to be transmitted to the first node N1, the signal of V N1 =vref at the first power supply terminal VDD is input to the third node N3 until vgs=vth of the driving transistor DTFT, and at this time, the anode voltage of the OLED, that is, V N2 =vref-Vth.
In the Data writing stage, the signal of the first power supply terminal VDD is stopped to be supplied to the third node N3, and the signal of the Data signal terminal Data is supplied to the first node N1 under the control of the fourth control terminal S4.
Illustratively, the fourth control terminal S4 outputs a high level signal, the sixth transistor T6 is turned on, and the signal of the Data signal terminal Data is input to the first node N1;
the rest of the transistors are turned off, no current passes through the driving transistor DTFT, the voltage of the second node N2 becomes Vref-vth+cst (Data-Vref)/(cst+c OLED+C12), where C 12 is the parasitic capacitance of the second node N2, C OLED is the intrinsic capacitance of the OLED, vgs=data of the driving transistor (Vref-vth+cst (Data-Vref)/(cst+c OLED+C12)).
In the light-emitting stage, the signal of the Data signal end Data is stopped to be transmitted to the first node N1, the signal of the first power end VDD is transmitted to the third node N3 under the control of the third control end S3, and the third node N3 and the second node N2 are conducted through the driving sub-circuit 4, so that the light-emitting device 6 emits light according to the potential of the second node N2 and the potential of the second power end; and the voltage difference between the first node N1 and the second node N2 is kept stable by the voltage regulation subcircuit 5.
Illustratively, the third control terminal S3 outputs a high level signal, and the fifth transistor T5 is turned on; the fifth control terminal S5 is connected to a dc high level signal, which is higher than the voltage of the first node N1 when the OLED is turned on, the third transistor T3 is turned on, the capacitance of the third transistor T3 is a part of the parasitic capacitance of the first node N1, after the OLED is normally turned on, the voltage of the first node N1 becomes data+ (VOLED-vref+vth-Cst (Data-Vref)/C N2)*(Cst/CN1), the voltage of the second node N2 becomes V OLED, the rest of the transistors are turned off, the pixel emits light, and I OLED =k (Vgs-Vth) 2.
It will be appreciated that the parasitic capacitance of the first node N1 is no longer a constant but a variable related to the threshold voltage Vth of the drive transistor. The larger Vth, the more the voltage of the first node N1 rises, the lower Vgs of the third transistor T3, that is, the capacitance of the third transistor T3 decreases. Accordingly, the lower the parasitic capacitance of the first node N1, the smaller the voltage of the dropped first node N1. In the description of the conventional 5T1C pixel circuit, it is mentioned that the dependence of the difference in Vgs of the driving transistor DTFT on the threshold voltage Vth is expressed as-Vth ((C N1-Cst)/CN1).
In this embodiment, under the control of the third transistor T3, when Vth becomes large (C N1-Cst)/CN1 becomes small, the difference in Vgs of the different driving transistors DTFT of the threshold voltage Vth is reduced, thereby improving the compensation effect.
Taking the pixel circuit shown in fig. 7 as an example, a pixel driving method will be described with reference to the timing chart shown in fig. 8. The pixel circuit is a 7T2C pixel circuit, and includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a driving transistor DTFT, a first capacitor C1 and a second capacitor Cst, the light emitting device 6 includes an OLED, and the connection manner of each element can be referred to the description of the corresponding parts above. The transistors are all N-type transistors.
The pixel driving method includes:
one frame period includes at least a reset phase, a compensation phase, a data writing phase, and a light emitting phase.
In the reset stage, in the t1 and t2 stages, the second sub-control circuit 12 transmits the signal of the reset signal terminal Vint to the second node N2 under the control of the second control terminal S2, and the third sub-control circuit 13 transmits the signal of the reset signal terminal Vint to the fourth node N4 under the control of the sixth control terminal S6; in the t2 stage, the first sub-control circuit 11 transmits the signal of the reference signal terminal Vref to the first node N1 under the control of the first control terminal S1, so as to reset the first node N1, the second node N2, and the fourth node N4 in the reset stage.
For example, the first control terminal S1, the second control terminal S2 and the sixth control terminal S6 output high level signals, the first transistor T1, the second transistor T2 and the fourth transistor T4 are turned on, the rest of the transistors are turned off, and the signal of the reference signal terminal Vref is input to the first node N1, V N1 =vref; the signal of the reset signal terminal Vint is input to the second node N2 and the fourth node N4, V N2＝VN4 =vint. An initial gate-source voltage vgs=vref-Vint is written to the driving transistor DTFT.
The compensation stage, under the control of the first control end S1, continuously transmitting the signal of the reference signal end Vref to the first node N1, and maintaining the potential of the first node N1;
Under the control of a third control end S3, a signal of a first power end VDD is transmitted to a third node N3, the third node N3 and a second node N2 are conducted through a driving sub-circuit 4, and voltage compensation is carried out on the second node N2 according to the potentials of the third node N3 and the first node N1;
The voltage of the second node N2 is coupled to the fourth node N4 under the control of the sixth control terminal S6.
For example, the first control terminal S1 continues to output the high level signal, the third control terminal S3 and the sixth control terminal S6 all output the high level signal, the first transistor T1, the fifth transistor T5 and the fourth transistor T4 are turned on, the rest of the transistors are turned off, the signal of the reference signal terminal Vref continues to be transmitted to the first node N1, the signal of the first power supply terminal VDD is input to the third node N3 until vgs=vth of the driving transistor DTFT, at this time, the voltage of the anode (i.e., the second node) of the OLED is Vref-Vth, and the voltage of the fourth node is Vref-Vth.
A Data writing stage, stopping transmitting the signal of the first power supply terminal VDD to the third node N3, and transmitting the signal of the Data signal terminal Data to the first node N1 under the control of the fourth control terminal S4;
the voltage of the second node N2 is coupled to the fourth node N4 under the action of the sixth control terminal S6.
Illustratively, the fourth control terminal S4 outputs a high level signal, the sixth transistor T6 is turned on, and the signal of the Data signal terminal Data is input to the first node N1; the sixth control terminal S6 continues to output the high level signal, and the fourth transistor T4 is turned on;
The rest transistors are turned off, no current passes through the driving transistor DTFT, and the voltages of the second node N2 and the fourth node N4 become Vref-vth+cst (Data-Vref)/(cst+c OLED+C12), wherein C 12 is the parasitic capacitance of the second node N2, and C OLED is the intrinsic capacitance of the OLED. Vgs=data- (Vref-vth+cst)/(cst+c OLED+C12) of the driving transistor.
In the light-emitting stage, the signal of the Data signal end Data is stopped to be transmitted to the first node N1, the signal of the first power end VDD is transmitted to the third node N3 under the control of the third control end S3, and the third node N3 and the second node N2 are conducted through the driving sub-circuit 4, so that the light-emitting device 6 emits light according to the potential of the second node N2 and the potential of the second power end; and the voltage difference between the first node N1 and the second node N2 is kept stable by the voltage regulation subcircuit 5.
Illustratively, the third control terminal S3 outputs a high level signal and the fifth transistor T5 is turned on; the gate voltage of the third transistor T3 is the voltage of the fourth node N4, the source voltage of the third transistor T3 is the voltage of the first node N1, the third transistor T3 is turned on, the source voltage of the third transistor T3 (i.e., the voltage of the first node N1) is in accordance with the jump amplitude due to the gate-source voltage Vgs of the driving transistor, while the voltage of the fourth node N4 is inversely related to Vth, and the voltage of the first node N1 is positively related to Vth.
The parasitic capacitance of the first node N1 is no longer a constant but a variable related to the threshold voltage Vth of the drive transistor. The larger Vth, the more the voltage of the first node N1 rises, the lower Vgs of the third transistor T3, that is, the capacitance of the third transistor T3 decreases. Accordingly, the lower the parasitic capacitance of the first node N1, the smaller the voltage of the divided first node N1, and the correlation between the Vgs of the driving transistor DTFT and the threshold voltage Vth is represented as-Vth ((C N1-Cst)/CN1), and under the control of the third transistor T3, when Vth becomes larger (C N1-Cst)/CN1 becomes smaller, so that the Vgs of the driving transistor DTFT with different threshold voltages Vth is reduced, thereby improving the compensation effect.
In addition, since the voltage of the fourth node N4 is inversely related to Vth, and the voltage of the first node N1 is positively related to Vth, the capacitance of the third transistor T3 in the pixel circuit of fig. 7 is larger than that of the third transistor T3 in the pixel circuit of fig. 4 under the same Vth difference, so that the third transistor T3 in the pixel circuit of fig. 7 can be designed smaller, which is beneficial to the layout of the circuit; meanwhile, due to the voltage division effect of C1, DATA RANGE of the pixel circuit can be adjusted by the size of C1.
The embodiment of the invention also provides a display panel which comprises the pixel circuit.
The embodiment of the invention also provides a display device which comprises the display panel.
The display device is, for example but not limited to, a desktop computer, a tablet computer, a notebook computer, a mobile phone, a PDA (Personal DIGITAL ASSISTANT), a GPS (Global Positioning System; global positioning system), a vehicle-mounted display, a projection display, a video camera, a digital camera, an electronic watch, a calculator, an electronic instrument, an instrument, a liquid crystal panel, an electronic paper, a television, a display, a digital photo frame, a navigator, or any other product or component having a display function, and can be applied to products or components of public display, phantom display, or the like.
The beneficial technical effects of the display panel and the display device provided by the embodiment of the invention can refer to the beneficial technical effects of the pixel circuit, and are not repeated here.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
The present invention employs first, second, etc. to describe various information, but such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, a first message may also be referred to as a second message, and similarly, a second message may also be referred to as a first message, without departing from the scope of the invention.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the connection may be direct connection, indirect connection via an intermediate medium, communication between two elements, wireless connection, or wired connection. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
The above description is only illustrative of the preferred embodiments of the present invention and of the principles of the technology employed. It will be appreciated by persons skilled in the art that the scope of the invention referred to in the present invention is not limited to the specific combinations of the technical features described above, but also covers other technical features formed by any combination of the technical features described above or their equivalents without departing from the inventive concept. Such as the above-mentioned features and the technical features disclosed in the present invention (but not limited to) having similar functions are replaced with each other.

Claims (13)

1. The pixel circuit is characterized by comprising a first control sub-circuit, a second control sub-circuit, a writing sub-circuit, a driving sub-circuit, a voltage regulation sub-circuit and a light emitting device;
The first control sub-circuit is connected with a first control end, a second control end, a reference signal end, a reset signal end, a first node and a second node, and is used for transmitting signals of the reference signal end to the first node under the control of the first control end and transmitting signals of the reset signal end to the second node under the control of the second control end in a reset stage; and in the compensation stage, under the control of the first control end, continuing to transmit the signal of the reference signal end to the first node;
The second control sub-circuit is connected with a third control end, a first power end and a third node and is used for transmitting signals of the first power end to the third node under the control of the third control end in a compensation stage and a light-emitting stage;
The writing sub-circuit is connected with a fourth control end, a data signal end and the first node and is used for transmitting signals of the data signal end to the first node under the control of the fourth control end in a data writing stage;
The voltage regulation sub-circuit is connected with a fifth control end and the first node and is used for keeping the voltage difference between the first node and the second node stable under the control of the fifth control end in a light-emitting stage;
the driving sub-circuit is connected with the first node, the second node and the third node, the light emitting device is connected with the second node and the second power end, and the driving sub-circuit is used for conducting the third node and the second node according to the voltage of the first node so that the light emitting device emits light according to the potential of the second node and the potential of the second power end.
2. The pixel circuit according to claim 1, wherein the first control sub-circuit includes a first sub-control circuit and a second sub-control circuit;
The first sub-control circuit is connected with the first control end, the reference signal end and the first node and is used for transmitting signals of the reference signal end to the first node under the control of the first control end in the reset stage so as to reset the potential of the first node; and in the compensation stage, under the control of the first control end, continuing to transmit the signal of the reference signal end to the first node;
The second sub-control circuit is connected with the second control end, the reset signal end and the second node and is used for transmitting signals of the reset signal end to the second node under the control of the second control end in the reset stage so as to reset the potential of the second node.
3. The pixel circuit of claim 2, wherein the first sub-control circuit comprises a first transistor and the second sub-control circuit comprises a second transistor;
the control electrode of the first transistor is connected with the first control end, the first electrode of the first transistor is connected with the reference signal end, and the second electrode of the first transistor is connected with the first node;
The control electrode of the second transistor is connected with the second control end, the first electrode of the second transistor is connected with the reset signal end, and the second electrode of the second transistor is connected with the second node.
4. The pixel circuit of claim 2, wherein the voltage regulation sub-circuit comprises a third transistor, a control electrode of the third transistor is connected to the fifth control terminal, a first electrode of the third transistor is suspended or connected to the first node, and a second electrode of the third transistor is connected to the first node.
5. The pixel circuit of claim 2, wherein the first control sub-circuit further comprises a third sub-control circuit;
The third sub-control circuit is connected with a sixth control end, the second node and a fourth node and is used for transmitting a signal of the reset signal end to the fourth node under the control of the sixth control end in the reset stage and resetting the potential of the fourth node; the voltage of the second node is coupled to the fourth node under control of the sixth control terminal during the compensation phase and the data writing phase.
6. The pixel circuit according to claim 5, wherein the third sub-control circuit comprises a fourth transistor, a control electrode of the fourth transistor being connected to the sixth control terminal, a first electrode of the fourth transistor being connected to the second node, and a second electrode of the fourth transistor being connected to the fourth node.
7. The pixel circuit of claim 5, wherein the voltage regulation subcircuit includes a third transistor and a first capacitor, the fifth control terminal being connected to the fourth node;
the control electrode of the third transistor is connected with the fifth control end, the first electrode of the third transistor is suspended or connected with the first node, and the second electrode of the third transistor is connected with the first node;
The first end of the first capacitor is connected with the first power supply end, and the second end of the first capacitor is connected with the fourth node.
8. The pixel circuit of claim 1, wherein the second control sub-circuit comprises a fifth transistor, a control electrode of the fifth transistor being connected to the third control terminal, a first electrode of the fifth transistor being connected to a first power supply terminal, and a second electrode of the fifth transistor being connected to a third node.
9. The pixel circuit of claim 1, wherein the write sub-circuit comprises a sixth transistor having a control electrode connected to the fourth control terminal, a first electrode connected to the data signal terminal, and a second electrode connected to the first node.
10. The pixel circuit of claim 1, wherein the drive sub-circuit comprises a drive transistor and a second capacitance;
The control electrode of the driving transistor is connected with the first node, the first electrode of the driving transistor is connected with the third node, and the second electrode of the driving transistor is connected with the second node;
the first end of the second capacitor is connected with the first node, and the second end of the second capacitor is connected with the second node.
11. A display panel comprising the pixel circuit of any one of claims 1-10.
12. A display device comprising the display panel of claim 11.
13. A pixel driving method applied to the pixel circuit according to any one of claims 1 to 10, comprising:
A reset stage, in which a signal of the reference signal terminal is transmitted to a first node under the control of a first control terminal, and a signal of the reset signal terminal is transmitted to a second node under the control of a second control terminal;
The compensation stage is used for continuously transmitting the signal of the reference signal end to the first node under the control of the first control end, transmitting the signal of the first power end to a third node under the control of a third control end, conducting the third node and the second node through a driving sub-circuit, and performing voltage compensation on the second node according to the potentials of the third node and the first node;
A data writing stage, stopping transmitting the signal of the first power supply end to the third node, and transmitting the signal of the data signal end to the first node under the control of the fourth control end;
A light-emitting stage, in which the signal of the data signal end is stopped from being transmitted to the first node, the signal of the first power end is transmitted to a third node under the control of the third control end, and the third node and the second node are conducted through the driving sub-circuit, so that the light-emitting device emits light according to the potential of the second node and the potential of the second power end; and the voltage difference between the first node and the second node is kept stable through a voltage regulation sub-circuit.
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