CN108701676A - Assembly having a shielded wire of an upper wiring layer electrically coupled with a shielded wire of a lower wiring layer - Google Patents

Abstract

Some embodiments include a kind of sub-assembly with the first wiring layer, and first wiring layer has multiple first shielding lines and the first signal wire.First shielding line and first signal wire have the first segment extended along a first direction and extend along the first direction and from the second segment of the first segment lateral shift.The sub-assembly includes the second wiring layer, and second wiring layer is under first wiring layer and has multiple secondary shielding lines and second signal line.The secondary shielding line and the second signal line have the third section extended along the first direction and along first direction extensions and from the 4th section of the third section lateral shift.Below the first segment that described 4th section of the secondary shielding line extends to first shielding line, and it is electrically coupled to by perpendicular interconnection the first segment of first shielding line.

Description

having the shielded wire of the upper wiring layer electrically coupled with the shielded wire of the lower wiring layer assembly

technical field

An assembly having a shielded wire of an upper wiring layer electrically coupled to a shielded wire of a lower wiring layer.

Background technique

An integrated circuit may include multiple layers of stacked wiring. The layer may include signal lines alternately arranged with shielding lines. Shielded wires can be used to mitigate crosstalk between adjacent signal wires. An example configuration including three stacked wiring layers is shown in FIG. 1 . Specifically, the configuration shows a first wiring layer M1, a second wiring layer M2, and a third wiring layer M3; wherein M3 is above M2, and M2 is above M1. Although three wiring layers are shown, it should be understood that there may be other wiring layers below and/or above the illustrated layers. Also, although the illustrated wiring layers are labeled M1 to M3, if other wiring layers are present, the illustrated layers may actually be M2 to M4; M3 to M6; etc., depending on the wiring layers below the illustrated wiring layers Number of.

Each of the illustrated layers includes signal lines alternately arranged with shielded lines. It may be desirable for shielded wires within one layer to be electrically connected to shielded wires of other layers above and below the one layer. For example, it may be desirable for the shielded wires in layer M2 to be electrically connected to the shielded wires in layer M1 and the shielded wires in layer M3 so as to mitigate coupling noise between vertically stacked layers.

Since the wires in layer M1 continue perpendicularly to the wires in layer M2, the connection of the shielded wires of layer M2 to the shielded wires of layer M1 is relatively straight. However, since the wiring in layer M2 is parallel to the wiring in layer M3, and the shielding lines are staggered in layer M2 with respect to layer M3, the connection of the shielding lines of layer M2 to the shielding lines of layer M3 is problematic. Therefore, there is no vertical overlap between the shielded wires of layer M2 and the shielded wires of layer M3.

It would be desirable to develop architectures that enable coupling between shielded wires of stacked layers of the type illustrated in FIG. 1 as layers M2 and M3.

Description of drawings

FIG. 1 is a schematic three-dimensional view of a prior art wiring layer arrangement.

2-2C are schematic diagrams of example embodiment arrangements of wiring layers. Figure 2 is a top view. 2A-2C are schematic cross-sectional views along lines 2A-2A, 2B-2B, and 2C-2C, respectively, in FIG. 2 .

FIG. 3 is an enlarged view of area "3" of FIG. 2 .

4 and 4A are schematic diagrams of example embodiment arrangements of wiring layers. Figure 4 is a top view. FIG. 4A is a schematic cross-sectional view along line 4A-4A of FIG. 4 .

5 is an exploded view of an example embodiment assembly of wiring layers. In the view of Figure 5, three layers are stacked.

6 to 8 are schematic top views of the individual layers of FIG. 5 .

FIG. 9 is a schematic top view showing an example grid of interconnecting shield lines containing the three layers of FIG. 5 .

Figure 10 is an exploded view of another example embodiment assembly of wiring layers. In the view of Figure 10, three layers are stacked.

11 to 13 are schematic top views of the individual layers of FIG. 10 .

FIG. 14 is a schematic top view showing an example grid of interconnected shield lines containing the three layers of FIG. 10 .

15A is a schematic top view of an assembly of wiring layers across a substrate, and FIG. 15B is a view of an expanded area of FIG. 15A to illustrate alternating signal and shield lines. In the top view of FIG. 15A , three wiring layers of FIG. 5 are stacked, where the portion shown in FIG. 5 is within the region “FIG. 5 ” of FIG. 15A .

16A is a schematic top view of an example arrangement of circuitry across a substrate. 16B is a view of the expanded area of FIG. 16A to illustrate alternating signal and shield lines, and to show redundant (or dummy) structures.

17 is a schematic top view of an example arrangement of circuits from two stacked wiring layers.

18 is a view of the expanded area of FIG. 17 to illustrate alternating signal and shield routing within stacked wiring layers, and to show redundant (or dummy) structures.

Figure 19 shows a schematic top view of a comparative example circuit arrangement.

Figure 20 shows a schematic top view comparing a pair of example circuit arrangements.

FIG. 21 is an exploded view of an assembly of example wiring layers that may be used in one of the circuit arrangements of FIG. 20 . In the view of FIG. 21, three wiring layers are stacked.

22 to 24 are schematic top views of the individual wiring layers of FIG. 21 .

25 is a schematic cross-sectional side view along line 25 - 25 shown in FIGS. 23 and 24 , and through wiring layers M2 and M3 of FIGS. 23 and 24 .

26 is a view of the extended area of FIGS. 23 and 24 and shows the wiring layer of FIG. 24 stacked above the wiring layer of FIG. 23 . The area in Figure 26 is indicated by the dashed line "Figure 26" in Figures 23 and 24 .

27A-27C are enlarged schematic top views of regions of the M2 wiring layer of FIG. 23 showing example alternative configurations.

FIG. 28 is an exploded view of an assembly of example wiring layers that may be used in one of the circuit arrangements of FIG. 20 . In the view of Figure 28, three layers are stacked.

29 to 31 are schematic top views of the individual layers of FIG. 28 .

32A-C are schematic cross-sectional side views along lines 32A-32A, 32B-32B, and 32C-32C of FIGS. 30 and 31 , and through wiring layers M2 and M3 of FIGS. 30 and 31 .

33 and 34 are enlarged schematic top views of regions of wiring layer M3 of FIG. 31 showing example alternative configurations.

35 and 36 are enlarged schematic top views of regions of wiring layer M2 of FIG. 30 showing example alternative configurations.

Detailed ways

Some embodiments include architectures in which signal lines and shield lines within routing layers are configured to have offset regions. Such offset regions may enable vertical overlap to occur between the shielded lines of the upper wiring layer and the shielded lines of the lower wiring layer, even though the shielded lines within the two wiring layers run substantially to each other, and even in The configuration of the configuration in which the shielded wires in the lower wiring layer are staggered relative to the shielded wires in the upper wiring layer.

Example embodiments are described with reference to FIGS. 2 to 36 .

Referring to Figures 2 through 2C, areas of the integrated assembly 510 are illustrated. Assembly 510 includes a pair of vertically stacked wiring layers M2 and M3. Layer M2 is shown in dashed lines in the top view of FIG. 2 to indicate that this layer is below layer M3.

Layer M3 includes a shielded wire 512 and a signal wire 514 adjacent to the shielded wire. Lines 512 and 514 may represent a large number of multiple shield lines and signal lines formed in alternating relationship within wiring layer M3.

Layer M2 includes a shielded wire 516 and a signal wire 518 adjacent to the shielded wire. Lines 516 and 518 may represent a large number of multiple shield lines and signal lines formed in alternating relationship within wiring layer M2.

In some embodiments, the wiring layer M3 may be referred to as a first wiring layer, and the wiring layer M2 may be referred to as a second wiring layer below the first wiring layer. The shielded lines 512 and the signal lines 514 in the first wiring layer may be referred to as first shielded lines and first signal lines, and this may mean a plurality of first shielded lines and first shielded lines formed in an alternate arrangement across the first wiring layer. signal line. Similarly, the shielded line 516 and the signal line 518 of the second wiring layer are referred to as a second shielded line and a second signal line, and this may mean a plurality of second shielded lines and first shielded lines formed in an alternate arrangement across the second wiring layer. Two signal lines.

The first shielded wire 512 has a first segment 520 and a second segment 522 laterally offset from the first segment. The first segment 520 and the second segment 522 are connected to each other by a link segment 524 . Linking segment 524 may be arranged to connect one end of first segment 520 with one end of second segment 522 . The first segment 520 may extend from one end of the link segment 524 . The second segment 522 may be relatively elongated from the other end of the link segment 524 relative to the first segment 520 . Similarly, the first signal line 514 has a first segment 526, a second segment 528 laterally offset from the first segment, and a link segment 530 interconnecting the first segment 526 and the second segment 528 to each other. Linking segment 530 may be arranged to connect one end of first segment 526 with one end of second segment 528 . The first segment 526 can extend from one end of the link segment 530 . The second segment 528 may be elongated from the other end of the link segment 530 opposite to the first segment 526 .

The second shield line and the second signal line in the second wiring layer M2 have segments similar to those of the first wiring layer M3. However, for simplicity of explanation, the segments of the second shielded line and the second signal line will be referred to as third and fourth segments to distinguish them from the first and fourth segments of the first shielded line 512 and the first signal line 514. The two sections are separated. Accordingly, the second shielded wire 516 has a third segment 532 and a fourth segment 534 laterally offset from the third segment. The third segment 532 and the fourth segment 534 are connected to each other by a link segment 536 . Linking segment 536 may be arranged to connect one end of third segment 532 with one end of fourth segment 534 . The third segment 532 may extend from one end of the link segment 536 . The fourth segment 534 may be relatively elongated from the other end of the link segment 536 relative to the third segment 532 . Similarly, the first signal line 518 has a third segment 538, a fourth segment 540 laterally offset from the first segment, and a link segment 542 interconnecting the third segment 538 and the fourth segment 540 with each other. Linking segment 542 may be arranged to connect one end of third segment 538 with one end of fourth segment 540 . The third segment 538 can extend from one end of the link segment 542 . The fourth segment 540 is elongated from the other end of the link segment 542 opposite to the third segment 538 . In some embodiments, link segments 524 and 530 in the first wiring layer M3 may be referred to as first link segments, and link segments 536 and 542 in the second wiring layer M2 may be referred to as second link segments, such that Link segments in different routing layers can be distinguished from each other.

A shaft system is provided near the top view in FIG. 2 . The axis system shows a first axis 503 and a second axis 505 extending orthogonally with respect to the first axis. The first and second segments 520 , 522 , 526 and 528 mainly extend along a first direction corresponding to the axis 503 , and the link segments 524 and 530 mainly extend along a second direction corresponding to the axis 505 . A segment is indicated to extend "primarily" along the indicated direction to indicate that the entire course of the segment is along the indicated direction even if the segment is wavy or otherwise non-straight. In some embodiments, the segments may be substantially straight, where the term "substantially straight" means that the segments are straight within reasonable tolerances of fabrication and measurement.

Third and fourth segments 532 , 534 , 538 , and 540 also extend primarily along a first direction corresponding to axis 503 , and in the illustrated embodiment link segments 536 and 542 extend primarily along second axis 505 .

In the illustrated embodiment, the link segment 524 extends substantially orthogonally to the first segment 520 and the second segment 522 of the shield line 512, and the link segment 530 extends substantially orthogonally to the first segment 526 and the second segment of the signal line 514. 528 , the link segment 536 extends substantially perpendicularly to the third segment 532 and the fourth segment 534 of the second shielded line 516 , and the link segment 542 extends substantially orthogonally to the segments 538 and 540 of the second signal line 518 . The term "substantially orthogonal" means that the linking segments run orthogonally to the other indicated segments within reasonable tolerances of fabrication and measurement. In other embodiments, one or both of the linking segments may extend at an angle other than normal relative to the main direction of the segments interconnected by this linking segment.

An advantage of the architecture of FIG. 2 is that the offset (ie, bend) provided in the signal and shield lines enables the area of the shield line from the upper wiring layer M3 to vertically overlap the area of the shield line of the lower wiring layer M2. Specifically, the shielded line 512 of the upper wiring layer vertically overlaps the region of the shielded line 516 of the lower wiring layer within the illustrated overlap region 544; wherein the illustrated fourth segment 534 of the second shielded line 516 extends to the first shielded line 512 below the first segment 520 .

A vertical interconnect 546 is disposed within the overlap region 544 to electrically couple the shielded lines 516 and 512 to each other. Vertical interconnects 546 are illustrated in the top view of FIG. 2 with dashed lines (dashed lines) to indicate that the interconnects are located below line 512 . A vertical interconnect may extend substantially vertically, where the term "substantially vertical" means that the interconnect is vertical within reasonable tolerances of fabrication and measurement.

The illustrated embodiment shows two vertical interconnects within overlapping region 544 . In other embodiments, only a single interconnect may be provided in the overlapping area, or more than two interconnects may be provided in the overlapping area. Furthermore, while interconnects 546 are square in the top view of FIG. 2 , in other embodiments, interconnects may have other shapes including, for example, rectangular, circular, oval, etc. FIG.

An alternative description of the assembly 510 of FIGS. 2-2C follows. The first shielded wire 512 in the upper wiring layer can be considered to have a first portion 548 extending in a first direction of the axis 503, a second portion 550 extending in a second direction (eg, the direction of the axis 505), and The third portion 552 extending in the first direction. The second portion 550 interconnects the first portion 548 with the third portion 552 . The first signal line 514 in the upper wiring layer is adjacent to the first shielding line and has a fourth portion 554 , a fifth portion 556 and a sixth portion 558 . The fourth, fifth and sixth sections (554, 556 and 558) are substantially parallel to the third, second and first sections (552, 550 and 548), respectively. The term "substantially parallel" means parallel within reasonable tolerances of fabrication and measurement.

Continuing with the alternative description of the assembly 510, the second shielded wire 516 in the lower wiring layer includes a seventh portion 560 and an eighth portion 562; wherein the seventh portion 560 is substantially vertically aligned with the third portion 552 of the first shielded wire 512 , the eighth portion 562 is substantially vertically aligned with the fourth portion 554 of the first signal line 514 . The second shielded wire 516 also includes a ninth portion 564 . The ninth section interconnects the seventh section 560 with the eighth section 562 . The seventh portion 560 extends continuously from below the third portion 552 of the first shielding line 512 to below the sixth portion 558 of the first signal line 514; wherein the seventh portion 560 is substantially perpendicular to the third portion 552 of the first shielding line 512 alignment.

Continuing further with the alternative description of the assembly 510, the overlapping region 544 extends through the third portion 552 of the first shielded wire 512 and the seventh portion 560 of the second shielded wire 516, and a vertical interconnect 546 connects the third portion 552 to the third portion 552 of the second shielded wire 516. The seven sections 560 are electrically connected.

Figure 3 shows an enlarged view of area "3" of assembly 510 of Figure 2, and will be used to describe some dimensional relationships within this assembly.

The shielded lines 512 may be considered as individual first shielded lines representing the plurality of shielded lines within the upper wiring layer, and the signal lines 514 may be considered as individual first signal lines representing the plurality of signal lines within the upper wiring layer. Similarly, the second shielded lines 516 can be considered as individual second shielded lines representing the plurality of second shielded lines within the lower wiring layer, and the second signal lines 518 can be considered to represent the plurality of second shielded lines within the lower wiring layer. Individual second signal lines of the two signal lines.

The first signal line 514 is immediately adjacent to the first shielding line 512, wherein the term "immediately adjacent" indicates that there are no other signal lines between the signal line 514 and the shielding line 512 in the upper wiring layer (that is, the signal line 514 is the closest to the shielding line in the upper wiring layer). signal line of line 512).

The first shielded wire 512 has a first segment 520 of the first shielded wire, a second segment 522 of the first shielded wire, and a link segment 524 between the first segment 520 and the second segment 522 . Link segment 524 may be referred to as a first shielded wire link segment.

The signal line 514 includes a first section 526 of the first signal line, a second section 528 of the first signal line, and a link section 530 between the first section 526 and the second section 528 . The link section 530 may be referred to as a first signal line link section.

The first shielded link segment 524 is offset from the first signal link segment 530 by a first distance D ₁ along the first direction of the axis 503 .

The second shielded line 516 includes a third section 532 located below the area of the first section 526 of the first signal line. The second shielded line 516 also has a fourth segment 534 that extends below the area of the second segment 528 of the signal line, and this also extends below the area of the first segment 520 of the first shielded line. The second shielded wire link segment 536 connects the third segment 532 with the fourth segment 534 .

The vertical interconnect 546 extends between the first shielded line first segment 520 and the second shielded line fourth segment 534 to electrically couple the first shielded line 512 and the second shielded line 516 to each other (ie, connect the upper wiring layer The shield wire 512 is electrically coupled with the shield wire 516 of the lower wiring layer).

The second shielded link segment 536 is offset from the first signal link segment 530 along the first direction of the axis 503 by a second distance D ₂ .

The _second distance D2 is greater than the _first distance D1, and in some embodiments may be at least twice the first distance.

FIG. 3 also shows that the first shielding line 512 and the first signal line 514 are spaced apart from each other by a third distance interval D ₃ corresponding to the pitch, and that the adjacent corners of the shielding line 512 and the signal line 514 are separated by a fourth distance D ₄ , which The fourth distance extends along a direction corresponding to axis 507 . The direction of axis 507 is midway between the directions of axes 503 and 505, and in some embodiments may be approximately 45° (ie, midway between axes 503 and 505).

_In some embodiments, a D4 shift can be considered equal to a _D3 shift combined with _a D1 shift.

In some embodiments, the illustrated link segments (eg, 524, 530, and 536) can be considered to define steps or bridge paths along the various shielded and signal lines.

The wiring layer M2 of FIGS. 2 and 3 may be over another wiring layer similar to layer M1 of FIG. 1 . FIGS. 4 and 4A show the area of the assembly 510 below the area illustrated in FIGS. 2 and 3, and specifically show the third wiring layer M1 below the second wiring layer M2 (layer M3 is not shown in FIG. and not shown in 4A). The illustrated region of wiring layer M2 of FIG. 4 has a second shielded line 516 between a pair of second lines 518 .

The wiring layer M1 includes a signal line 566 between a pair of shield lines 568 . The signal line and the shielded line in the third wiring layer M1 may be referred to as a third signal line and a third shielded line in order to distinguish them from the second shielded line and the second signal line in the second wiring layer M2, and It is distinguished from the first shielding line and the first signal line in the first wiring layer M3 ( FIG. 2 ). In the illustrated embodiment, the shielding lines and signal lines in the wiring layer M1 mainly extend along the direction of the axis 505, or in other words, are substantially orthogonal to the third section 532 and the fourth section of the second shielding line 516. 534 extension.

The third shielded line 568 is electrically coupled to the third segment 532 and the fourth segment 534 of the second shielded line 516 through a vertical interconnect 570 (or alternatively, is considered to be electrically coupled to the seventh segment of the second shielded line through a vertical interconnect 570 ). part 560 and eighth part 562). In some embodiments, the vertical interconnects 546 (ie, interconnects for connecting the shield lines in the first wiring layer M3 to the shield lines in the second wiring layer M2) may be referred to as the first set of interconnects, And interconnects 570 may be referred to as a second set of interconnects to distinguish interconnects 570 from interconnects 546 . Interconnects 546 and 570 are shown as squares and circles in the top view of FIG. 4 in order to provide a clear visual distinction between interconnects 546 and 570 . In practice, interconnects 46 and 70 may be the same shape as each other, or may be different shapes; and may be any suitable shape, including, for example, square, rectangular, circular, oval, and the like. Vertical interconnect 570 is illustrated in dashed (dashed) lines in the top view of FIG. Location of interconnect 546 (interconnect 546 may or may not be visible in the view of FIG. 4 depending on the particular architecture of interconnect 546 and whether the location chosen for the view of FIG. 4 is a cross-section through interconnect 546) .

5-8 further illustrate assembly 510 including wiring layers Ml, M2, and M3. FIG. 5 is an exploded view showing wiring layers stacked on top of each other; while FIGS. 6 to 8 show each of the individual wiring layers M1 , M2 and M3 individually. The wiring in layer M3 is shown to be slightly thicker than the wiring in layers M2 and Ml. In fact, depending on the application, the wiring within layers M1 to M3 may all be of the same thickness, or some wiring may have a different thickness relative to other wiring.

Assembly 510 of FIGS. 5-8 may be considered to include connection region 572 encompassing interconnect 546 and, more specifically, the location where portions of shielded lines 512 of layer M3 vertically overlap portions of shielded lines 516 of layer M2. The linking areas of shield and signal lines within layers M2 and M3 are within connection area 572 (such linking areas are as described above with reference to FIG. 2 and may alternatively be referred to as bend areas, bridge areas, etc.).

The connection area can be considered to include a first boundary 571 and a second boundary 573 . The first shielding region 574 extends outward from the connection region 572 along the direction of the axis 505 , and the second shielding region 576 extends outward from the connection region 572 along the axis direction 503 . The signal line 514 of the layer M3 vertically overlaps the shielding line 516 of the layer M2 in the first shielding area 574 and the second shielding area 576; Lines 518 overlap vertically.

In the embodiments of FIGS. 5-8, all shield lines within wiring layers M3, M2, and M1 are electrically connected to Vss (voltage Vss may be any suitable voltage, and may be ground or a negative supply voltage in some embodiments) . Together, the various shield lines from wiring layers M3, M2, and M1 can form a three-dimensional grid 578 of the type shown in FIG. 9, with a uniform voltage throughout the grid. Specifically, the mesh of FIG. 9 includes a first shielded wire 512 of the upper wiring layer M3, a second shielded wire 516 of the middle wiring layer M2, and a third shielded wire 568 of the lower wiring layer M1. Shielded lines 512, 516, and 568 are illustrated as lines of different thicknesses so they can be distinguished from each other in the diagram of FIG. 9 . In practice, the shielded wires may all have substantially the same thickness as each other (or in some embodiments, some shielded wires may have a different thickness than others if the shielded wires are appropriate for a particular application). The area where the shielded lines from layer M3 connect with the shielded lines from layer M2 is shown as overlap area 544, and this would include vertical interconnects 546 (shown in Figures 5-8, but not in Figure 9).

One aspect of the embodiment of FIG. 9 is that each of the first shielded lines 512 of the top wiring layer M3 is directly connected to a pair of second shielded lines 516 from the middle wiring layer M2; and conversely, the second shielded lines of the middle wiring layer Each of 516 is directly connected to a pair of first shielded wires 512 from the top wiring layer. Shielded lines 512 and 516 include bridging regions (ie, linking regions) 524 and 536 as previously described.

9 shows both of the first shielded wires 512 labeled 512a and 512b to distinguish them from the other shielded wires in the first shielded wires, and shows both of the second shielded wires 516 labeled 516a and 516b as well. Distinguish it from the other shielded wires in the second shielded wire. The first shielding line 512a extends mainly along a first direction corresponding to the axis 503 and along two first paths 580 and 582 that are laterally offset relative to each other. Similarly, the second shielded line 516b extends mainly along the first direction of the axis 503 and along two second paths 590 and 592 that are laterally offset relative to each other. Except for first paths 580 and 582 having overlapping region 544, first shielded line 512a is primarily laterally offset from second shielded line 516, with portions of first shielded line 512a overlapping portions of second shielded lines 516a and 516b. The particular overlapping regions where portions of the first shielded line 512a overlap with portions of the second shielded lines 516a and 516b are labeled 584 and 586 .

Notably, the path 580 of a shielded wire 512a overlaps a second shielded wire 516a, while the path 582 of the same first shielded wire 512a overlaps a different second shielded wire 516b. In a similar manner, the second shielded line 516b is connected to two different first shielded lines 512a and 512b. A vertical interconnect 546 (not shown in FIG. 9 ) is disposed within the overlapping region 544 to connect the first shielded line 512 and the second shielded line 516 together.

The shield line 568 of the bottom wiring layer M1 may be connected to the shield line 516 of the middle wiring layer M2 by a vertical contact 570 (shown in FIG. 9 ) of the type described above with reference to FIG. 4 .

The interweaving interconnects between the first, second and third wiring layers within grid 578 enable a consistent voltage to be maintained throughout all shielded wires tangled within this grid. This may alleviate or prevent the problems described above in the "Background of the Invention" section of this disclosure.

5-9 illustrate embodiments in which all shield lines are held at a common voltage (illustrated as Vss, but in other embodiments it may be a common voltage other than Vss). In some embodiments, shielded wires may be subdivided between groups held at different voltages relative to each other. For example, in some embodiments, some shielded lines may be held at Vss while other shielded lines are held at Vdd. An exemplary embodiment in which some shielded lines are electrically connected to Vss and other shielded lines are electrically connected to Vdd is described with reference to FIGS. 10 to 14 .

The wiring layers M1 , M2 and M3 of assembly 10 are illustrated in FIGS. 10-13 . FIG. 10 is an exploded view showing wiring layers stacked on top of each other; while FIGS. 11 to 13 show each of the individual wiring layers M1, M2, and M3 individually.

The general architecture of FIGS. 10-13 is similar to that described above for FIGS. 5-8, except that additional complexity is introduced such that the shielded lines within the various layers M1-M3 may include some shielded lines electrically connected to Vdd and Other shielded wires are electrically connected to Vss.

The various shield lines from wiring layers M3, M2, and M1 together can form a pair of three-dimensional meshes similar to the meshes shown in FIG. 9 . One of these grids is electrically connected to Vss and the other is electrically connected to Vdd. Figure 14 shows a three-dimensional mesh 88 electrically connected to Vss, and a similar mesh (not shown) would be electrically connected to Vdd.

The assembly discussed above can be incorporated into an integrated circuit supported by an underlying semiconductor substrate (not shown). The substrate may, for example, comprise, consist essentially of, or consist of single crystal silicon. The term "semiconductor substrate" refers to any structure comprising semiconductor material, including but not limited to bulk semiconductor material such as semiconductor wafers (alone or in combination with other materials) and layers of semiconductor material (alone or in combination with other materials). ). The term "substrate" refers to any supporting structure, including but not limited to the semiconductor substrates described above.

In some embodiments, the present invention includes an architecture that reduces the distance between interconnects that couple shielded lines of an upper wiring layer (eg, M3) to shielded lines of a lower wiring layer (eg, M2) such that via The bypass spacing can be reduced. Signal lines within a given via bypass pitch can be coupled to the common bus. Thus, reducing the via bypass pitch can result in a reduced number of signal lines associated with each bus, and thus can result in reduced resistance across the signal lines and associated bus lines.

15A and 15B show an assembly 510 comprising the arrangement of FIG. 5 , but illustrated with respect to FIG. 5 in an alternative manner. Assembly 510 is shown in a top view in FIG. 15A where the wires of the wiring layer are severely compressed. The extended region of the top wiring layer M3 is shown in a cross-sectional side view in FIG. 15B to help the reader understand the top view of FIG. 15A . The approximate location of the illustrated portion of FIG. 5 is schematically illustrated in FIG. 15A as corresponding to the area labeled "FIG. 5". Connection region 572 is schematically illustrated as having a line through the top view of FIG. 15A .

A continuing goal of semiconductor fabrication is to increase circuit density (ie, increase integration). A problem with the architectures of FIGS. 5, 15A, and 15B is the interconnection (FIG. 5 546 ) of a given wiring layer (eg, shielding line 512 of wiring layer M3 shown in FIGS. 5 and 6 ) may have a large distance. This problem is illustrated in the top view of FIG. 15A with arrows 320 indicating the spacing between interconnects (ie, via bypass spacing). Arrow 320 is open to indicate that the full via bypass spacing is not visible in the top view of FIG. 15A .

A signal line (eg, signal line 514 of wiring layer M3 (shown in FIG. 6 ), signal line 518 of wiring layer M2 (shown in FIG. 7 ), etc.) is coupled to an associated bus (ie, an electrical path), and The number of signal lines coupled to an individual bus can be related to the via bypass pitch.

As circuit density increases, the need for shielded wires may increase (eg, increased voltage along the shielded wires and/or increased current along the shielded wires). Additionally, an increase in signal line density may result in increased resistance along the signal lines and associated busses. Therefore, it would be desirable to develop new architectures that reduce the distance between the interconnects that couple the shielded lines of one wiring layer to the shielded lines of another wiring layer, and reduce the resistance along signal lines and associated bus lines.

In some embodiments, one or more redundant (dummy) channels are provided within the shield/signal line circuits of the wiring layers (eg, M2 and M3 ) so that via bypass pitch can be reduced. In these embodiments, the bus can be considered to be arranged between subgroups by providing one or more redundant (dummy) channels within the signal/shield circuit. For example, the number of buses may be denoted as "n", and the buses may be arranged into "m" subgroups; each of the "m" subgroups has "k" signal lines. In some embodiments, the via bypass pitch on the shield line may be 1/m compared to architectures where the bus lines are not merged into subgroups.

As indicated above, the term "virtual" may be used to describe redundant channels, which term indicates that redundant channels are distinct from other channels including shielding/signal lines. In some cases, the label "dummy" is used to identify a structure that has no function other than as a spacer (ie, not used as a wiring or component of an integrated circuit). In the present case, that is usually not the case. Conversely, a "dummy" structure may contain circuitry (e.g., shielded wires), and the label "dummy" may be used to indicate that structures within a wiring layer (e.g., shielded wires) have a different configuration and/or use other similar structures.

Virtual (ie, redundant) structures may be configured as "channels," or may correspond to other suitable structures and regions.

Example calculations relative to a configuration with 288 signal lines indicate that a single group (i.e., only one subgroup) results in a worst resistance value of 40.95 ohms, two subgroups result in a worst resistance value of 21.85 ohms, and eight subgroups result in a worst resistance value of 21.85 ohms. This resulted in a worst resistance value of 12.23 ohms, and 16 subgroups resulted in a worst resistance value of 6.73 ohms. Therefore, the arrangement of signal lines between subgroups can result in substantial improvement (specifically, a reduction in resistance). Calculated resistance values are provided to aid the reader in understanding the invention, and are not intended to limit the claims that follow; unless the extent, if any, of such values are expressly recited in the claims.

Figures 16A and 16B show an assembly 10 similar to assembly 510 of Figures 15A and 15B. This assembly may include wiring layers M1 , M2 and M3 (similar to those of FIG. 5 ) stacked one on top of the other. FIG. 16A shows a top view with heavily compressed lines of top wiring layer M3 (similar to the top view of FIG. 15A ), and FIG. 16B shows an expanded area of top wiring layer M3 in a cross-sectional side view. The wiring layer M3 of FIG. 16B includes the shielding line 12 and the signal line 14 , which are similar to the shielding line 512 and the signal line 514 of FIG. 15B . In addition, wiring layer M3 of FIGS. 16A and 16B includes redundant (dummy) vias 15 that separate the shield/signal lines of wiring layer M3 into subgroups 16a and 16b.

Connection area 18a is associated with subgroup 16a, and connection area 18b is associated with subgroup 16b; and these connection areas 18a/18b are schematically illustrated with lines passing through the top view of Figure 16A. Connection regions 18a/18b are similar to connection region 372 of FIG. 15A. However, the connection region 18a/18b pitch is reduced relative to the connection region 372 of FIG. 15A, which reduces the via bypass pitch. Specifically, arrow 21 is provided in FIG. 16A to schematically illustrate via bypass pitch. This via bypass pitch 21 is significantly reduced (and may be reduced by approximately half in some embodiments) compared to the via bypass pitch 320 of the assembly 510 of FIG. 15A . The reduction in via bypass pitch can significantly reduce the resistance along the signal lines and associated bus lines of assembly 10 of FIG. 16A as compared to assembly 510 of FIG. 15A .

17 and 18 illustrate alternative views of the assembly 10 of FIG. 16 ; wherein the view of FIG. 18 is an expanded area of FIG. 17 .

Figures 17 and 18 show wiring layer M3 overlying wiring layer M2; and show interconnects 20 and 22, respectively, similar to interconnects 546 and 570 described above with reference to Figure 5 . Specifically, the interconnection 20 vertically connects the shielding line of the wiring layer M2 and the shielding line of the wiring layer M3, and the interconnection 22 vertically connects the shielding line of the wiring layer M2 and the shielding line of the wiring layer M1 (in FIGS. 17 and 18 not shown). Interconnects 20 and 22 are shown as square and circular features, respectively, so that interconnect 20 can be easily distinguished from interconnect 22 in the illustration, although in other applications interconnects 20 and 22 may have other shapes; and The shapes may be the same as each other, or different shapes relative to each other.

The wiring layers M2 and M3 are shown in dashed and solid line views, respectively, in FIGS. 17 and 18 so that they can be distinguished from each other.

18 shows a table that provides a pair of lines (Line 1 and Line 2) across the assembly 10 with the state (configuration) of the materials in the M2 and M3 wiring layers at the location of each line below the diagram of the assembly 10. described in. The signal line is denoted as "Sig" and the shielded line is denoted as "Vss". The term Vss was chosen because it is common for the shield lines of wiring layers M3, M2, and M1 to be electrically connected to Vss (it should be understood that voltage Vss may be any suitable voltage, and may be ground or a negative supply voltage in some embodiments). In some embodiments, the shield line may be coupled to a voltage other than Vss.

The table of FIG. 18 shows that the location of redundant channel 15 along line 1 is different from other locations of wiring layers M2/M3. Specifically, the redundant channel 15 includes the space below the signal line of the wiring layer M3 and includes the space above the shielding line of the wiring layer M2. Instead, redundant channel 15 has the same configuration as other locations of wiring layer M2/M3 at the location of line 2, and simply includes the Vss line of M3 on the signal line of M2, and the Vss line of M3 above the Vss of M2 signal line. Although the term "space" is used to describe locations along line 1, it should be understood that locations indicated as "spaces" may include insulating materials (eg, silicon nitride, silicon dioxide, etc.).

Figure 19 compares assembly 510 (described above with reference to Figure 15A) with example assemblies 10, 10a, and 10b of other embodiments. Assembly 10 is similar to the assembly described above with reference to Figure 16A. Assemblies 10a and 10b incorporate additional redundant channels 15 to thereby form additional subgroups. Specifically, assembly 10 has two subgroups 16a and 16b; assembly 10a has four subgroups 16a, 16b, 16c, and 16d; assembly 10b has eight subgroups 16a, 16b, 16c, 16d, 16e, 16f, 16g and 16h. Example resistances on the signal lines and associated bus lines within the subgroups were estimated to be approximately 40.95 ohms for assembly 300; 21.85 ohms for assembly 10; 12.23 ohms for assembly 10a; and 6.73 ohms for assembly 10b. Accordingly, arranging signal lines into subgroups within assemblies 10, 10a, and 10b can result in substantial improvements (specifically, reducing resistance across signal lines and associated busses).

FIG. 20 shows a top view of a pair of example assemblies 10c and 1Od that may be used in some embodiments. The assembly 10c has connection regions 18a and 18b which are mirrored with respect to a first plane 5 passing through the middle of the assembly and also relative to a first plane 5 passing through the middle of the assembly and orthogonal to the first plane 5. The two planes 7 are mirror images. Connection region 18b is shown with a thicker line than connection region 18a so that connection regions 18a and 18b are distinguishable from each other. Region A is identified in assembly 10c, and this region is discussed in more detail below with reference to FIGS. 21-27.

The assembly 10d has connection regions 18a and 18b which are mirrored with respect to a plane 5 passing through the middle of the assembly. Regions B and B' are identified in assembly 10d, and such regions will be discussed in more detail below with reference to FIGS. 28-36.

21-24 illustrate assembly 10c, and show wiring layers Ml, M2, and M3. FIG. 21 is an exploded view showing wiring layers stacked on top of each other; while FIGS. 22 to 24 show each of the individual wiring layers M1, M2, and M3 individually.

Referring to FIG. 22 , the wiring layer M1 includes signal lines 30 alternating with shield lines 32 . The signal wire and the shield wire are separated from each other by insulating material 34 . Shield line 32 is shown supplied with (ie, coupled to) a fixed voltage identified as Vss, but may be supplied with any suitable voltage.

Signal lines 30 and shield lines 32 may comprise any suitable conductive composition, for example, various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, etc.) , metal carbide, etc.) and/or one or more of conductively doped semiconductor materials (eg, conductively doped silicon, conductively doped germanium, etc.). The conductive material of signal line 30 and shield line 32 may be homogeneous, or may include two or more discrete compositions. The conductive material of the shielding line 32 may be the same as that of the signal line 30, or may be different from that of the signal line.

Insulating material 34 can comprise any suitable composition, and in some embodiments can comprise consisting essentially of one or both of silicon dioxide and silicon nitride, or consisting of one of silicon dioxide and silicon nitride. or both. The insulating material 34 may be homogeneous, or may comprise two discrete compositions of two or more.

Interconnects 22 (only some of which are labeled) are shown along shielded lines 32, where such interconnects 22 are used to vertically connect shielded lines 32 of wiring layer M1 with shielded lines 42 of wiring layer M2 (as shown in FIG. 23 ). .

Referring to FIG. 23 , the wiring layer M2 includes signal lines 40 alternating with shield lines 42 . The signal wire and the shield wire are separated from each other by insulating material 34 . Shield line 42 is shown coupled to a fixed voltage identified as Vss, but any suitable voltage may be coupled.

Signal lines 40 and shield lines 42 may comprise any suitable conductive composition, such as various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, etc.) , metal carbide, etc.) and/or one or more of conductively doped semiconductor materials (eg, conductively doped silicon, conductively doped germanium, etc.). The conductive material of signal line 40 and shield line 42 may be homogeneous, or may comprise two or more discrete compositions. The conductive material of the shielding line 42 may be the same as that of the signal line 40, or may be different from that of the signal line. Additionally, the threads 40/42 of layer M2 may be of the same composition as one or both of the threads 30/32 of layer M1, or may be of a different composition than one or both of the threads 30/32 of layer M1 thing.

Interconnects 22 (only some of which are labeled) are shown along shielded lines 42, where such interconnects 22 are used to vertically connect shielded lines 42 of wiring layer M2 with shielded lines 32 of wiring layer M1 (as shown in FIG. 22 ). . Interconnects 20 (only some of which are labeled) are shown along shielded lines 42, where such interconnects 20 are used to vertically connect shielded lines 42 of wiring layer M2 with shielded lines 12 of wiring layer M3 (as shown in FIG. 24 ). . Interconnects 20 are shown in a paired arrangement (ie, two interconnects 20 in each location where shield line 42 of wiring layer M2 connects with shield line 12 of wiring layer M3). In other embodiments, only a single interconnect 20 may be located in at least some of these locations; and in some embodiments, more than two interconnects 20 may be located in at least some of these locations.

Referring to FIG. 24 , the wiring layer M3 includes signal lines 14 alternating with shield lines 12 . The signal wire and the shield wire are separated from each other by insulating material 34 . Shielded line 12 is shown coupled to a fixed voltage identified as Vss, but any suitable voltage may be coupled.

Signal lines 14 and shield lines 12 may comprise any suitable conductive composition, for example, various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, etc.) , metal carbide, etc.) and/or one or more of conductively doped semiconductor materials (eg, conductively doped silicon, conductively doped germanium, etc.). The conductive material of signal line 14 and shield line 12 may be homogeneous, or may comprise two or more discrete compositions. The conductive material of the shield line 12 may be the same as that of the signal line 14, or may be different from that of the signal line. Additionally, wires 12/14 of wiring layer M3 may be of the same composition as one or more of wires 30/32 and 40/42 of wiring layers M1 and M2, or may be of the same composition as wire 30 of wiring layers M1 and M2. One or more different combinations of /32 and 40/42.

Interconnects 20 (only some of which are labeled) are shown along shielded lines 12, wherein such interconnects 20 are utilized to vertically connect shielded lines 12 of wiring layer M3 with shielded lines 42 of wiring layer M2 (as shown in FIG. 23 ). ). Coverage areas 18a and 18b are schematically indicated in FIGS. 23 and 24, and this corresponds to the area where interconnect 20 vertically connects shield line 12 of wiring layer M3 with shield line 42 of wiring layer M2.

Region A is schematically illustrated with respect to wiring layers M2 and M3 of FIGS. 23 and 24 , and this region includes redundant (dummy) regions (eg, channels). One of the shielded lines 42 in FIG. 23 is marked with a mark 42a to distinguish this shielded line from other shielded lines, and the redundant area of the wiring layer M2 includes a widening structure 45 along the shielded line 42a. One of the shielded lines 12 in FIG. 24 is marked with a mark 12a to distinguish this shielded line from other shielded lines, and the redundant area of the wiring layer M3 includes a widening structure 17 along the shielded line 12a.

In some embodiments, the wiring layers M2 and M3 of FIGS. 23 and 24 may be referred to as a lower wiring layer and an upper wiring layer, respectively; and may be considered to include the illustrated first wiring track, second wiring track, third wiring track and a fourth routing track (labeled as first track, second track, third track and fourth track in FIGS. 23 and 24 ). The first wiring track, the second wiring track, the third wiring track and the fourth wiring track of the upper wiring layer M3 directly cover the first wiring track, the second wiring track, the third wiring track and the fourth wiring track of the lower wiring layer M2 , and in the redundant area (ie, redundant channel).

The first routing track, the second routing track, the third routing track, and the fourth routing track extend in a first direction along the x-axis (where the x-axis is shown adjacent to the portion of assembly 10c along FIGS. 23 and 24 . ), and extend parallel to each other (or at least substantially parallel to each other, where the term "substantially parallel" means parallel within reasonable tolerances of fabrication and measurement). The first routing track and the third routing track sandwich the second routing track therebetween; and the second routing track and the fourth routing track sandwich the third routing track therebetween.

In some embodiments, it may be considered that the lower wiring layer M2 includes a first wiring corresponding to the wiring of the shielding line 42a. The first routing can be considered to have a first portion 50 extending along the second routing track, a second portion 52 extending along the first routing track, and a third portion 54 extending along the third routing track. The first portion 50 may be considered to include a first side 51 and a second side 53 opposite the first side. The second portion 52 may be considered offset from the first side 51 of the first portion 50 by a first offset region 56 and the third portion 54 may be considered offset from the second side 53 by a second offset region 58 . In the illustrated embodiment, the first portion 50, the second portion 52, and the third portion 54 extend along the x-axis direction. The second portion 52 is offset from the second wiring track by protrusions 55 and 57 extending along the y-axis. The third portion 54 is offset from the second wiring track by protrusions 59 and 61 extending along the y-axis. The first portion 50, the second portion 52, and the third portion 54 can be considered to extend along the first direction (the direction of the x-axis); and the protrusions 55, 57, 59, and 61 can be considered to extend along the second direction (the direction of the y-axis). direction) to extend. In the illustrated embodiment, the second direction is orthogonal to the first direction. In other embodiments, the first and second directions may intersect each other rather than being orthogonal to each other.

It can be considered that the upper wiring layer M3 includes the second wiring (ie, wiring of the shielded wire 12a). The second wiring 12a is connected to the first wiring 42a through interconnects 20a and 20b (where interconnects 20a and 20b are the same as the other interconnects 20 but labeled 20a and 20b so that they can be identified separately from the other interconnects). In some embodiments, the second routing 12a can be considered to include a fourth portion 60 extending along the third routing track, and include a fifth portion 62 extending along the second routing track. The third portion 54 of the first wiring 42a (FIG. 23) is electrically coupled to the fourth portion 60 of the second wiring 12a (FIG. 24) through the interconnection 20a, and the first portion 50 of the first wiring 42a (FIG. 23) is through the interconnection 20b. It is electrically coupled with the fifth portion 62 of the second wiring 12a ( FIG. 24 ). Figure 26 shows the coverage of the extended area of Figures 23 and 24;

25 shows a cross-section along line 25-25 of FIGS. 23 and 24, and shows interconnects 20a/20b extending through insulating material 34 to connect shielded wire 12a of upper wiring layer M3 to shielded wire of lower wiring layer M2. 42a is electrically coupled. Although the illustrated embodiment shows two contact plugs corresponding to interconnect 20a/20b, in other embodiments there may only be a single contact plug, and in other embodiments there may be more than two contact plugs.

In some embodiments, the first wiring 42a of the lower wiring layer M2 may be considered to include the first portion 50, the second portion 52, and the third portion 54 described above; part (wherein this fourth part couples the first part 50 with the second part 52), and the fifth part corresponds to the protrusion 59 (wherein this fifth part couples the first part 50 with the third part 54). In these embodiments, the second wiring 12a of the upper wiring layer M3 can be considered to include a portion 60 as a sixth portion extending along the third wiring track, and a portion 60 as a seventh portion extending along the second wiring track. Section 62. The second wiring 12a also includes an eighth portion 64 extending along the fourth wiring track, a ninth portion 66 extending along the y-axis and coupling the sixth portion 60 with the seventh portion 62, and extending along the y-axis and The sixth part 60 is coupled to the tenth part 68 of the eighth part 64 . The contact plug 20a of Figures 23 and 24 can be considered to penetrate the insulating layer corresponding to the insulating material 34, and couple the third portion 54 of the first wiring 42a with the sixth portion 60 of the second wiring 12a; and similarly, contact The plug 20b may be considered to penetrate the insulating layer corresponding to the insulating material 34 and couple the first portion 50 of the first wiring 42a with the seventh portion 62 of the second wiring 12a.

In some embodiments, it can be considered that the lower wiring layer M2 further includes a third wiring 40a (that is, one of the signal lines) electrically disconnected from the first wiring 42a; it has an eleventh wiring along the third wiring track. portion 70 , a twelfth portion 72 along the fourth routing track, and a thirteenth portion 71 extending along the y-axis and coupling the eleventh portion 70 with the twelfth portion 72 .

In some embodiments, the upper wiring layer M3 can be considered to further include a fourth wiring 14a (ie, one of the signal lines) electrically disconnected from the first wiring 12a; it has a tenth wiring along the second wiring track. Four sections 80 , a fifteenth section 82 along the first routing track, and a sixteenth section 83 extending along the y-axis and coupling the fourteenth section 80 with the fifteenth section 82 .

In some embodiments, the shielded wire 12a of the upper wiring layer M3 may be referred to as a first shielded wire, and the other shielded wire 12b may be referred to as a second shielded wire. The second shielded wire 12b has a portion 90 extending along the first wiring track and vertically overlapping the second portion 52 of the shielded wire 42a of the lower wiring layer M2. Portion 90 of shielded wire 12b is coupled to portion 52 of shielded wire 42a by an interconnect labeled 20c (shown in FIGS. 23 and 24, and also shown in FIG. 26).

In some embodiments, the first portion 50, the second portion 52, and the third portion 54 of the shielded line 42a in the wiring layer M2 and the protrusions 55, 57, 59, and 61 of the shielded line 42a may be considered to include The widening structure 45 (as shown in FIG. 23 ). 27A-C illustrate some example embodiments of such a widening structure 45 . FIG. 27A shows the widening structure 45 of FIG. 23 . This has a protrusion 59 (which in some embodiments may be referred to as the fourth portion of shielded wire 42a) in the same direction as protrusion 55 (which in some embodiments may be referred to as the fifth portion). extended, but completely misaligned (ie, displaced along the x-axis) relative to protrusion 55 . This also has a protrusion 61 which extends in the same direction as protrusion 57 but is completely misaligned (ie offset) relative to protrusion 57 . In contrast, FIG. 27B shows widened structure 45a with a configuration in which the area of protrusion 55 is aligned with the area of protrusion 59 , and the area of protrusion 57 is aligned with the area of protrusion 61 .

The embodiment of Figures 27A and 27B maintains the insulating guard region 102 between the second portion 52 and the third portion 54 of the shielded wire 42a. In some embodiments, each insulating region 102 may be considered to include a first void region 104 corresponding to a first offset region 101 between the first portion 50 of the shielded wire 42a and the second portion 52 of the shielded wire 42a, And includes a second gap region 106 corresponding to the second offset region 103 between the first portion 50 and the third portion 54 . Regions 104 and 106 are referred to as "void" regions to indicate that the regions do not include conductive material. It is understood that such regions may or may not be empty; and for example, in some embodiments, void regions 104 and 106 may comprise an insulating material, such as one or both of silicon dioxide and silicon nitride.

The insulating region 102 within the widening structure (45/45a) is optional and may be replaced with a conductive material. For example, FIG. 27C shows a widening structure 45b having a configuration in which the conductive material of the shielding line 42a fills the first offset region 101 and the second offset region 103 (ie, the first offset region 101 and the second offset region 103 a configuration constructed entirely of conductive material).

In some embodiments, the sixth portion 60, the seventh portion 62, the eighth portion 64, the ninth portion 66, and the tenth portion 68 of the shielded line 12a in the wiring layer M3 may be considered to include the widened structure 17 of FIG. . Ninth portion 66 and tenth portion 68 include respective portions that are aligned along the y-axis, and include portions that are not aligned along the y-axis. In some embodiments, the entire ninth portion 66 may be aligned with the entire tenth portion 68 along the y-axis; and in some embodiments, the entire ninth portion 66 may be misaligned with the entire tenth portion 68 along the y-axis. (i.e., displaceable along the x-axis relative to the tenth portion).

In the illustrated embodiment of FIG. 24 , the conductive material of the shielding line 12 a extends completely across the widening structure 17 . In other embodiments, an insulating region similar to region 102 of FIGS. 27A and 27B may be provided within widening structure 17 .

28-31 illustrate assembly lOd (previously described in FIG. 20), and show wiring layers Ml, M2, and M3. FIG. 28 is an exploded view showing wiring layers stacked on top of each other; while FIGS. 29 to 31 show each of the individual wiring layers M1, M2, and M3 individually.

Referring to FIG. 29 , the wiring layer M1 includes signal lines 30 alternating with shield lines 32 . The signal wire and the shield wire are separated from each other by insulating material 34 . Shield line 32 is shown coupled to a fixed voltage identified as Vss, but any suitable voltage may be coupled.

Interconnects 22 (only some of which are labeled) are shown along shielded lines 32, where such interconnects 22 are used to vertically connect shielded lines 32 of wiring layer M1 with shielded lines 42 of wiring layer M2 (as shown in FIG. 30 ). .

Referring to FIG. 30 , the wiring layer M2 includes signal lines 40 alternating with shield lines 42 . The signal wire and the shield wire are separated from each other by insulating material 34 . Shield line 42 is shown coupled to a fixed voltage identified as Vss, but any suitable voltage may be coupled.

Interconnects 22 (only some of which are labeled) are shown along shielded lines 42, where such interconnects 22 are used to vertically connect shielded lines 42 of wiring layer M2 with shielded lines 32 of wiring layer M1 (as shown in FIG. 29 ). . Interconnects 20 (only some of which are labeled) are shown along shielded lines 42, where such interconnects 20 are used to vertically connect shielded lines 42 of wiring layer M2 with shielded lines 12 of wiring layer M3 (as shown in FIG. 31 ). . Interconnects 20 are shown in a paired arrangement (ie, two interconnects 20 in each location where shield line 42 of wiring layer M2 connects with shield line 12 of wiring layer M3). In other embodiments, only a single interconnect 20 may be located in at least some of these locations; and in some embodiments, more than two interconnects 20 may be located in at least some of these locations.

Referring to FIG. 31 , the wiring layer M3 includes signal lines 14 alternating with shield lines 12 . The signal wire and the shield wire are separated from each other by insulating material 34 . Shielded line 12 is shown coupled to a fixed voltage identified as Vss, but any suitable voltage may be coupled.

Interconnects 20 (only some of which are labeled) are shown along shielded lines 12, where such interconnects 20 are used to vertically connect shielded lines 12 of wiring layer M3 with shielded lines 42 of wiring layer M2 (as shown in FIG. 30 ). . Coverage areas 18a and 18b are schematically indicated in FIGS. 30 and 31 , and this corresponds to the area where interconnect 20 vertically connects shield line 12 of wiring layer M3 with shield line 42 of wiring layer M2.

Regions B and B' are schematically illustrated with respect to wiring layers M2 and M3 of FIGS. 30 and 31 , and such regions include redundant (dummy) regions (eg, channels). Specifically, one of the shielded wires 42 in FIG. 30 is marked with a mark 42a to distinguish this shielded wire from other shielded wires. The redundant area of the wiring layer M2 includes the widening structure 125 along the shielding line 42a in the area B, and includes the widening structure 127 along the shielding line 42a in the area B′. One of the shielded wires 12 in FIG. 31 is marked with a mark 12a to distinguish this shielded wire from other shielded wires, and the redundant regions of the wiring layer M3 include widening structures 131 along the shielded wires 12a in regions B and B' respectively. and 133.

In some embodiments, the wiring layers M2 and M3 of FIGS. 30 and 31 may be referred to as a lower wiring layer and an upper wiring layer, respectively; and may be considered to include the illustrated first wiring track, second wiring track, third wiring track and a fourth routing track (labeled as first, second, third and fourth tracks in FIGS. 30 and 31 ). The first wiring track, the second wiring track, the third wiring track and the fourth wiring track of the upper wiring layer M3 directly cover the first wiring track, the second wiring track, the third wiring track and the fourth wiring track of the lower wiring layer M2 .

The first wiring track, the second wiring track, the third wiring track and the fourth wiring track extend in a first direction along the x-axis and extend parallel to each other (or at least substantially parallel to each other). The first routing track and the third routing track sandwich the second routing track therebetween; and the second routing track and the fourth routing track sandwich the third routing track therebetween.

In some embodiments, it may be considered that the lower wiring layer M2 includes a first wiring corresponding to the wiring of the shielding line 42a. The first wiring can be considered to have similar portions 50, 52 and 54 to those described above with respect to the embodiments of Figures 21-24. Specifically, the first wiring 42a has a first portion 50 extending along the second wiring track (and extending across both regions B and B′), and a second portion 52 along the first routing track (and within the region B′ ) extends, and the third portion 54 extends along the third routing track (and within region B). The first portion 50 may be considered to include a first side 51 and a second side 53 opposite the first side. The second portion 52 may be considered offset from the first side 51 of the first portion 50 by a first offset region 56 and the third portion 54 may be considered offset from the second side 53 by a second offset region 58 . In the illustrated embodiment, the first portion 50, the second portion 52, and the third portion 54 extend along the x-axis direction. The second portion 52 is offset from the second wiring track by protrusions 55 and 57 extending along the y-axis. The third portion 54 is offset from the second wiring track by protrusions 59 and 61 extending along the y-axis.

The upper wiring layer M3 can be considered to include a second wiring corresponding to the wiring of the shield line 12a. The second wiring 12a is connected to the first wiring 42a, and can be considered to have a fourth portion 60 similar to that described above with respect to the embodiment of FIGS. 21 to 24 . The fourth portion 60 extends along the third routing track and is electrically coupled to the third portion 54 of the first routing 42a ( FIG. 18 ) through the interconnect 20a.

32A shows a cross-section along the line 32A-32A of FIGS. 30 and 31, and shows the interconnection 20a extending through the insulating material 34 to electrically connect the shielded line 12a of the upper wiring layer M3 to the shielded line 42a of the lower wiring layer M2. coupling.

The upper wiring layer M3 ( FIG. 31 ) includes a third wiring 12 b having a fifth portion 62 similar to the portion 62 of the embodiment of FIGS. 21 to 24 . The fifth portion 62 of the third wiring 12b extends along the first wiring track, and is electrically coupled with the second portion 52 of the underlying wiring layer M2 ( FIG. 30 ) through the interconnection 20b. A cross-section along line 32B-32B is shown in Figure 32B, and this shows the coupling of fifth portion 62 and second portion 52 through interconnect 20b.

In some embodiments, the first wiring 42 a of the lower wiring layer M2 may be considered to include a first portion 50 , a second portion 52 and a third portion 54 . The upper wiring layer M3 can be considered to include the wiring 12b as the second wiring, and include the wiring 12a as the third wiring. The second wiring 12b includes a fourth portion 62 along the first wiring track, and the third wiring 12a includes a fifth portion 60 extending along the third wiring track. At least one contact plug 20b penetrates the insulating material layer 34 to connect the second portion 52 of the first wiring 42a with the fourth portion 62 of the second wiring 12b; and at least one contact plug 20a penetrates the insulating material layer 34 to connect The third portion 54 of the first wiring 42a is connected to the fifth portion 60 of the third wiring 12a. In the shown embodiment, the third wiring 12a has a sixth portion 64 that extends along the second wiring track and is electrically coupled with the first portion 50 of the underlying wiring 42a ( FIG. 30 ) through the interconnect 20c. A cross-section along line 32C-32C is shown in Figure 32C, and this shows the coupling of sixth portion 64 and first portion 50 through interconnect 20c.

In some embodiments, the third wiring 12a of the upper wiring layer M3 may be considered to further include a seventh portion 66 extending along the fourth wiring track. The fifth and sixth portions ( 60 and 64 ) are offset from each other by a first offset region 200 , and the fifth and seventh portions ( 60 and 66 ) are offset from each other by a second offset region 202 . The first offset region 200 and the second offset region 202 may include void regions, as shown in FIG. 31 . Alternatively, the first and second offset regions 200 and 202 may be filled with (ie, may completely include) the conductive material of the shielding line 12a, as shown in FIGS. 33 and 34 . In some embodiments, regions 64 and 66 of FIG. 31 may be referred to as the seventh region and the eighth region, respectively; they extend along the second routing track and the fourth routing track, respectively.

In some embodiments, the first wiring 42a of the lower wiring layer M2 may be considered to further include a ninth portion (corresponding to the protrusion 55 or 57) extending along the y-axis to couple the first portion 50 and the second portion 52 to each other, and a tenth portion (corresponding to the protrusion 59 or 61 ) extending along the y-axis to connect the first portion 50 and the third portion 54 to each other.

In some embodiments, the first and second portions (50 and 52) of the first wiring 42a can be considered to be offset from each other by the third offset region 204, and the first and third portions (50) of the first wiring 42a and 44) may be considered to be offset from each other by the fourth offset region 206. The third offset region 204 and the fourth offset region 206 may include void regions, as shown in FIG. 30 . Alternatively, the third offset region 204 and the fourth offset region 206 may be filled with (ie, may completely include) the conductive material of the shield line 42a, as shown in FIGS. 35 and 36 .

The assemblies discussed above can be used in electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power supply modules, communication modems, processor modules, and application-specific modules, and may include multi-layer multi-chip modules. An electronic system can be any of a wide range of systems such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc. .

The specific orientations of the various embodiments in the figures are for illustration purposes only, and in some applications the embodiments may be rotated relative to the orientation shown. The description provided herein and the claims that follow refer to any structure having the described relationship between the various features, whether the structure is in a particular orientation of the figures, or rotated relative to that orientation.

To simplify the drawings, unless otherwise indicated, the cross-sectional views of the accompanying illustrations show only features within the plane of the cross-section, and do not show material behind the plane of the cross-section.

When a structure is referred to above as being "on" or "opposite" another structure, it can be directly on the other structure, or intervening structures may also be present. In contrast, when a structure is referred to as being "directly on" or "directly against" another structure, there are no intervening structures present. When a structure is referred to as being "connected" or "coupled" to another structure, it can be directly connected or coupled to the other structure or intervening structures may be present. In contrast, when a structure is referred to as being "directly connected" or "directly coupled" to another structure, there are no intervening structures present.

Some embodiments include an assembly (eg, 510 ) having a first wiring layer (eg, M3 ) with a plurality of first shielding lines (eg, 512 ) and first signal lines (eg, 514 ) arranged alternately. The first shielding line and the first signal line have a first segment (eg, 520, 526) extending along a first direction (eg, the direction of axis 503), extending along the first direction and laterally offset from the first segment A second segment (eg, 522, 528) of , and a first link segment (eg, 524, 530) connecting the first and second segments to each other. The assembly includes a second wiring layer (eg, M2 ) under the first wiring layer, and has a plurality of second shielding lines (eg, 516 ) and second signal lines (eg, 518 ) arranged alternately. The second shielding line and the second signal line have a third segment (eg, 532, 538) extending along the first direction, a fourth segment (eg, 534) extending along the first direction and laterally offset from the third segment. , 540), and a second link segment (eg, 536, 542) interconnecting the third and fourth segments. A fourth segment of the second shielded wire extends below the first segment of the first shielded wire and is electrically coupled to the first segment of the first shielded wire through a vertical interconnect (546).

Some embodiments include an assembly (eg, 510 ) having a first wiring layer (eg, M3 ) including a plurality of first shielding lines (eg, 512 ) and first signal lines (eg, 514 ) arranged alternately. The assembly has a second wiring layer (eg, M2 ) below the first wiring layer, and it includes a plurality of second shielding lines (eg, 516 ) and second signal lines (eg, 518 ) arranged alternately. One of the first shielded wires has a first portion (eg, 548) extending in a first direction (eg, the direction of axis 503), a second portion (eg, For example, 550) and a third portion (for example, 552) extending in the first direction. The second part interconnects the first part and the third part to each other. One of the first signal lines is adjacent to the one of the first shielded lines. The one of the first signal lines has fourth, fifth, and sixth portions (eg, 554, 556, 558) that are connected to the third, first, and second portions of the one of the first shielded lines, respectively. The second and first parts are basically parallel. One of the second shielded lines includes seventh and eighth portions (e.g., 560, 562) respectively below and substantially perpendicular to the third portion of the first shielded line and the fourth portion of the first signal line alignment. A vertical interconnect (eg, 546 ) electrically connects the third portion of the one of the first shields to the seventh portion of the one of the second shielded lines.

Some embodiments include an assembly (eg, 510 ) having a first wiring layer (eg, M3 ) including a plurality of first shielding lines (eg, 512 ) and first signal lines (eg, 514 ) arranged alternately. The assembly has a second wiring layer (eg, M2 ) below the first wiring layer, and it includes a plurality of second shielding lines (eg, 516 ) and second signal lines (eg, 518 ) arranged alternately. The mesh structure (eg, 578 ) includes a first shielded wire electrically coupled with a second shielded wire. Each of the first shielded wires of the mesh structure extends primarily along a first direction (eg, the direction of axis 503 ) and along two first paths (eg, 580 , 582 ) that are laterally offset relative to each other. extend. Each of the second shielded wires of the mesh structure extends primarily along a first direction and along two second paths (eg, 590 , 592 ) that are laterally offset relative to each other. The first shielded wires of the mesh are primarily laterally offset from the second shielded wires of the mesh, except that each of the first paths of each of the first shielded wires has an overlapping region (e.g., 544), wherein the first shielded wires Portions of one shielded line vertically overlap portions of a second shielded line. A vertical interconnect (eg, 546 ) is within the overlap region to connect the first shielded line to the second shielded line. One of the first paths of the individual first shielded wires has an overlapping region over a different second shielded wire than the other of the first paths of the individual first shielded wires.

Some embodiments include an assembly having a first routing track, a second routing track, a third routing track, and a fourth routing track over a substrate. The first wiring track, the second wiring track, the third wiring track and the fourth wiring track extend in the first direction. The first routing track and the third routing track sandwich the second routing track therebetween; and the second routing track and the fourth routing track sandwich the third routing track therebetween. The lower wiring layer includes a first wiring having a first portion extending along the second wiring track, a second portion extending along the first wiring track, and a third portion extending along the third wiring track. The second portion is offset by a first offset region along a first side of the first portion, and the third portion is offset by a second offset region along a second side of the first portion. The first side is opposite the second side. The upper wiring layer includes a second wiring electrically connected to the first wiring and having a fourth portion extending along the third wiring track. The third portion of the first wiring is electrically coupled with the fourth portion of the second wiring.

Some embodiments include an assembly having a first routing track, a second routing track, a third routing track, and a fourth routing track over a substrate. The first routing track, the second routing track, the third routing track and the fourth routing track extend in the first direction and are substantially parallel to each other. The first routing track and the third routing track sandwich the second routing track therebetween; and the second routing track and the fourth routing track sandwich the third routing track therebetween. The lower wiring layer includes first wiring. The first wiring includes a first portion extending along the second wiring track, a second portion extending along the first wiring track, a third portion extending along the third wiring track, in a second direction crossing the first direction A fourth portion extending to couple the first portion and the second portion, and a fifth portion extending in the second direction to connect the first portion and the third portion. The upper wiring layer includes second wiring electrically connected to the first wiring. The second wiring includes a sixth portion extending along the third wiring track, a seventh portion extending along the second wiring track, an eighth portion extending along the fourth wiring track, extending in the second direction to couple the sixth and a ninth part of the seventh part, and a tenth part extending in the second direction to couple the sixth part and the eighth part.

Some embodiments include an assembly having a first routing track, a second routing track, a third routing track, and a fourth routing track over a substrate. The first routing track, the second routing track, the third routing track and the fourth routing track extend in the first direction and are substantially parallel to each other. The first routing track and the third routing track sandwich the second routing track therebetween; and the second routing track and the fourth routing track sandwich the third routing track therebetween. The lower wiring layer includes first wiring. The first wiring includes a first portion extending along the second wiring track, a second portion extending along the first wiring track, and a third portion extending along the third wiring track. The upper wiring layer includes second and third wirings electrically connected to the first wirings. The second wiring includes a fourth portion extending along the first wiring track, and the third wiring includes a fifth portion extending along the third wiring track. The insulating layer is located between the lower wiring layer and the upper wiring layer. At least one contact plug penetrates the insulating layer to couple the second portion of the first wiring and the fourth portion of the second wiring. At least one contact plug penetrates the insulating layer to couple the third portion of the first wiring and the fifth portion of the third wiring.

Claims (22)

1. a kind of sub-assembly comprising:

First wiring layer comprising multiple first shielding lines being alternately arranged and the first signal wire;First shielding line and institute Each stated in the first signal wire has the first segment extended along a first direction, extends along the first direction and from institute The second segment of first segment lateral shift is stated, and makes the first segment and the second segment the first chained segment interconnected amongst one another;

Second wiring layer under first wiring layer and includes the multiple secondary shielding lines being alternately arranged and second signal Line;Each in the secondary shielding line and the second signal line have the third section extended along the first direction, Extend along the first direction and from the 4th section of the third section lateral shift, and makes the third section and 4th section described Second chained segment interconnected amongst one another;And

Below the first segment that described 4th section of the secondary shielding line extends to the first shielding line, and pass through perpendicular interconnection It is electrically coupled to the first segment of first shielding line.

2. sub-assembly according to claim 1, wherein first chained segment is substantially normal to the first segment and institute State second segment extension.

3. sub-assembly according to claim 2, wherein first chained segment extends along second direction, and wherein second Chained segment extends also along the second direction.

4. sub-assembly according to claim 1, wherein:

Individual first shielding lines have individual first shielding line first segments and individual first shielding line second segments;

Individual first signal wires close to individual first shielding lines have individual first signal wire first segments and individual first Signal wire second segment;

First chained segment includes to keep individual first shielding line first segments and individual first shielding line second segments mutual Individual first shielding line chained segments even, and include to make individual first signal wire first segments and individual first signal wires Individual first signal wire chained segments of second segment interconnection;

Individual first shielding line chained segments are along the first direction from the individual first signal wires link field offsets the One distance;

Individual secondary shielding lines have individual secondary shielding line thirds below the region of individual first signal wire first segments Section, and there is below the region of the first shielding line first segment and extend to the area of individual first signal wire second segments The 4th section of individual secondary shielding lines below domain, and in individual secondary shielding line third sections and individual secondary shielding lines There are individual second chained segments between 4th section;

The 4th section of individual secondary shielding lines are electrically coupled to individual first shieldings by the individual in the perpendicular interconnection Line first segment;

Individual second chained segments link field offset second distance along the first direction from individual first signal wires; And

The second distance is more than first distance.

5. sub-assembly according to claim 4, wherein the second distance is at least twice of first distance.

6. sub-assembly according to claim 1, wherein:

First shielding line is all electrically connected with Vss;And

The secondary shielding line is all electrically connected with Vss.

7. sub-assembly according to claim 1, wherein:

First shielding line includes some lines being electrically connected with Vdd and some lines being electrically connected with Vss;And

The secondary shielding line includes some lines being electrically connected with Vdd and some lines being electrically connected with Vss.

8. sub-assembly according to claim 1 wherein the perpendicular interconnection is first group of perpendicular interconnection, and includes:

Third wiring layer under second wiring layer and includes the multiple third shielding lines being alternately arranged and third signal Line;The third shielding line and the third signal wire are substantially normal to the third section and the 4th section of extension;And

The third shielding line is electrically coupled to the third section of the secondary shielding line and described by second group of perpendicular interconnection 4th section.

9. a kind of sub-assembly comprising:

First wiring layer comprising multiple first shielding lines being alternately arranged and the first signal wire;

Second wiring layer below first wiring layer and includes the multiple secondary shielding lines being alternately arranged and second signal Line;

Reticular structure comprising first shielding line being electrically coupled with the secondary shielding line;The reticular structure it is described Each in first shielding line extends mainly along first direction, and along two first via deviated laterally relative to each other Diameter extends;Each in the secondary shielding line of the reticular structure extends mainly along the first direction and along phase Two the second paths being laterally offset from each other are extended;

First shielding line of the reticular structure mainly from the secondary shielding line lateral shift of the reticular structure, removes It hangs down each part with first shielding line in the first path of each in first shielding line Directly it is overlapped the region of the part of the secondary shielding line;Perpendicular interconnection in the overlapping region with by first shielding line with The secondary shielding line connection;And

One in the first path of individual first shielding lines has an overlapping region, and the overlapping region is with described individual first Above another different secondary shielding line in the first path of shielding line.

10. sub-assembly according to claim 9, wherein each in first shielding line includes by described two the The first bridge areas as there that one path is connected to each other.

11. sub-assembly according to claim 10, wherein first bridge areas as there is along being substantially normal to described The second direction in one direction extends.

12. sub-assembly according to claim 10, wherein each in the secondary shielding line includes will be described two The second bridge areas as there that second path is connected to each other.

13. sub-assembly according to claim 12, wherein first bridge region and second bridge region are along basic On be orthogonal to the first direction second direction extend.

14. sub-assembly according to claim 9 comprising under second wiring layer and include multiple third shieldings The third wiring layer of line;The third shielding line extends mainly along the second direction for being substantially normal to the first direction; And the wherein described perpendicular interconnection corresponds to first group of perpendicular interconnection, and the third shielding line passes through second group of perpendicular interconnection thermocouple Close the secondary shielding line.

15. a kind of sub-assembly comprising:

First wiring tracks, the second wiring tracks, third wiring tracks and the 4th wiring tracks, on substrate side, wherein institute State the first wiring tracks, second wiring tracks, the third wiring tracks and the 4th wiring tracks in a first direction It is upper to extend and be substantially parallel to each other, wherein first wiring tracks and the third wiring tracks connect up rail by described second Road presss from both sides in-between, and the third wiring tracks are clipped in it by wherein described second wiring tracks and the 4th wiring tracks Between;

Lower-layer wiring layer comprising the first wiring, wherein first wiring includes extending along second wiring tracks First part, the second part extended along first wiring tracks, the third portion extended along the third wiring tracks Divide, upwardly extended in the second party intersected with the first direction to couple the 4th of the first part and the second part the Part, and extend in this second direction to couple the Part V of the first part and the Part III;And

Upper-layer wirings layer comprising be electrically connected to it is described first wiring second wiring, wherein it is described second wiring include along Part VI that the third wiring tracks extend, the Part VII extended along second wiring tracks, along described the The Part VIII of four wiring tracks extension extends along the second direction to couple the Part VI and the Part VII Part IX, and along the second direction extend to couple the Part X of the Part VI and the Part VIII.

16. sub-assembly according to claim 15 further comprises in the lower-layer wiring layer and the upper-layer wirings Insulating layer between layer, and penetrate what the insulating layer was connected up with the first part and second that couple first wiring At least one contact plug of the Part VII.

17. sub-assembly according to claim 15 further comprises in the lower-layer wiring layer and the upper-layer wirings Insulating layer between layer, and penetrate what the insulating layer was connected up with the Part III and second that couple first wiring At least one contact plug of the Part VI.

18. sub-assembly according to claim 15, wherein the Part IV and the Part V are included in described the Straight corresponding portion is directed on two directions, and the Part IX and the Part X include in this second direction It is directed at straight corresponding portion.

19. sub-assembly according to claim 15, wherein the Part IV is in this second direction with the described 5th Part misalignment, and the Part IX in this second direction with the Part X misalignment.

20. sub-assembly according to claim 15, wherein each confession in first wiring and second wiring There should be fixed voltage.

21. sub-assembly according to claim 15, wherein the lower-layer wiring layer further comprises and first wiring The third wiring of electrical connection is disconnected, wherein third wiring includes the 11st extended along the third wiring tracks The 12nd part divided, extended along the 4th wiring tracks, and extend in this second direction to couple the described tenth Tenth three parts of a part of and described 12nd part.

22. sub-assembly according to claim 15, wherein the upper-layer wirings layer further comprises and second wiring The 4th wiring of electrical connection is disconnected, wherein the 4th wiring includes the 14th extended along second wiring tracks The 15th part divided, extended along first wiring tracks, and extend in this second direction to couple the described tenth 16th part of four parts and the 15th part.