CN108683418B

CN108683418B - Input circuit compatible with suspended state

Info

Publication number: CN108683418B
Application number: CN201810298684.6A
Authority: CN
Inventors: 谢芳
Original assignee: Shanghai Sensylink Microelectronics Co ltd
Current assignee: Sensylink Microelectronics Co ltd
Priority date: 2018-04-04
Filing date: 2018-04-04
Publication date: 2022-03-25
Anticipated expiration: 2038-04-04
Also published as: CN108683418A

Abstract

The invention provides an input Circuit compatible with a suspended state, which comprises a detection Circuit; the detection Circuit comprises an input end PIN, an output end INTERNAL, a power supply end and a ground end; the detection Circuit converts a signal obtained by the input terminal PIN from the outside and inputs the converted signal to an output terminal INTERNAL, and the output terminal INTERNAL outputs a detection signal. According to the input circuit compatible with the suspended state, when the pin of the chip is suspended, the input circuit can automatically judge and output a high level or a low level, and simultaneously lock the potential of the pin to be a high potential or a low potential. The input circuit compatible with the suspended state provided by the invention does not consume current when the pin is normally connected with a power supply or a ground. The invention is an interface portion of a chip designed using CMOS technology for integrated circuits.

Description

Input circuit compatible with suspended state

Technical Field

The present invention relates to an input circuit, and more particularly, to an input circuit compatible with a suspended state.

Background

In many chip circuit applications, in order to reduce the number of PINs (PIN PINs or PINs) of a chip, different states of one PIN are required to represent different information, and the chip identifies the states on the PIN to obtain its own ID. After the chip obtains its own ID, a response can be made later to distinguish the chip from other IDs. When a plurality of similar chips which are connected in parallel on the same Bus (Bus) together, for example, a plurality of sensor chips are connected to the same group of Bus, different IDs (identification) are required to be distinguished from each other, and the chip with the chip PIN state detection function can realize independent IDs by connecting PIN PINs in different ways on a board level.

Different chip IDs can be realized by connecting a chip PIN PIN to a high potential, a low potential, suspending, connecting a communication protocol interface and other different methods. For example, a System Management Bus (SMBus) or I2C protocol communication chip may connect a PIN for chip identification PIN to a power supply terminal (VDD), a ground terminal (GND) of the chip, and suspend in the air, and connect to a data PIN SDA or a clock PIN clock signal line (SCL) of the SMBus protocol. Such a PIN leg can distinguish 5 states, and if n PIN legs are simultaneously present, the distinguished states are 5 × n, and 5 × n different IDs can be realized.

A 3-state control signal input IO circuit, referred to in patent publication No. CN102931971A, provides a detection circuit for a high state, a low state and a floating state, which allows loading three input states at the input terminal — the high state, the low state and the floating state, and generating three corresponding output states at the output terminal. When the external input signal IN is high, the output result O1 is less than O2, O3 is less than O4; when the external input signal IN is IN a low level, the output results are that O1 is greater than O2, and O3 is greater than O4; when the external input signal IN is suspended, the output result is that O1 is smaller than O2, and O3 is larger than O4. Because one IO can generate three input states, for a chip needing to input a plurality of control signals from the outside, the number of the IO input by adopting 3-state control signals is obviously reduced compared with that of the traditional IO, thereby reducing the area of the chip and improving the reliability of the chip. The invention is different from the patent in that the invention can lock the suspension state at a determined potential, and the invention realizes no static power consumption, simple circuit and low cost.

Disclosure of Invention

In view of the defects in the prior art, the present invention provides an input circuit compatible with the suspended state.

The input Circuit compatible with the suspended state comprises a detection Circuit, a detection Circuit and a control Circuit, wherein the detection Circuit is used for detecting the suspended state of the input Circuit;

the detection Circuit comprises an input end PIN, an output end INTERNAL, a power supply end and a ground end;

the detection Circuit converts a signal obtained by the input terminal PIN from the outside and inputs the converted signal to an output terminal INTERNAL, and the output terminal INTERNAL outputs a detection signal.

Preferably, the detection Circuit includes a first NMOS transistor, a first resistor R1, a second resistor R2, a fifth NMOS transistor, an inverter Schmitt, a third PMOS transistor, and a sixth NMOS transistor;

the drain electrode of the first NMOS tube forms an input end PIN;

the source electrode of the first NMOS tube forms a grounding end;

the grid electrode of the first NMOS tube is connected to one end of a first resistor R1;

the other end of the first resistor R1 is connected to the source electrode of the first NMOS tube;

one end of the second resistor R2 is connected to the drain electrode of the first NMOS tube;

the other end of the second resistor R2 is connected to the input end of the inverter;

the drain D5 of the fifth NMOS transistor is connected to the other end of the second resistor R2;

the source electrode of the fifth NMOS tube is connected to the source electrode of the first NMOS tube;

the grid electrode of the fifth NMOS tube is connected to the control end of the phase inverter;

the grid electrode of the third PMOS tube is connected to the output end of the phase inverter

The grid electrode of the third PMOS tube is connected to the grid electrode of the sixth NMOS tube;

the drain electrode of the third PMOS tube is connected to the drain electrode of the sixth NMOS tube;

the source electrode of the sixth NMOS transistor is connected to the source electrode of the first NMOS transistor

The source electrode of the third PMOS tube is connected to the source electrode of the first PMOS tube;

and the drain of the third PMOS tube forms an output end INTERNAL.

Preferably, the inverter Schmitt;

the detection Circuit comprises a first PMOS tube and a second PMOS tube;

the phase inverter Schmitt comprises a first PMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube;

the grid electrode of the first PMOS tube forms the input end of the phase inverter;

the source electrode of the first PMOS tube forms a power supply end;

the grid electrode of the first PMOS tube is connected to the grid electrode of the third NMOS tube;

the grid electrode of the second NMOS tube is connected to the grid electrode of the first PMOS tube; the source electrode of the second NMOS tube is connected to the drain electrode of the third NMOS tube;

the source electrode of the third NMOS tube is connected to the source electrode of the first NMOS tube;

the drain electrode of the second NMOS tube forms a control end of the phase inverter;

the drain electrode of the second NMOS tube is connected to the drain electrode of the first PMOS tube;

the grid electrode of the fourth NMOS tube forms the output end of the phase inverter;

the source electrode of the fourth NMOS tube is connected to the source electrode of the second NMOS tube;

the grid electrode of the fourth NMOS tube is connected to the drain electrode of the first PMOS tube;

the drain electrode of the fourth NMOS tube is connected to the drain electrode of the second PMOS tube;

the grid electrode of the second PMOS tube is connected to the source electrode of the first NMOS tube;

and the source electrode of the second PMOS tube is connected to the source electrode of the first PMOS tube.

Compared with the prior art, the invention has the following beneficial effects:

1. according to the input circuit compatible with the suspended state, when the pin of the chip is suspended, the input circuit can automatically judge and output a high level or a low level, and simultaneously lock the potential of the pin to be a high potential or a low potential.

2. The input circuit compatible with the suspended state provided by the invention does not consume current when the pin is normally connected with a power supply or a ground.

3. The invention adopts Complementary Metal Oxide Semiconductor (CMOS) technology of integrated circuit to realize the interface part of the designed chip.

4. When the chip is designed intentionally due to compatibility reasons or a system manufacturer using the chip, the input PIN of the chip is suspended, the potential of the PIN of the chip is uncertain, and the chip cannot detect the state of the PIN. If the input itself has a resistive path up or down, the chip will consume current when the PIN is connected to ground or power, or when the communication protocol interface is turned on. The circuit designed by the invention can realize that the state of the PIN PIN is locked to a determined potential, so that the chip detects the determined state, and meanwhile, when the PIN is grounded or powered on, or a communication protocol interface is switched on, the chip does not consume current. In addition, the circuit has simple structure, small realization area and low cost.

Drawings

Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:

fig. 1 is a block diagram of an interface circuit of an input circuit compatible with a suspended state according to the present invention.

Fig. 2 is a circuit diagram of an embodiment of the suspension-compatible input circuit according to the present invention.

The reference numbers in the figures are shown in the following table:

101 input PIN	102 output terminal INTERNAL
		103 power supply terminal	104 ground terminal
105 detection Circuit	202 first NMOS transistor
		204 first resistor R1	205 second resistor R2
206 fifth NMOS transistor	207 first PMOS transistor
		208 second NMOS transistor	209 third NMOS transistor
210 fourth NMOS transistor	211 second PMOS tube
		212 third PMOS transistor	213 sixth NMOS transistor

Detailed Description

The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.

The invention provides an input Circuit compatible with a suspended state, which comprises a detection Circuit; the detection Circuit comprises an input end PIN, an output end INTERNAL, a power supply end and a ground end; the detection Circuit converts a signal obtained by the input terminal PIN from the outside and inputs the converted signal to an output terminal INTERNAL, and the output terminal INTERNAL outputs a detection signal.

The detection Circuit comprises a first NMOS (N-channel metal oxide semiconductor) tube, a first resistor R1, a second resistor R2, a fifth NMOS tube, a phase inverter Schmitt, a third PMOS (P-channel metal oxide semiconductor) tube and a sixth NMOS tube; the drain electrode of the first NMOS tube forms an input end PIN; the source electrode of the first NMOS tube forms a grounding end; the grid electrode of the first NMOS tube is connected to one end of a first resistor R1; the other end of the first resistor R1 is connected to the source electrode of the first NMOS tube; one end of the second resistor R2 is connected to the drain electrode of the first NMOS tube; the other end of the second resistor R2 is connected to the input end of the inverter; the drain D5 of the fifth NMOS transistor is connected to the other end of the second resistor R2; the source electrode of the fifth NMOS tube is connected to the source electrode of the first NMOS tube; the grid electrode of the fifth NMOS tube is connected to the control end of the phase inverter; the grid electrode of the third PMOS tube is connected to the output end of the phase inverter; the grid electrode of the third PMOS tube is connected to the grid electrode of the sixth NMOS tube; the drain electrode of the third PMOS tube is connected to the drain electrode of the sixth NMOS tube; the source electrode of the sixth NMOS tube is connected to the source electrode of the first NMOS tube; the source electrode of the third PMOS tube is connected to the source electrode of the first PMOS tube; and the drain of the third PMOS tube forms an output end INTERNAL.

The inverter Schmitt; the detection Circuit comprises a first PMOS tube and a second PMOS tube; the phase inverter Schmitt comprises a first PMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube; the grid electrode of the first PMOS tube forms the input end of the phase inverter; the source electrode of the first PMOS tube forms a power supply end; the grid electrode of the first PMOS tube is connected to the grid electrode of the third NMOS tube; the grid electrode of the second NMOS tube is connected to the grid electrode of the first PMOS tube; the source electrode of the second NMOS tube is connected to the drain electrode of the third NMOS tube; the source electrode of the third NMOS tube is connected to the source electrode of the first NMOS tube; the drain electrode of the second NMOS tube forms a control end of the phase inverter; the drain electrode of the second NMOS tube is connected to the drain electrode of the first PMOS tube; the grid electrode of the fourth NMOS tube forms the output end of the phase inverter; the source electrode of the fourth NMOS tube is connected to the source electrode of the second NMOS tube; the grid electrode of the fourth NMOS tube is connected to the drain electrode of the first PMOS tube; the drain electrode of the fourth NMOS tube is connected to the drain electrode of the second PMOS tube; the grid electrode of the second PMOS tube is connected to the source electrode of the first NMOS tube; and the source electrode of the second PMOS tube is connected to the source electrode of the first PMOS tube.

The suspension-compatible input circuit provided by the present invention is further described as follows:

as shown in fig. 1, the input PIN 101 is a PIN and is directly connected to an external system board, the output terminal INTERNAL102 is an internally obtained detection signal, and the detection Circuit105 converts the state of the PIN 101 into 102 and inputs the 102 into the chip.

As shown in fig. 2, in the input circuit compatible with the suspended state provided by the present invention, the first NMOS transistor 202 is an NMOS providing an ESD discharging path, and the first resistor R1204 is a resistor providing a fast turn-on of an ESD coupled NMOS. The second resistor R2205 is a current limiting resistor for protecting the gates of the first PMOS transistor 207, the second NMOS transistor 208, and the third NMOS 209. The first PMOS transistor 207, the second NMOS 208, the third NMOS 209, and the fourth NMOS 210 preferably form an inverter Schmitt structure, the sampling inverter Schmitt structure is used as an input to filter jitter glitches of an input signal, and the second PMOS transistor 211 is used to isolate an ERC problem that may be caused when a drain of the fourth NMOS 210 is directly connected to a power supply. The third PMOS transistor 212 and the sixth NMOS 213 form an inverter together, so that the detected signal of the output terminal INTERNAL102 is identical to the signal of the input terminal 101, i.e. the input PIN.

In the invention, the grid electrode of the fifth NMOS tube 206 is connected to the output end INTERNAL of the inverter Schmitt, the drain electrode of the fifth NMOS tube 206 is connected to the input end of the inverter Schmitt, and the fifth NMOS tube 206 and the Schmitt inverter form a latch mechanism together.

The fifth NMOS transistor 206 and the inverter Schmitt together form a latch mechanism in the present invention, which can latch the input suspended state to a certain low signal.

In the latch structure of the present invention, under the condition of input floating, the charge stored in the input floating is leaked by the leakage of the drain of the ESD structure formed by the first NMOS transistor 202, so that the input potential is finally low. Since the first NMOS transistor 202 is used as an ESD leakage path, the area of the drain is usually larger, so that the floating stored charge can be quickly discharged, and the floating state can be quickly locked to a low potential.

The fifth NMOS transistor 206 of the present invention is generally designed with a reverse aspect ratio. In this way, in the case of the input PIN 101 switching on the communication protocol interface, for example the SDA or SCL signal of I2C, the current consumed can be very small.

The circuit has no static power consumption when the input PIN 101 is grounded or connected into a power supply. While the dangling stateful approach is detected as low. The flying and grounding are equivalent to the user.

The PIN-in-air state is detected as a low signal in the specific circuit of the invention, but the invention is not limited to the PIN-in-air state as a low signal, in the design, the NMOS of the fifth NMOS tube 206 which is pulled down is replaced by the first PMOS tube 207 which is pulled up to the power supply, and meanwhile, a route power supply is added to the first PMOS tube 207 which is input or a reverse diode is added to provide power supply to the leakage of the input, so that the PIN-in-air state can be detected as a high signal.

The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.

Claims

1. An input Circuit compatible with a suspended state is characterized by comprising a detection Circuit;

the detection Circuit converts a signal acquired by the input terminal PIN from the outside and inputs the converted signal to an output terminal INTERNAL, and the output terminal INTERNAL outputs a detection signal;

the detection Circuit comprises a first NMOS (N-channel metal oxide semiconductor) tube, a first resistor R1, a second resistor R2, a fifth NMOS tube, a phase inverter Schmitt, a third PMOS (P-channel metal oxide semiconductor) tube and a sixth NMOS tube;

the drain electrode of the first NMOS tube forms an input end PIN;

the source electrode of the first NMOS tube forms a grounding end;

the source electrode of the sixth NMOS tube is connected to the source electrode of the first NMOS tube;

and the drain of the third PMOS tube forms an output end INTERNAL.

2. The suspended state compatible input circuit of claim 1,

the detection Circuit comprises a first PMOS tube and a second PMOS tube;

the source electrode of the first PMOS tube forms a power supply end;