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CN108630105A - 一种阵列基板、显示面板及显示装置 - Google Patents

一种阵列基板、显示面板及显示装置 Download PDF

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Publication number
CN108630105A
CN108630105A CN201810443168.8A CN201810443168A CN108630105A CN 108630105 A CN108630105 A CN 108630105A CN 201810443168 A CN201810443168 A CN 201810443168A CN 108630105 A CN108630105 A CN 108630105A
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China
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pixel
line
multiplexing
array substrate
gate
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Granted
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CN201810443168.8A
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CN108630105B (zh
Inventor
杨明
玄明花
张粲
王灿
岳晗
丛宁
刘佳尧
赵文卿
肖丽
刘冬妮
王磊
陈亮
陈小川
杨盛际
卢鹏程
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to CN201810443168.8A priority Critical patent/CN108630105B/zh
Publication of CN108630105A publication Critical patent/CN108630105A/zh
Priority to PCT/CN2019/076250 priority patent/WO2019214323A1/zh
Priority to US16/642,584 priority patent/US11374032B2/en
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Publication of CN108630105B publication Critical patent/CN108630105B/zh
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
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    • G02B27/0075—Optical systems or apparatus not provided for by any of the groups G02B1/00 - G02B26/00, G02B30/00 with means for altering, e.g. increasing, the depth of field or depth of focus
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    • G09G3/001—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
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    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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  • Physics & Mathematics (AREA)
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  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
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  • Computer Hardware Design (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

本发明提供了一种阵列基板、显示面板及显示装置，涉及显示技术领域。本发明通过在阵列基板中设置多个像素区域，每个像素区域包括设置在显示区的像素组以及设置在盲区的与像素组一一对应的驱动电路单元，在相邻的两行像素组之间设置有栅线，在相邻的两列像素组之间设置有数据线，每个像素组包括至少两个像素电极，驱动电路单元包括驱动元件，驱动元件与栅线、数据线以及像素电极连接。通过在显示区设置像素组，在盲区设置驱动电路单元，像素组内的像素电极之间无栅线及数据线，使得像素电极的排布更加紧密，像素组内像素电极的解析度显著提高，提高了集成成像的显示效果。

Description

一种阵列基板、显示面板及显示装置
技术领域
本发明涉及显示技术领域，特别是涉及一种阵列基板、显示面板及显示装置。
背景技术
集成成像显示技术是一种无须任何助视设备(例如偏振眼镜)的裸眼立体显示，在显示过程中，显示面板中的像素单元发出的光线通过对应的透镜投射至人眼观测范围，通过对像素单元进行特定的图像渲染，使得左右眼分别接收到不同的图像，从而形成立体视觉。
现有的显示面板中的阵列基板，如图1所示，其包括薄膜晶体管T、像素电极A、栅线，如Gm-1、Gm、Gm+1，以及数据线，如Sn-1、Sn、Sn+1，像素电极A均匀地分布在阵列基板中，各个像素单元对应的像素电极A被栅线及数据线分隔，像素电极A之间距离较大，相同面积内含有像素电极A数量较少。
当采用现有的阵列基板应用于集成成像显示系统时，往往有大量的像素电极对应的像素单元处于关闭状态，造成像素电极的利用率低，像素电极的解析度提升难度较大，集成成像显示效果较差。
发明内容
本发明提供一种阵列基板、显示面板及显示装置，以解决现有的阵列基板应用于集成成像显示系统时，像素电极的利用率低，像素电极的解析度提升难度较大，集成成像显示效果较差的问题。
为了解决上述问题，本发明公开了一种阵列基板，包括：多个像素区域，所述像素区域包括设置在显示区的像素组以及设置在盲区的与所述像素组一一对应的驱动电路单元，在相邻的两行像素组之间设置有栅线，在相邻的两列像素组之间设置有数据线；
每个像素组包括至少两个像素电极，所述驱动电路单元包括驱动元件，所述驱动元件与所述栅线、所述数据线以及所述像素电极连接；
其中，所述驱动元件的数量与所述每个像素组中的像素电极的数量一致。
优选地，所述驱动元件包括驱动晶体管，所述驱动晶体管的栅极与所述栅线连接，所述驱动晶体管的第一极与所述数据线连接，所述驱动晶体管的第二极通过电极连接线与所述像素电极连接。
优选地，当所述每个像素组包括M×N个像素电极时，相邻的两行像素组之间的栅线为M个，相邻的两列像素组之间的数据线为N个；其中，M为大于1的正整数，N为大于或等于1的正整数，或者，M为大于或等于1的正整数，N为大于1的正整数。
优选地，所述阵列基板还包括复用线以及与所述复用线连接的复用连接线；所述驱动元件包括驱动晶体管和复用晶体管；
所述驱动晶体管的栅极与所述栅线连接，所述驱动晶体管的第一极与所述复用晶体管的第二极连接，所述驱动晶体管的第二极通过电极连接线与所述像素电极连接；
所述复用晶体管的栅极与所述复用连接线连接，所述复用晶体管的第一极与所述数据线连接。
优选地，当所述每个像素组包括M×N个像素电极时，相邻的两行像素组之间的栅线为M个，所述复用线的数量为N个，所述复用连接线的数量为M×N个，相邻的两列像素组之间的数据线为1个。
优选地，所述电极连接线的材料为透明导电材料。
优选地，所述透明导电材料为氧化铟锡或氧化铟锌。
为了解决上述问题，本发明还公开了一种显示面板，包括上述的阵列基板。
为了解决上述问题，本发明还公开了一种显示装置，包括上述的显示面板。
优选地，所述显示装置还包括透镜阵列，所述透镜阵列位于所述显示面板的出光侧，且所述透镜阵列与所述像素组的位置相对应；
所述透镜阵列，被配置为将显示面板中所述像素组对应的像素单元发出的光投射至人眼观测范围。
与现有技术相比，本发明包括以下优点：
通过在阵列基板中设置多个像素区域，每个像素区域包括设置在显示区的像素组以及设置在盲区的与像素组一一对应的驱动电路单元，在相邻的两行像素组之间设置有栅线，在相邻的两列像素组之间设置有数据线，每个像素组包括至少两个像素电极，驱动电路单元包括驱动元件，驱动元件与栅线、数据线以及像素电极连接。通过在显示区设置像素组，在盲区设置驱动电路单元，像素组内的像素电极之间无栅线及数据线，使得像素电极的排布更加紧密，像素组内像素电极的解析度显著提高，提高了集成成像的显示效果。
附图说明
图1示出了现有的一种阵列基板的结构示意图；
图2示出了本发明实施例的一种阵列基板的结构示意图；
图3示出了图2中的一个像素区域的局部示意图；
图4示出了本发明实施例的另一种阵列基板的结构示意图；
图5示出了图4中的一个像素区域的局部示意图；
图6示出了图5所示的阵列基板中像素电极的驱动时序图；
图7示出了本发明实施例的一种显示装置的结构示意图。
具体实施方式
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图和具体实施方式对本发明作进一步详细的说明。
实施例一
参照图2，示出了本发明实施例的一种阵列基板的结构示意图，图3示出了图2中的一个像素区域的局部示意图，图4示出了本发明实施例的另一种阵列基板的结构示意图，图5示出了图4中的一个像素区域的局部示意图。
如图2至图5所示，本发明实施例提供了一种阵列基板，包括：多个像素区域20，像素区域20包括设置在显示区的像素组21以及设置在盲区的与像素组21一一对应的驱动电路单元22，在邻的两行像素组21之间设置有栅线，如图2和图3中的栅线Gm-1、Gm和Gm+1，如图4和图5中的栅线G1、G2和G3，在相邻的两列像素组21之间设置有数据线，如图2和图3中的数据线Sn-1，Sn和Sn+1，如图4和图5中的数据线S1和S2。
每个像素组21包括至少两个像素电极A，驱动电路单元22包括驱动元件T，驱动元件T与栅线、数据线以及像素电极A连接；其中，驱动元件T的数量与每个像素组21中的像素电极A的数量一致。
在本发明实施例中，一个像素组21和一个驱动电路单元22组成一个像素区域20，多个像素区域20布置在阵列基板中，每个像素组21内包含至少两个紧密排布的像素电极A，驱动电路单元22设置在相邻的两行像素组21之间，其中，每个像素组21内的像素电极A之间没有设置栅线和数据线，使得像素电极A的排布更加紧密，像素组21内像素电极A的解析度显著提高。
当采用本发明的阵列基板应用于集成成像显示系统时，通过将像素组21设置在显示区，将驱动电路单元22设置在盲区，位于显示区的像素电极A对应的像素单元处于开启状态，使得像素电极的利用率提高，可有效提高集成成像的显示效果。
在本发明的一种实施例中，如图3所示，驱动元件T包括驱动晶体管T1，驱动晶体管T1的栅极与栅线连接，驱动晶体管T1的第一极与数据线连接，驱动晶体管T1的第二极通过电极连接线C与像素电极A连接。
当每个像素组21包括M×N个像素电极A时，相邻的两行像素组21之间的栅线为M个，相邻的两列像素组21之间的数据线为N个；其中，M为大于1的正整数，N为大于或等于1的正整数，或者，M为大于或等于1的正整数，N为大于1的正整数。
如图3所示，当每个像素组21包括3×3个像素电极A时，相邻的两行像素组21之间的栅线为3个，分别为栅线Gm-1、Gm和Gm+1，相邻的两列像素组21之间的数据线也为3个，分别为数据线Sn-1，Sn和Sn+1。
需要说明的是，每个像素组21内的像素电极A的数量不仅仅如图3所示的9个，每个像素组21包括至少两个像素电极A，如每个像素组21包括4个像素电极A、8个像素电极A或两个像素电极A，当每个像素组21包括两个像素电极A时，其排布方式可以为2×1，即两个像素电极A设置成两行，每行只设置一个像素电极A，此时，M为2，N为1，其排布方式还可以为1×2，即两个像素电极A设置成两列，每列只设置一个像素电极A，此时，M为1，N为2。
当需要对像素电极A充电时，向栅线输入栅极信号，控制驱动晶体管T1打开，向数据线输入数据电压，驱动晶体管T1将数据电压充至像素电极A。
例如，针对图3中的第二行第一列的像素电极A，向栅线Gm输入栅极信号，控制驱动电路单元22中第二行第一列的驱动晶体管T1打开，向数据线Sn-1写入数据电压，第二行第一列的驱动晶体管T1将数据电压充至第二行第一列的像素电极A。
在本发明的另一种实施例中，如图5所示，阵列基板还包括复用线以及与复用线连接的复用连接线，驱动元件T包括驱动晶体管T1和复用晶体管T2；驱动晶体管T1的栅极与栅线连接，驱动晶体管T1的第一极与复用晶体管T2的第二极连接，驱动晶体管T1的第二极通过电极连接线C与像素电极A连接；复用晶体管T2的栅极与复用连接线连接，复用晶体管T2的第一极与数据线连接。
当每个像素组21包括M×N个像素电极时，相邻的两行像素组21之间的栅线为M个，复用线的数量为N个，复用连接线的数量为M×N个，相邻的两列像素组之间的数据线为1个。
其中，M为大于1的正整数，N为大于或等于1的正整数，或者，M为大于或等于1的正整数，N为大于1的正整数。
如图5所示，当每个像素组21包括3×3个像素电极A时，相邻的两行像素组21之间的栅线为3个，分别为栅线G1、栅线G2和栅线G3，复用线的数量为3个，分别为复用线MUX1、复用线MUX2和复用线MUX3，复用连接线的数量为9个，分别为与复用线MUX1连接的复用连接线L11、复用连接线L12和复用连接线L13，与复用线MUX2连接的复用连接线L21、复用连接线L22和复用连接线L23，与复用线MUX3连接的复用连接线L31、复用连接线L32和复用连接线L33，相邻的两列像素组之间的数据线为1个，为数据线S1。
需要说明的是，每个像素组21内的像素电极A的数量不仅仅如图5所示的9个，每个像素组21包括至少两个像素电极A，如每个像素组21包括8个像素电极A，像素电极A的排布为4×2，即每行像素电极A的数量为2个，共有4行像素电极A，此时，相邻的两行像素组21之间的栅线为4个，复用线的数量为2个，复用连接线的数量为4×2个，相邻的两列像素组之间的数据线为1个。
参照图6，示出了图5所示的阵列基板的驱动时序图。
针对图5中的栅线G1，在时间段t内，栅线G1输入的栅极信号为高电平，数据线S1输入的数据电压为高电平或低电平，当栅线G1输入的栅极信号为高电平时，控制第一行的所有驱动晶体管T1打开。
在第一时间段t1内，复用线MUX1输入的复用信号为高电平，则与复用线MUX1连接的复用连接线L11也对应输入高电平信号，进而控制第一行第一列的复用晶体管T2打开，当第一行第一列的复用晶体管T2打开时，将数据线S1输入的数据电压转写至第一行第一列的驱动晶体管T1的第一极，由于第一行第一列的驱动晶体管T1处于打开状态，则第一行第一列的驱动晶体管T1将数据电压充至第一行第一列的像素电极A。
在第二时间段t2内，复用线MUX2输入的复用信号为高电平，则与复用线MUX2连接的复用连接线L12也对应输入高电平信号，进而控制第一行第二列的复用晶体管T2打开，当第一行第二列的复用晶体管T2打开时，将数据线S1输入的数据电压转写至第一行第二列的驱动晶体管T1的第一极，由于第一行第二列的驱动晶体管T1处于打开状态，则第一行第二列的驱动晶体管T1将数据电压充至第一行第二列的像素电极A。
在第二时间段t3内，复用线MUX3输入的复用信号为高电平，则与复用线MUX3连接的复用连接线L13也对应输入高电平信号，进而控制第一行第三列的复用晶体管T2打开，当第一行第三列的复用晶体管T2打开时，将数据线S1输入的数据电压转写至第一行第三列的驱动晶体管T1的第一极，由于第一行第三列的驱动晶体管T1处于打开状态，则第一行第三列的驱动晶体管T1将数据电压充至第一行第三列的像素电极A。
接着，向栅线G2输入高电平的栅极信号，依次向第二行第一列的像素电极A、第二行第二列的像素电极A和第二行第三列的像素电极A充电；相应的，最后向栅线G3输入高电平的栅极信号，依次向第三行第一列的像素电极A、第三行第二列的像素电极A和第三行第三列的像素电极A充电。
需要说明的是，图6中的栅线G1表示阵列基板中的第一行栅线，用于控制第一行驱动晶体管T1的打开；数据线S1表示阵列基板中的第一列数据线，用于向对应连接的复用晶体管T2输入数据电压，数据线S1输入的数据电压可以为高电平，也可以为低电平，根据实际的需求来确定。
以上描述仅仅示出了一个像素区域的驱动方法，可以理解的是，对于阵列基板中的其他像素区域，对应参照上述的驱动方法即可。
通过在阵列基板中设置复用线、与复用线连接的复用连接线，以及复用晶体管T2，减少了阵列基板中的数据线，使得像素组内像素电极的解析度进一步得到提高。
需要说明的是，每个像素组21内包括M×N个像素电极时，只需在第一列像素电极A的左侧设置M个复用线，而相邻的两列像素组之间的数据线可以减少为1个，当然，M个复用线的位置也可设置在最后一列像素电极A的右侧。
在本发明实施例中，如图2和图3所示，由于改变了驱动元件的位置，则驱动晶体管T1的第一极与数据线之间的连接长度增加，因此，需要增加一道工艺制作连接驱动晶体管T1的第一极与数据线之间的数据连接线B，相应的，如图4和图5所示，也需要增加一道工艺制作连接复用晶体管T2的第一极与数据线之间的数据连接线B，数据连接线B的材料为金属材料，可以采用铝、钼、铜等金属材料，电极连接线C的材料也可以采用上述金属材料，优选地，电极连接线C的材料为透明导电材料，透明导电材料可采用ITO(Indium Tin Oxide，氧化铟锡)、IZO(Indium Zinc Oxide，氧化铟锌)等，采用透明导电材料制作形成电极连接线C，可保证像素组21内像素电极A的透过率。
此外，复用线、与复用线连接的复用连接线也可以采用上述金属材料。
如图3所示，数据线和数据连接线B这两种走线需要交叠设计，因此，在实际制作过程中，可采用两道掩膜板分别制作，如先制作形成数据线，再制作形成数据连接线B；当然，电极连接线C与数据连接线B，栅线与电极连接线C也需要交叠设计，因此，在实际制作过程中，也需采用掩膜板分别制作，关于数据线、数据连接线B、电极连接线C和栅线的具体制作工艺顺序本发明实施例对此不做限制。
如图5所示，复用线与复用连接线这两种走线需要交叠设计，电极连接线C与数据连接线B、电极连接线C与栅线以及复用连接线也需交叠设计，因此，在实际制作过程中，也需采用掩膜板分别制作。
在本发明实施例中，通过在阵列基板中设置多个像素区域，每个像素区域包括设置在显示区的像素组以及设置在盲区的与像素组一一对应的驱动电路单元，在相邻的两行像素组之间设置有栅线，在相邻的两列像素组之间设置有数据线，每个像素组包括至少两个像素电极，驱动电路单元包括驱动元件，驱动元件与栅线、数据线以及像素电极连接。通过在显示区设置像素组，在盲区设置驱动电路单元，像素组内的像素电极之间无栅线及数据线，使得像素电极的排布更加紧密，像素组内像素电极的解析度显著提高，提高了集成成像的显示效果。
实施例二
本发明实施例还提供了一种显示面板，包括上述的阵列基板。
关于阵列基板的具体描述可以参照实施例一的描述，本发明实施例对此不再赘述。
通过采用实施例一中的阵列基板制作形成显示面板，在像素组21内的像素电极A对应的位置处可形成像素单元，当向像素组21内的像素电极A充电时，像素单元可发出光线。
在本发明实施例中，显示面板包括阵列基板，通过在阵列基板中设置多个像素区域，每个像素区域包括设置在显示区的像素组以及设置在盲区的与像素组一一对应的驱动电路单元，在相邻的两行像素组之间设置有栅线，在相邻的两列像素组之间设置有数据线，每个像素组包括至少两个像素电极，驱动电路单元包括驱动元件，驱动元件与栅线、数据线以及像素电极连接。通过在显示区设置像素组，在盲区设置驱动电路单元，像素组内的像素电极之间无栅线及数据线，使得像素电极的排布更加紧密，像素组内像素电极的解析度显著提高，提高了集成成像的显示效果。
实施例三
参照图7，示出了本发明实施例的一种显示装置的结构示意图。
本发明实施例另外提供了一种显示装置，包括上述的显示面板30，该显示面板30包括上述的阵列基板。
此外，显示装置还包括透镜阵列40，透镜阵列40位于显示面板30的出光侧，且透镜阵列40与像素组21的位置相对应，透镜阵列40，被配置为将显示面板30中像素组21对应的像素单元发出的光投射至人眼观测范围50。
其中，透镜阵列40包括多个微透镜41，每个微透镜41对应一个像素组21，该像素组21内的像素电极A对应的像素单元发出的光被微透镜41投射至人眼观测范围50，左眼51和右眼52分别接收到一个像素组21对应的至少一个像素单元发出的光线。
如图7所示，一个像素组21内对应的像素单元从上至下分别为第一像素单元、第二像素单元和第三像素单元，左眼51接收到第一像素单元形成的图像，右眼52接收到第三像素单元形成的图像，第二像素单元形成的图像位于左眼51和右眼52之间，当人眼移动至该位置时将被人眼接收到，通过对第一像素单元、第二像素单元和第三像素单元进行特定的图像渲染，左眼51和右眼52将分别接收到不同的图像，从而形成立体视觉。
将像素组21设置在透镜成像的显示区，驱动电路单元22设置在透镜成像的盲区，即处于关闭状态的像素区域，因此，像素电极A集中位于透镜成像的显示区，使得像素电极的利用率提高，可有效提高集成成像的显示效果。
本发明实施例中，显示装置包括显示面板，显示面板包括阵列基板，通过在阵列基板中设置多个像素区域，每个像素区域包括设置在显示区的像素组以及设置在盲区的与像素组一一对应的驱动电路单元，在相邻的两行像素组之间设置有栅线，在相邻的两列像素组之间设置有数据线，每个像素组包括至少两个像素电极，驱动电路单元包括驱动元件，驱动元件与栅线、数据线以及像素电极连接。通过在显示区设置像素组，在盲区设置驱动电路单元，像素组内的像素电极之间无栅线及数据线，使得像素电极的排布更加紧密，像素组内像素电极的解析度显著提高，提高了集成成像的显示效果。
本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
最后，还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、商品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、商品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、商品或者设备中还存在另外的相同要素。
以上对本发明所提供的一种阵列基板、显示面板及显示装置，进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的一般技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (10)

1.一种阵列基板，其特征在于，包括：多个像素区域，所述像素区域包括设置在显示区的像素组以及设置在盲区的与所述像素组一一对应的驱动电路单元，在相邻的两行像素组之间设置有栅线，在相邻的两列像素组之间设置有数据线；
每个像素组包括至少两个像素电极，所述驱动电路单元包括驱动元件，所述驱动元件与所述栅线、所述数据线以及所述像素电极连接；
其中，所述驱动元件的数量与所述每个像素组中的像素电极的数量一致。
2.根据权利要求1所述的阵列基板，其特征在于，所述驱动元件包括驱动晶体管，所述驱动晶体管的栅极与所述栅线连接，所述驱动晶体管的第一极与所述数据线连接，所述驱动晶体管的第二极通过电极连接线与所述像素电极连接。
3.根据权利要求2所述的阵列基板，其特征在于，当所述每个像素组包括M×N个像素电极时，相邻的两行像素组之间的栅线为M个，相邻的两列像素组之间的数据线为N个；其中，M为大于1的正整数，N为大于或等于1的正整数，或者，M为大于或等于1的正整数，N为大于1的正整数。
4.根据权利要求1所述的阵列基板，其特征在于，所述阵列基板还包括复用线以及与所述复用线连接的复用连接线；所述驱动元件包括驱动晶体管和复用晶体管；
所述驱动晶体管的栅极与所述栅线连接，所述驱动晶体管的第一极与所述复用晶体管的第二极连接，所述驱动晶体管的第二极通过电极连接线与所述像素电极连接；
所述复用晶体管的栅极与所述复用连接线连接，所述复用晶体管的第一极与所述数据线连接。
5.根据权利要求4所述的阵列基板，其特征在于，当所述每个像素组包括M×N个像素电极时，相邻的两行像素组之间的栅线为M个，所述复用线的数量为N个，所述复用连接线的数量为M×N个，相邻的两列像素组之间的数据线为1个。
6.根据权利要求3或5所述的阵列基板，其特征在于，所述电极连接线的材料为透明导电材料。
7.根据权利要求6所述的阵列基板，其特征在于，所述透明导电材料为氧化铟锡或氧化铟锌。
8.一种显示面板，其特征在于，包括如权利要求1-7中任一项所述的阵列基板。
9.一种显示装置，其特征在于，包括如权利要求8所述的显示面板。
10.根据权利要求9所述的显示装置，其特征在于，所述显示装置还包括透镜阵列，所述透镜阵列位于所述显示面板的出光侧，且所述透镜阵列与所述像素组的位置相对应；
所述透镜阵列，被配置为将显示面板中所述像素组对应的像素单元发出的光投射至人眼观测范围。
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