CN108598236A - A kind of LED epitaxial slice and preparation method thereof - Google Patents

Abstract

The invention discloses a light-emitting diode epitaxial wafer and a manufacturing method thereof, belonging to the technical field of semiconductors. The epitaxial wafer includes a substrate, a buffer layer, an N-type semiconductor layer, an active layer, and a P-type semiconductor layer. The buffer layer is laid on the substrate, and the first surface of the N-type semiconductor layer is laid on the buffer layer. The second surface includes protrusions and depressions, the second surface is the surface opposite to the first surface; the active layer is laid on the protrusions and the depressions, the P-type semiconductor layer is laid on the active layer, and the P-type semiconductor The sum of the thicknesses of the layer and the active layer is smaller than the height of the raised portion. In the present invention, the surface of the N-type semiconductor layer on which the active layer is arranged is changed from flat to uneven, thereby increasing the light-emitting area of the active layer and improving the luminous brightness of the LED; at the same time, changing the outgoing direction of the light emitted by the active layer is beneficial Improve the light-emitting efficiency of the LED, and then improve the luminous efficiency of the LED.

Description

A light-emitting diode epitaxial wafer and its manufacturing method

technical field

The invention relates to the technical field of semiconductors, in particular to a light-emitting diode epitaxial wafer and a manufacturing method thereof.

Background technique

A light-emitting diode (English: Light Emitting Diode, referred to as: LED) is a semiconductor electronic component that can emit light. LED has attracted wide attention due to its advantages of energy saving, environmental protection, high reliability, and long service life. For civil lighting, luminous efficiency and service life are the main criteria, so increasing the luminous efficiency of LEDs and improving the antistatic ability of LEDs is particularly critical for the wide application of LEDs.

Epitaxial wafers are the primary products in the LED manufacturing process. The existing LED epitaxial wafer includes a substrate, a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer, and the buffer layer, the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially stacked on the substrate. The substrate is used to provide a growth surface for epitaxial materials, the buffer layer is used to alleviate the lattice mismatch between the substrate and the N-type semiconductor layer, the N-type semiconductor layer is used to provide electrons for recombination and light emission, and the active layer is used to perform The recombination of electrons and holes emits light, and the P-type semiconductor layer is used to provide holes for recombination and light emission.

In the process of realizing the present invention, the inventor finds that there are at least the following problems in the prior art:

The holes provided by the P-type semiconductor layer and the electrons provided by the N-type semiconductor layer are injected into the active layer for composite light emission. The N-type semiconductor layer, the active layer and the P-type semiconductor layer are stacked in sequence. The light-emitting area of the active layer is limited, and the light output angle It is also limited, resulting in low luminous efficiency of LEDs.

Contents of the invention

In order to solve the problems in the prior art, an embodiment of the present invention provides a light emitting diode epitaxial wafer and a manufacturing method thereof. Described technical scheme is as follows:

On the one hand, an embodiment of the present invention provides a light-emitting diode epitaxial wafer, the light-emitting diode epitaxial wafer includes a substrate, a buffer layer, an N-type semiconductor layer, an active layer, and a P-type semiconductor layer, and the buffer layer is laid on the On the above substrate, the first surface of the N-type semiconductor layer is laid on the buffer layer, the second surface of the N-type semiconductor layer includes protrusions and depressions, and the second surface is compatible with the The surface opposite to the first surface; the active layer is laid on the raised portion and the depressed portion, the P-type semiconductor layer is laid on the active layer, the P-type semiconductor layer and the The sum of the thicknesses of the active layers is smaller than the height of the protrusions.

Optionally, the height of the raised portion is 2 μm˜8 μm.

Preferably, the raised portion includes a curved surface, the curved surface intersects the concave portion, and an angle between a tangent plane of each point on the curved surface and the concave portion is an obtuse angle.

More preferably, the raised portion further includes a plane, the plane is parallel to the concave portion, and the plane intersects the curved surface.

Optionally, the distance between the depression and the first surface is 1 μm˜3 μm.

Optionally, the number of the protrusions is multiple, and the plurality of protrusions are arranged in the depressions in an array; or, the number of the depressions is multiple, and the plurality of depressions The portions are arranged in the raised portion in an array.

On the other hand, an embodiment of the present invention provides a method for manufacturing a light-emitting diode epitaxial wafer, and the method includes:

growing a buffer layer on the substrate;

growing an N-type semiconductor layer on the buffer layer;

patterning the N-type semiconductor layer by using photolithography technology and etching technology, and forming protrusions and depressions on the surface of the N-type semiconductor layer;

growing an active layer on the raised portion and the depressed portion;

A P-type semiconductor layer is grown on the active layer, and the sum of the thicknesses of the P-type semiconductor layer and the active layer is smaller than the height of the raised portion.

Optionally, the patterning of the N-type semiconductor layer by using photolithography technology and etching technology to form protrusions and depressions on the surface of the N-type semiconductor layer includes:

A photoresist with a set pattern is formed on the N-type semiconductor layer by photolithography technology, and the photoresist includes a plurality of glue blocks arranged in an array on the N-type semiconductor layer, or the photoresist There are through holes arranged in an array in the resist;

The N-type semiconductor layer is patterned by an etching technique, and protrusions and depressions are formed on the surface of the N-type semiconductor layer.

Preferably, the photoresist has a thickness of 2 μm˜8 μm.

Preferably, the patterning of the N-type semiconductor layer by using an etching technique to form protrusions and depressions on the surface of the N-type semiconductor layer includes:

The N-type semiconductor layer is patterned by using a plasma etching process, and the ratio of the plasma components is controlled so that the tangent plane of each point on the curved surface intersecting the concave portion in the raised portion is aligned with the concave portion The angle between the parts is an obtuse angle.

The beneficial effects brought by the technical solution provided by the embodiments of the present invention are:

By changing the surface of the N-type semiconductor layer on the active layer from flat to uneven, the light-emitting area of the active layer is increased, and the luminous brightness of the LED is improved; at the same time, the direction of the light emitted by the active layer is changed, which is beneficial to improve the performance of the LED. Light extraction efficiency, and then improve the luminous efficiency of LED.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained based on these drawings without creative effort.

FIG. 1 is a schematic structural view of a light-emitting diode epitaxial wafer provided by an embodiment of the present invention;

Fig. 2 is a schematic structural view of another light-emitting diode epitaxial wafer provided by an embodiment of the present invention;

Fig. 3 is a schematic structural diagram of a protrusion provided by an embodiment of the present invention;

Fig. 4 is a schematic structural diagram of another protrusion provided by an embodiment of the present invention;

Fig. 5 is a schematic structural diagram of another raised portion provided by an embodiment of the present invention;

Fig. 6 is a flowchart of a method for manufacturing a light-emitting diode epitaxial wafer provided by an embodiment of the present invention;

7a-7e are structural schematic diagrams of the light-emitting diode epitaxial wafer provided by the embodiment of the present invention during the execution of the manufacturing method.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the implementation manner of the present invention will be further described in detail below in conjunction with the accompanying drawings.

An embodiment of the present invention provides a light-emitting diode epitaxial wafer. FIG. 1 is a schematic structural diagram of a light-emitting diode epitaxial wafer provided by an embodiment of the present invention. Referring to FIG. 1 , the light-emitting diode epitaxial wafer includes a substrate 10, a buffer layer 20, N-type semiconductor layer 30 , active layer 40 and P-type semiconductor layer 50 . The buffer layer 20 is laid on the substrate 10, the first surface of the N-type semiconductor layer 30 is laid on the buffer layer 20, the second surface of the N-type semiconductor layer 30 includes a protrusion 31 and a depression 32, and the second surface is the same as The surface opposite the first surface. The active layer 40 is laid on the raised portion 31 and the depressed portion 32, the P-type semiconductor layer 50 is laid on the active layer 40, and the sum of the thicknesses of the P-type semiconductor layer 50 and the active layer 40 is less than the height of the raised portion 31 .

In this embodiment, the sum of the thicknesses of the P-type semiconductor layer 50 and the active layer 40 is the sum of the laying depth of the active layer 40 and the laying depth of the P-type semiconductor layer 50; The height h of 31 is the maximum value of the distance between each point on the raised portion 31 and the plane where the depressed portion 32 is located.

In the embodiment of the present invention, the surface of the N-type semiconductor layer on which the active layer is arranged is changed from flat to uneven, thereby increasing the light-emitting area of the active layer and improving the luminous brightness of the LED; at the same time, changing the outgoing direction of the light emitted by the active layer, It is beneficial to improve the light-emitting efficiency of the LED, thereby improving the luminous efficiency of the LED.

In an implementation of this embodiment, as shown in FIG. 1, the number of raised portions 31 may be multiple, and the plurality of raised portions 31 are arranged in an array in the recessed portion 32. At this time, each raised portion The recessed portion 32 between 31 is connected.

In actual implementation, the heights of the plurality of protrusions are usually the same due to the limitation of the manufacturing process. If a plurality of protruding parts are arranged in an array in the concave part, the distance between two adjacent protruding parts is also the same. By uniformly setting the height of each raised portion and the distance between each raised portion, the raised portion can be fully used to increase the light-emitting area of the active layer and improve the light extraction efficiency of the LED, which is simpler and more convenient to implement.

FIG. 2 is a schematic structural diagram of another light-emitting diode epitaxial wafer provided by an embodiment of the present invention. In another implementation of this embodiment, referring to FIG. 2 , the number of recessed parts 32 may be multiple, and the plurality of recessed parts 32 are arranged in the raised part 31 in an array. At this time, between each recessed part 32 The raised portion 31 is connected.

In actual implementation, limited by the manufacturing process, the N-type semiconductor layer is usually grown first, and then the N-type semiconductor layer is etched to form protrusions and depressions on the surface of the N-type semiconductor layer. In the case where a plurality of depressed portions are arranged in the raised portion, compared with the case where a plurality of raised portions are arranged in the depressed portion, less N-type semiconductor layers need to be etched away to form the raised portion and the depressed portion, and the realization cost relatively low.

Moreover, limited by the manufacturing process, the depths of the plurality of depressions are usually the same, and if the plurality of depressions are arranged in the raised portion in an array, the distances between two adjacent depressions are also the same. By uniformly setting the heights of the depressions and the distances between the depressions, the protrusions can be fully used to increase the light-emitting area of the active layer and improve the light extraction efficiency of the LED, which is simpler and more convenient to implement.

Optionally, the height of the raised portion 31 may be 2 μm˜8 μm. If the height of the raised portion is less than 2 μm, it may be lower than the sum of the thicknesses of the active layer and the P-type semiconductor layer due to the height of the raised portion being too small, and the raised portion cannot be effectively used to increase the light emitting area of the active layer and improve the light extraction efficiency of the LED, or cause the thickness of at least one of the active layer and the P-type semiconductor layer to be too small to affect its own function, thereby affecting the luminous efficiency of the LED; if the height of the raised portion is greater than 8 μm, it may be due to the convex If the height of the raised portion is too large, the formation of the active layer and the P-type semiconductor layer on the raised portion will be affected, or the raised portion will be too large, and the effect of improving the luminous brightness and luminous efficiency of the LED is not ideal.

Specifically, the maximum distance between two points in the projection of the projection 31 on the plane where the depression 32 is located can be 200nm-4000nm, and the distance between two adjacent projections 31 can be 50nm-1500nm to match the convexity. The height of the raised portion is 2 μm to 8 μm.

Fig. 3 is a schematic structural diagram of a protrusion provided by an embodiment of the present invention. In an implementation of this embodiment, referring to FIG. 3 , the convex portion 31 may include a curved surface 31a, such as a spherical cap, the curved surface 31a intersects the concave portion 32, and the tangent plane of each point on the curved surface 31a and the concave portion 32 The included angle θ is an obtuse angle.

By defining the angle between the tangent plane of each point on the curved surface intersecting the concave portion and the concave portion as an obtuse angle, it is beneficial to lay the active layer on the concave portion, and facilitate the realization of the light-emitting diode epitaxial wafer provided by the embodiment of the present invention. .

Fig. 4 is a schematic structural diagram of another protrusion provided by an embodiment of the present invention. Further, referring to FIG. 4 , the raised portion 31 may further include a plane 31b, such as the upper surface of a circular truncated portion, the plane 31b is parallel to the concave portion 32, and the plane 31b intersects the curved surface 31a.

By arranging a plane parallel to the recessed portion, it is beneficial to increase the front light output of the LED.

It is easy to know that the area of the plane 31 b is smaller than the area of the projection of the protrusion 31 on the plane where the depression 32 is located.

Fig. 5 is a schematic structural diagram of another protrusion provided by an embodiment of the present invention. In yet another implementation of this embodiment, referring to FIG. 5 , the raised portion 31 may include a plane 31c and a connecting surface 31d, the plane 31c is parallel to the recessed portion 32, and the connecting surface 31d is perpendicular to the plane 31c and the recessed portion 32 respectively. intersect.

Specifically, the connection surface 31d may be a curved surface, or may include a plurality of planes connected end-to-end, which may be selected according to the shape of the plane 31c. For example, if the shape of the plane 31c is circular, then the connecting surface 31d is a curved surface; for another example, if the shape of the plane 31c is rectangular, then the connecting surface 31d includes four planes connected end to end.

Optionally, as shown in FIG. 1 , the distance d between the concave portion 32 and the first surface is 1 μm˜3 μm. If the distance between the depression and the first surface is less than 1 μm, it may not be able to provide a sufficient number of electrons due to the too small thickness of the N-type semiconductor layer under the depression, which will affect the luminous efficiency of the LED; if the distance between the depression and the first surface If the distance is greater than 3 μm, it may cause waste of materials, and may also affect the number of electrons provided by the N-type semiconductor layer under the raised portion, which is not conducive to the raised portion improving the luminous brightness and light extraction efficiency of the LED.

Specifically, the material of the substrate 10 can be sapphire. The material of the buffer layer 20 can be gallium nitride (GaN). The material of the N-type semiconductor layer 30 can be N-type doped gallium nitride. The active layer 40 can include multiple quantum wells and multiple quantum barriers, and multiple quantum wells and multiple quantum barriers are alternately stacked; the material of the quantum wells can be indium gallium nitride (InGaN), and the material of the quantum barriers can be nitrogen gallium chloride. The material of the P-type semiconductor layer 50 can be P-type doped gallium nitride.

In the specific implementation, a thin layer of gallium nitride is first grown on the substrate at low temperature, which is called a low-temperature buffer layer; and then vertical growth of gallium nitride is performed on the low-temperature buffer layer to form multiple independent three-dimensional islands. structure, called a three-dimensional growth layer; then lateral growth of gallium nitride is performed on all three-dimensional island structures and between each three-dimensional island structure to form a two-dimensional planar structure, called a two-dimensional growth layer; finally in two-dimensional growth A thick layer of gallium nitride is grown on the high temperature layer, which is called a high temperature buffer layer. In this embodiment, one or more of the low-temperature buffer layer, the three-dimensional growth layer, the two-dimensional growth layer and the high-temperature buffer layer are collectively referred to as a buffer layer.

Further, the number of quantum wells is the same as the number of quantum barriers, and the number of quantum barriers may be 5-11. The doping concentration of the N-type dopant in the N-type semiconductor layer 30 may be 10 ¹⁸ cm ⁻³ to 10 ²⁰ cm ⁻³ ; the doping concentration of the P-type dopant in the P-type semiconductor layer 50 may be 10 ¹⁸ cm ^{−3 3} ~ 10 ²⁰ cm ^-3 .

Optionally, as shown in FIG. 1 and FIG. 2, the light emitting diode epitaxial wafer may further include a stress release layer 60, and the stress release layer 60 is arranged between the N-type semiconductor layer 30 and the active layer 40 to release the epitaxial growth process. The stress and defects generated in the film can improve the growth quality of the active layer, thereby improving the luminous efficiency of the LED.

In this embodiment, the stress release layer 60 is laid on the raised portion 31 and the recessed portion 32, the active layer 40 is laid on the stress release layer 60, the stress release layer 60, the active layer 40 and the P-type semiconductor layer 50 The sum of the thicknesses is smaller than the height of the raised portion 31 .

Specifically, the stress release layer 60 may include a plurality of first sublayers and a plurality of second sublayers, and a plurality of first sublayers and a plurality of second sublayers are alternately stacked; the material of the first sublayer may be nitrided For indium gallium, gallium nitride may be used as a material for the second sublayer.

Optionally, as shown in FIG. 1 and FIG. 2, the light emitting diode epitaxial wafer may further include an electron blocking layer 70, and the electron blocking layer 70 is arranged between the active layer 40 and the P-type semiconductor layer 50, so as to prevent electrons from transitioning to The non-radiative recombination of holes in the P-type semiconductor layer affects the luminous efficiency of the LED.

In this embodiment, the electron blocking layer 70 is laid on the active layer 40, the P-type semiconductor layer 50 is laid on the electron blocking layer 70, and the sum of the thicknesses of the active layer 40, the electron blocking layer 70 and the P-type semiconductor layer 50 less than the height of the raised portion 31.

Specifically, the material of the electron blocking layer 70 may be P-type doped aluminum gallium nitride (AlGaN).

Further, the material of the electron blocking layer 70 can be P-type doped _{AlyGa1 -yN} , 0.1<y<0.5.

Preferably, as shown in FIG. 1 and FIG. 2, the light emitting diode epitaxial wafer may further include a low-temperature P-type layer 80, and the low-temperature P-type layer 80 is arranged between the active layer 40 and the electron blocking layer 70 to relieve the P-type semiconductor The effect of high temperature growth of layer 50 on the active layer.

In this embodiment, the low-temperature P-type layer 80 is laid on the active layer 40, and the electron blocking layer 70 is laid on the low-temperature P-type layer 80. The active layer 40, the low-temperature P-type layer 80, the electron blocking layer 70 and the P The sum of the thicknesses of the type semiconductor layers 50 is smaller than the height of the raised portion 31.

Specifically, the material of the low-temperature P-type layer 80 may be P-type doped gallium nitride.

Further, the doping concentration of the P-type dopant in the low-temperature P-type layer 80 may be 10 ¹⁸ cm ⁻³ to 10 ²⁰ cm ⁻³ .

Optionally, as shown in Figures 1 and 2, the light emitting diode epitaxial wafer may further include a P-type contact layer 90, which is laid on the P-type semiconductor layer 50 so as to be compatible with the transparent semiconductor layer formed in the chip manufacturing process. Ohmic contacts are formed between the conductive films.

Specifically, the material of the P-type contact layer 90 may be P-type doped InGaN.

It should be noted that the sum of the thicknesses of all layers above the active layer including the active layer is smaller than the height of the protrusion.

An embodiment of the present invention provides a method for manufacturing a light-emitting diode epitaxial wafer, which is suitable for manufacturing the light-emitting diode epitaxial wafer shown in FIG. 1 or FIG. 2 . Fig. 6 is a flowchart of a method for manufacturing a light-emitting diode epitaxial wafer provided by an embodiment of the present invention. Referring to Fig. 6, the method includes:

Step 101: growing a buffer layer on a substrate.

Fig. 7a is a schematic structural diagram of the light emitting diode epitaxial wafer provided by the embodiment of the present invention after step 101 is performed. Wherein, 10 represents a substrate, and 20 represents a buffer layer. As shown in FIG. 7 a , the buffer layer 20 is laid on one surface of the substrate 10 .

Optionally, the preparation method may also include:

annealing the substrate in a hydrogen atmosphere for 1 to 10 minutes;

Nitriding treatment is performed at a temperature of 1000°C to 1200°C.

Further, the substrate may be sapphire with [0001] crystal orientation.

Step 102: growing an N-type semiconductor layer on the buffer layer.

Fig. 7b is a schematic structural diagram of the light emitting diode epitaxial wafer provided by the embodiment of the present invention after step 102 is performed. Wherein, 30 represents an N-type semiconductor layer. As shown in FIG. 7 b , the N-type semiconductor layer 70 is laid on one surface of the buffer layer 20 , and the surface of the buffer layer 20 on which the N-type semiconductor layer 30 is laid is opposite to the surface on which the buffer layer 20 is laid on the substrate 10 .

Step 103: Patterning the N-type semiconductor layer by using photolithography and etching techniques to form protrusions and depressions on the surface of the N-type semiconductor layer.

Fig. 7c is a schematic structural diagram of the light emitting diode epitaxial wafer provided by the embodiment of the present invention after step 103 is performed. Wherein, 31 denotes a convex portion, and 32 denotes a concave portion. As shown in Figure 7c, the protruding portion 31 and the recessed portion 32 are formed on the same surface of the N-type semiconductor layer 30, and the surface of the N-type semiconductor layer 30 forming the protruding portion 31 and the recessed portion 32 is paved with the N-type semiconductor layer 30. The surface on the buffer layer 20 is reversed.

In an implementation manner of this embodiment, step 103 may include:

A photoresist with a predetermined pattern is formed on the N-type semiconductor layer by photolithography technology, and the photoresist includes a plurality of rubber blocks arranged in an array on the N-type semiconductor layer;

The N-type semiconductor layer is patterned by using an etching technique, and protrusions and depressions are formed on the surface of the N-type semiconductor layer.

Further, the angle between the side surface of the rubber block and the bottom surface of the rubber block may be an acute angle.

In another implementation manner of this embodiment, step 103 may include:

A photoresist with a predetermined pattern is formed on the N-type semiconductor layer by photolithography technology, and through holes arranged in an array are arranged in the photoresist;

The N-type semiconductor layer is patterned by using an etching technique, and protrusions and depressions are formed on the surface of the N-type semiconductor layer.

Further, the included angle between the sidewall of the through hole and the bottom surface of the photoresist may be an acute angle.

By forming photoresists with different patterns, multiple protrusions or multiple depressions are formed on the surface of the N-type semiconductor layer.

Specifically, when photolithography technology is used to form a photoresist with a set pattern, a layer of photoresist is first laid, and then the photoresist is exposed under the shield of the mask plate with the set pattern, and then the exposed light is The resist is soaked in the developer solution, and the exposed or unexposed parts of the photoresist will dissolve into the developer solution, thereby forming a photoresist with a set pattern.

In the above two implementations, the thickness of the photoresist can be 2 μm to 8 μm to form a raised portion with a height of 2 μm to 8 μm to ensure that the height of the raised portion is greater than the thickness of the active layer and the P-type semiconductor layer. and.

Optionally, patterning the N-type semiconductor layer by using an etching technique to form protrusions and depressions on the surface of the N-type semiconductor layer may include:

Use a plasma etching process to pattern the N-type semiconductor layer, and control the proportion of plasma components, so that the angle between the tangent plane of each point on the curved surface intersecting the convex part and the concave part and the concave part is an obtuse angle .

By controlling the ratio of the plasma components to achieve a high etching rate, the shape control of the raised part is realized, so that the angle between the tangent plane of each point on the curved surface intersecting the raised part and the depressed part and the depressed part is an obtuse angle, It is beneficial for the subsequent active layer and the like to grow on the raised portion.

Step 104: growing an active layer on the protrusion and the depression.

FIG. 7d is a schematic structural diagram of the light emitting diode epitaxial wafer provided by the embodiment of the present invention after step 104 is performed. Wherein, 40 represents an active layer. As shown in FIG. 7 d , the active layer 40 is laid on the raised portion 31 and the depressed portion 32 .

Optionally, before step 104, the manufacturing method may also include:

A stress relief layer is grown on the protrusions and depressions.

Accordingly, the active layer is grown on the stress release layer.

Step 105: growing a P-type semiconductor layer on the active layer, the sum of the thicknesses of the P-type semiconductor layer and the active layer being smaller than the height of the protrusion.

FIG. 7e is a schematic structural diagram of the light emitting diode epitaxial wafer provided by the embodiment of the present invention after step 105 is performed. Wherein, 50 represents a P-type semiconductor layer. As shown in FIG. 7 e , the P-type semiconductor layer 50 is laid on the active layer 40 .

Optionally, before step 105, the manufacturing method may also include:

An electron blocking layer is grown on the active layer.

Accordingly, the P-type semiconductor layer grows on the electron barrier.

Preferably, before growing the electron blocking layer on the active layer, the fabrication method may further include:

A low temperature P-type layer is grown on the active layer.

Correspondingly, an electron blocking layer is grown on the low temperature P-type layer.

Optionally, after step 105, the manufacturing method may also include:

A P-type contact layer is grown on the P-type semiconductor layer.

Preferably, a P-type contact layer is grown on the P-type semiconductor layer, and the manufacturing method may also include:

The temperature is controlled at 650° C. to 850° C., the duration is 5 minutes to 15 minutes, and the annealing treatment is performed in a nitrogen atmosphere.

It should be noted that controlling the temperature and pressure both refers to controlling the temperature and pressure in the reaction chamber for growing epitaxial wafers. When it is realized, trimethylgallium or trimethylethyl is used as the gallium source, high-purity nitrogen is used as the nitrogen source, trimethylindium is used as the indium source, trimethylaluminum is used as the aluminum source, the N-type dopant is silane, and the P-type dopant is silane. Miscellaneous agent selects dichloromagnesium for use.

The embodiment of the present invention provides another method for manufacturing a light-emitting diode epitaxial wafer, which is a specific implementation of the manufacturing method shown in FIG. 6 , and the manufacturing method includes:

Step 201: controlling the temperature to 400°C-600°C and the pressure to 100torr-300torr, and growing a low-temperature buffer layer with a thickness of 15nm-35nm on the substrate.

Step 202: Control the temperature to 1000°C-1100°C and the pressure to 100torr-500torr, and grow a three-dimensional growth layer with a thickness of 100nm-500nm on the low-temperature buffer layer.

Step 203: controlling the temperature to 1000° C. to 1200° C. and the pressure to 100 torr to 500 torr, and growing a two-dimensional growth layer with a thickness of 500 nm to 800 nm on the three-dimensional growth layer.

Step 204: Control the temperature to 1000°C-1200°C and the pressure to 100torr-500torr, and grow a high-temperature buffer layer with a thickness of 800nm-1200nm on the three-dimensional growth layer.

Step 205: controlling the temperature to 1000° C. to 1200° C. and the pressure to 100 torr to 500 torr, and growing an N-type semiconductor layer with a thickness of 9 μm to 11 μm on the high temperature buffer layer.

Step 206 : patterning the N-type semiconductor layer by using photolithography and etching techniques, forming protrusions and depressions on the surface of the N-type semiconductor layer, and the height of the protrusions is 2 μm˜8 μm.

Step 207: controlling the temperature to 800° C. to 1000° C. and the pressure to 100 torr to 500 torr, and growing a stress release layer with a thickness of 5 nm to 10 nm on the protrusions and depressions.

Step 208: Control the pressure to 100 torr to 500 torr, grow an active layer on the stress release layer, the active layer includes multiple quantum wells and multiple quantum barriers grown alternately, the thickness of the quantum wells is 3nm, and the growth temperature of the quantum wells is 720°C to 829°C, the thickness of the quantum barrier is 9nm to 12nm, and the growth temperature of the quantum barrier is 850°C to 959°C.

Step 209 : controlling the temperature to 600° C. to 800° C. and the pressure to 200 torr to 600 torr, and growing a low-temperature P-type layer with a thickness of 10 nm to 50 nm on the active layer.

Step 210: controlling the temperature to 850° C. to 950° C. and the pressure to 100 torr to 500 torr, and growing an electron blocking layer with a thickness of 50 nm to 150 nm on the low temperature P-type layer.

Step 211 : controlling the temperature to 800° C. to 1000° C. and the pressure to 100 torr to 300 torr, and growing a P-type semiconductor layer with a thickness of 100 nm to 500 nm on the electron blocking layer.

Step 212: Control the temperature to 850° C. to 1050° C. and the pressure to 100 torr to 300 torr, and grow a P-type contact layer with a thickness of 10 nm to 100 nm on the P-type semiconductor layer.

The embodiment of the present invention provides another method for manufacturing a light-emitting diode epitaxial wafer, which is another specific implementation of the manufacturing method shown in FIG. 6 . The manufacturing method includes:

Step 301 : controlling the temperature to 400° C. to 600° C. and the pressure to 400 torr to 600 torr, and growing a low temperature buffer layer with a thickness of 15 nm to 40 nm on the substrate.

Step 302: Control the temperature to 1000°C-1040°C and the pressure to 400torr-600torr, and grow a three-dimensional growth layer with a thickness of 400nm-600nm on the low-temperature buffer layer.

Step 303: controlling the temperature to 1040° C. to 1080° C. and the pressure to 400 torr to 600 torr, and growing a two-dimensional growth layer with a thickness of 500 nm to 800 nm on the three-dimensional growth layer.

Step 304: Control the temperature to 1050° C. to 1100° C. and the pressure to 100 torr to 500 torr, and grow a high temperature buffer layer with a thickness of 1 μm to 2 μm on the three-dimensional growth layer.

Step 305: Control the temperature to 1000°C-1100°C, the pressure to 100torr-500torr, grow an N-type semiconductor layer with a thickness of 9μm-11μm on the high-temperature buffer layer, and the doping concentration of the N-type dopant in the N-type semiconductor layer is 10 ¹⁸ cm ^-3 ～3*10 ¹⁹ cm ^-3 .

Step 306: Patterning the N-type semiconductor layer by using photolithography and etching techniques, forming protrusions and depressions on the surface of the N-type semiconductor layer, the height of the protrusions being 2 μm˜8 μm.

Step 307 : controlling the temperature to 800° C. to 1000° C. and the pressure to 100 torr to 500 torr, and growing a stress release layer with a thickness of 5 nm to 10 nm on the raised portion and the depressed portion.

Step 308: Control the pressure to 100 torr to 500 torr, grow an active layer on the stress release layer, the active layer includes multiple quantum wells and multiple quantum barriers grown alternately, the thickness of the quantum wells is 3nm to 4nm, the growth of the quantum wells The temperature is 720°C-800°C, the thickness of the quantum barrier is 9nm-15nm, and the growth temperature of the quantum barrier is 900°C-950°C.

Step 309 : Control the temperature to 750° C. to 850° C. and the pressure to 100 torr to 500 torr, and grow a low-temperature P-type layer with a thickness of 30 nm to 50 nm on the active layer.

Step 310: controlling the temperature to 900° C. to 1000° C. and the pressure to 200 torr to 500 torr, and growing an electron blocking layer with a thickness of 50 nm to 100 nm on the low temperature P-type layer.

Step 311 : controlling the temperature to 850° C. to 950° C. and the pressure to 100 torr to 300 torr, and growing a P-type semiconductor layer with a thickness of 100 nm to 300 nm on the electron blocking layer.

Step 312: controlling the temperature to 850° C. to 1000° C. and the pressure to 100 torr to 300 torr, and growing a P-type contact layer with a thickness of 5 nm to 100 nm on the P-type semiconductor layer.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection of the present invention. within range.

Claims (10)

1. a kind of LED epitaxial slice, the LED epitaxial slice includes substrate, buffer layer, n type semiconductor layer, has Active layer and p type semiconductor layer, the buffer layer are laid with over the substrate, which is characterized in that the first of the n type semiconductor layer Surface is laid on the buffer layer, and the second surface of the n type semiconductor layer includes lug boss and recessed portion, second table Face is the surface opposite with the first surface；The active layer is laid on the lug boss and the recessed portion, the p-type Semiconductor layer is laid on the active layer, and the sum of thickness of the p type semiconductor layer and the active layer is less than the protrusion The height in portion.

2. LED epitaxial slice according to claim 1, which is characterized in that the height of the lug boss is 2 μm~8 μm。

3. LED epitaxial slice according to claim 2, which is characterized in that the lug boss includes curved surface, described Curved surface intersects with the recessed portion, and the angle on the curved surface between the tangent plane and the recessed portion of each point is obtuse angle.

4. LED epitaxial slice according to claim 3, which is characterized in that the lug boss further includes plane, institute It is parallel with the recessed portion to state plane, and the plane and the surface intersection.

5. according to Claims 1 to 4 any one of them LED epitaxial slice, which is characterized in that the recessed portion and institute It is 1 μm~3 μm to state the distance between first surface.

6. according to Claims 1 to 4 any one of them LED epitaxial slice, which is characterized in that the number of the lug boss Amount is multiple, and multiple lug bosses are arranged with array way in the recessed portion；Alternatively, the quantity of the recessed portion is more A, multiple recessed portions are arranged with array way in the lug boss.

7. a kind of production method of LED epitaxial slice, which is characterized in that the production method includes：

Grown buffer layer on substrate；

N type semiconductor layer is grown on the buffer layer；

, on the surface of the n type semiconductor layer the shape graphical to the n type semiconductor layer using photoetching technique and lithographic technique At lug boss and recessed portion；

Active layer is grown on the lug boss and the recessed portion；

The sum of thickness of growing P-type semiconductor layer on the active layer, the p type semiconductor layer and the active layer is less than institute State the height of lug boss.

8. production method according to claim 7, which is characterized in that described to use photoetching technique and lithographic technique to described N type semiconductor layer is graphical, and lug boss and recessed portion are formed on the surface of the n type semiconductor layer, including：

The photoresist of setting figure is formed on the n type semiconductor layer using photoetching technique, the photoresist includes with array Multiple blob of viscoses on the n type semiconductor layer are arranged in mode, are led to what array way arranged alternatively, being equipped in the photoresist Hole；

It is graphical to the n type semiconductor layer using lithographic technique, on the surface of the n type semiconductor layer formed lug boss and Recessed portion.

9. production method according to claim 8, which is characterized in that the thickness of the photoresist is 2 μm~8 μm.

10. production method according to claim 8 or claim 9, which is characterized in that described to use lithographic technique to the N-type half Conductor layer pattern forms lug boss and recessed portion on the surface of the n type semiconductor layer, including：

Using plasma etching technics is graphical to the n type semiconductor layer, and controls the ratio of plasma components, makes institute The angle stated on the curved surface intersected with the recessed portion in lug boss between the tangent plane and the recessed portion of each point is obtuse angle.