CN117936673A - Light-emitting diode with improved light efficiency, preparation method thereof and display panel - Google Patents

Abstract

The disclosure provides a light emitting diode for improving light efficiency, a preparation method thereof and a display panel, and belongs to the technical field of photoelectron manufacturing. The LED comprises an epitaxial layer, wherein the epitaxial layer comprises a first semiconductor layer, a multiple quantum well layer and a second semiconductor layer which are sequentially laminated, the second semiconductor layer is provided with a groove exposing the first semiconductor layer, the groove wall exposing the multiple quantum well layer comprises at least one step, each step comprises a first wall surface, a step surface and a second wall surface which are sequentially connected in the direction from the second semiconductor layer to the first semiconductor layer, and the first wall surface and the second wall surface of the adjacent steps are the same wall surface. The method can improve the problem that the non-radiative recombination center is formed on the side surface of the epitaxial layer after the grooves are etched, and improves the luminous effect of the light-emitting diode.

Description

Light-emitting diode with improved light efficiency, preparation method thereof and display panel

Technical Field

The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light emitting diode with improved light efficiency, a preparation method thereof, and a display panel.

Background technique

Light Emitting Diode (LED) is an extremely influential new product in the optoelectronics industry. It has the characteristics of small size, long service life, rich colors and low energy consumption. It is widely used in lighting, display screens, signal lights, backlight sources, toys and other fields.

In the related art, a light-emitting diode generally includes a substrate, a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer stacked in sequence. A groove exposing the first semiconductor layer is generally formed on the surface of the second semiconductor layer by plasma etching, so that the electrode can be electrically connected to the first semiconductor layer through the groove.

However, during the process of plasma etching the grooves, plasma implantation will affect the side of the epitaxial layer, forming non-radiative recombination centers within a certain distance of the side, resulting in a decrease in the luminous efficiency of the light-emitting diode.

Summary of the invention

The embodiments of the present disclosure provide a light-emitting diode with improved light efficiency, a method for manufacturing the same, and a display panel, which can improve the problem of non-radiative recombination centers formed on the side of the epitaxial layer after etching the grooves, and enhance the light-emitting effect of the light-emitting diode. The technical solution is as follows:

An embodiment of the present disclosure provides a light-emitting diode, which includes an epitaxial layer, which includes a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer stacked in sequence, the second semiconductor layer having a groove exposing the first semiconductor layer, the groove wall exposing the multi-quantum well layer including at least one step, each of the steps including a first wall surface, a step surface, and a second wall surface connected in sequence in a direction from the second semiconductor layer to the first semiconductor layer, and the first wall surfaces and the second wall surfaces of adjacent steps are the same wall surface.

In another implementation of the embodiment of the present disclosure, the angle between the first wall surface and the step surface is greater than or equal to 90 degrees, and the angle between the second wall surface and the step surface is greater than or equal to 90 degrees.

In another implementation of the embodiment of the present disclosure, at least one of the step surfaces is located in a region where a side wall of the multi-quantum well layer is located.

In another implementation of the embodiment of the present disclosure, the width of the step surface is 0.5 μm to 3 μm.

In another implementation of the embodiment of the present disclosure, the length of the first wall surface is 1 μm to 2 μm, and the length of the second wall surface is 0.6 μm to 1 μm.

An embodiment of the present disclosure provides a display panel, which includes a light-emitting functional layer and a driving backplane. The light-emitting functional layer is located on the driving backplane and is electrically connected to the driving backplane. The light-emitting functional layer includes a plurality of light-emitting diodes as described above.

An embodiment of the present disclosure provides a method for preparing a light-emitting diode, the method comprising: providing a substrate; forming an epitaxial layer on the substrate, the epitaxial layer being a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer stacked in sequence; etching the second semiconductor layer to form a groove exposing the first semiconductor layer, the groove wall exposing the multi-quantum well layer comprising at least one step, each of the steps comprising a first wall surface, a step surface, and a second wall surface sequentially connected in a direction from the second semiconductor layer to the first semiconductor layer.

In another implementation of the embodiment of the present disclosure, etching the second semiconductor layer to form a groove exposing the first semiconductor layer includes: performing a first etching on the surface of the second semiconductor layer to form a first groove body exposing at least the multi-quantum well layer; performing a second etching on the bottom of the first groove body to form a second groove body exposing the first semiconductor layer.

In another implementation of the embodiment of the present disclosure, the groove depth of the first groove body is 1 μm to 2 μm, the distance between the groove wall of the first groove body and the groove wall of the second groove body is 0.5 μm to 3 μm, and the groove depth of the second groove body is 0.6 μm to 1 μm.

In another implementation of the embodiment of the present disclosure, when the first etching is performed on the surface of the second semiconductor layer, the upper power of the etching equipment is controlled to be 300W to 600W, and the lower power is 100W to 300W; when the second etching is performed on the bottom of the first groove body, the upper power of the etching equipment is controlled to be 200W to 300W, and the lower power is 50W to 150W.

The beneficial effects brought by the technical solution provided by the embodiments of the present disclosure include at least:

The second semiconductor layer of the light-emitting diode provided by the embodiment of the present disclosure has a groove exposing the first semiconductor layer, and the groove wall exposing the multi-quantum well layer in the groove includes at least one step, and each step includes a first wall surface, a step surface, and a second wall surface connected in sequence. When making the groove, at least two etchings are required to make the groove wall of the groove have at least one step. In this way, even if damage is caused on the side of the epitaxial layer and a non-radiative recombination center is formed when the groove is etched for the first time, the damaged area formed by the first etching is removed by the second etching, thereby reducing the non-radiative recombination and being more conducive to the luminous efficiency of the light-emitting diode.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

FIG1 is a schematic diagram of the structure of a light emitting diode provided by the related art;

FIG2 is a schematic diagram of the structure of a light emitting diode provided by an embodiment of the present disclosure;

FIG3 is a schematic diagram of a groove wall of a groove provided by an embodiment of the present disclosure;

FIG4 is a schematic diagram of a groove wall of a groove provided in an embodiment of the present disclosure;

FIG. 5 is a flow chart of a method for preparing a light emitting diode provided in an embodiment of the present disclosure.

The descriptions of the marks in the figure are as follows:

20. epitaxial layer; 21. first semiconductor layer; 22. multi-quantum well layer; 23. second semiconductor layer;

30, groove; 301, first wall surface; 302, step surface; 303, second wall surface;

41. transparent conductive layer; 42. passivation layer;

50. Electrode.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons with ordinary skills in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", "top", "bottom" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

Fig. 1 is a schematic diagram of the structure of a light emitting diode provided by the related art. As shown in Fig. 1, the light emitting diode in the related art includes an epitaxial layer 20, a transparent conductive layer 41, a passivation layer 42 and an electrode 50 stacked in sequence, and the epitaxial layer 20 includes a first semiconductor layer 21, a multi-quantum well layer 22 and a second semiconductor layer 23 stacked in sequence.

As shown in FIG1 , the surface of the second semiconductor layer 23 has a groove 30 exposing the first semiconductor layer 21. The transparent conductive layer 41 is located on the surface of the second semiconductor layer 23 away from the first semiconductor layer 21, and the passivation layer 42 is located on the surface of the second semiconductor layer 23 away from the first semiconductor layer 21, the surface of the transparent conductive layer 41, and in the groove 30; the passivation layer 42 has through holes exposing the transparent conductive layer 41 and the bottom of the groove 30, respectively, and the electrode 50 is connected to the transparent conductive layer 41 and the first semiconductor layer 21 respectively through the through holes.

In the related art, when preparing such a light-emitting diode, plasma etching is usually used to form the second semiconductor layer 23 to form the groove 30. Since plasma implantation affects the side of the epitaxial layer 20, non-radiative recombination centers are formed on the side of the epitaxial layer 20, which leads to a decrease in luminous efficiency.

To this end, an embodiment of the present disclosure provides a light emitting diode. FIG2 is a schematic diagram of the structure of a light emitting diode provided by an embodiment of the present disclosure. As shown in FIG2, the light emitting diode includes an epitaxial layer 20, and the epitaxial layer 20 includes a first semiconductor layer 21, a multi-quantum well layer 22, and a second semiconductor layer 23 stacked in sequence, and the second semiconductor layer 23 has a groove 30 exposing the first semiconductor layer 21.

As shown in FIG2 , the groove wall of the groove 30 exposing the multi-quantum well layer 22 includes at least one step, and each step includes a first wall surface 301, a step surface 302, and a second wall surface 303 sequentially connected in the direction from the second semiconductor layer 23 to the first semiconductor layer 21, and the first wall surface and the second wall surface of adjacent steps are the same wall surface.

The second semiconductor layer 23 of the light-emitting diode provided in the embodiment of the present disclosure has a groove 30 exposing the first semiconductor layer 21, and the groove wall of the groove 30 exposing the multi-quantum well layer 22 includes at least one step, and each step includes a first wall surface 301, a step surface 302, and a second wall surface 303 connected in sequence. When making the groove 30, at least two etchings are required to make the groove wall of the groove 30 have at least one step.

In the disclosed embodiment, the depth of the second etching is shallower than the depth of the first etching, and the upper power and lower power of the etching device during the second etching are both less than the upper power and lower power of the etching device during the first etching, so the second etching can remove the damage formed on the side of the epitaxial layer by the first etching, while also producing less damage. In this way, even if damage is caused on the side of the epitaxial layer 20 and a non-radiative recombination center is formed when the groove 30 is etched for the first time, the damaged area formed by the first etching can be removed by the second etching, thereby reducing the non-radiative recombination and being more conducive to the luminous efficiency of the light-emitting diode.

Optionally, as shown in FIG. 2 , the groove wall includes a step, which includes a first wall surface 301 , a step surface 302 , and a second wall surface 303 that are sequentially connected in a direction from the second semiconductor layer 23 to the first semiconductor layer 21 .

In the above implementation, a step is provided on the groove wall of the groove 30, so that the groove wall is formed by connecting three sections of surface, and every two sections of surface together form a bending structure. In this way, when making the groove 30, firstly, a first groove body composed of a first wall surface 301 and a step surface 302 is etched, and then the step surface 302 is further etched, and a second groove body composed of a second wall surface 303 and the surface of the first semiconductor layer 21 is formed on the step surface 302, and finally a groove 30 formed by the combination of the first groove body and the second groove body is obtained, and the groove wall of the groove 30 formed by the first wall surface 301, the step surface 302 and the second wall surface 303 is in a step shape.

In this way, even if damage is caused on the side of the epitaxial layer 20 and a non-radiative recombination center is formed when etching the first groove body, the damaged area formed by the first etching can be removed by etching the second groove body, thereby reducing the non-radiative recombination and being more beneficial to the luminous efficiency of the light-emitting diode.

In one implementation, the included angle between the first wall surface 301 and the step surface 302 is greater than or equal to 90 degrees, and the included angle between the second wall surface 303 and the step surface 302 is greater than or equal to 90 degrees.

2 , the first wall surface 301 and the step surface 302 have an angle of 90 degrees, and the second wall surface 303 and the step surface 302 have an angle of 90 degrees. At this time, the step surface 302 is parallel to the surface of the first semiconductor layer 21 .

3, the angle between the first wall surface 301 and the step surface 302 is an obtuse angle, and the angle between the second wall surface 303 and the step surface 302 is an obtuse angle. At this time, the step surface 302 is parallel to the surface of the first semiconductor layer 21, or the step surface 302 has an angle with the surface of the first semiconductor layer 21.

In the above implementation, the angle between the first wall 301 and the step surface 302 is controlled to be larger, so that the film layer subsequently formed on the first wall 301 and the step surface 302 can transition more smoothly from the intersection of the first wall 301 and the step surface 302 to the step surface 302, thereby reducing the difficulty of preparing the subsequent film layer.

The angle between the second wall 303 and the step surface 302 is controlled to be larger, so that the film layer subsequently formed on the second wall 303 and the step surface 302 can transition more smoothly from the intersection of the second wall 303 and the step surface 302 to the second wall 303, reducing the difficulty of preparing the subsequent film layer.

In another implementation, as shown in FIG4 , the angle between the first wall surface 301 and the step surface 302 is an acute angle, and the angle between the second wall surface 303 and the step surface 302 is an acute angle. At this time, the step surface 302 is parallel to the surface of the first semiconductor layer 21 .

In the above implementation, the angle between the first wall surface 301 and the step surface 302 is controlled to be small, so that the first wall surface 301 and the surface of the second semiconductor layer 23 away from the first semiconductor layer 21 form a chamfer, and the angle between the second wall surface 303 and the step surface 302 is controlled to be small, so that the second wall surface 303 and the step surface 302 form a chamfer. In this way, the film layer subsequently formed on the groove wall of the groove 30 can be prevented from falling off easily by overlapping on the chamfer, thereby improving the reliability of the light-emitting diode.

In some implementations, as shown in FIGS. 3 and 4 , at least one step surface 302 is located in a region where a sidewall of the multi-quantum well layer 22 is located.

Since plasma implantation affects the side of the epitaxial layer 20, a non-radiative recombination center is formed on the side of the epitaxial layer 20. The multi-quantum well layer 22 is a film layer for light-emitting diodes to emit light, therefore, by setting the step surface 302 in the area where the side wall of the multi-quantum well layer 22 is located, the damaged area formed on the side wall of the multi-quantum well layer 22 by the first etching can be removed by the second etching, thereby reducing non-radiative recombination and being more conducive to the light-emitting efficiency of the light-emitting diode.

In some other implementations, the step surface may be located in a region where a side wall of the first semiconductor layer is located, or the step surface may be located in a region where a side wall of the second semiconductor layer is located.

Compared with the step surface set on the side wall area of the multi-quantum well layer, the step surface is set on the side wall area of the semiconductor layer. The damaged area formed on the side wall of the semiconductor layer is removed by the secondary etching, and the multi-quantum well layer is the light-emitting layer of the epitaxial layer. Therefore, the effect of the step surface set on the side wall of the semiconductor layer on reducing the non-radiative conformity is slightly worse than the effect of the step surface set on the side wall of the multi-quantum well layer on reducing the non-radiative conformity.

Optionally, as shown in FIG. 2 , the width L1 of the step surface 302 is 0.5 μm to 3 μm.

The width of the step surface refers to the dimension of the groove wall of the groove in a cross section perpendicular to the step surface and perpendicular to the first wall surface.

By controlling the width of the step surface 302 within the above range, it is possible to avoid setting the width of the step surface 302 too large, thereby preventing too much multi-quantum well layer 22 from being etched away, and affecting the light-emitting effect of the light-emitting diode.

Exemplarily, the width of the step surface 302 is 2 μm.

Optionally, as shown in FIG. 2 , the length L2 of the first wall surface 301 is 1 μm to 2 μm, and the length L3 of the second wall surface 303 is 0.6 μm to 1 μm.

The length of the first wall surface and the length of the second wall surface both refer to the size of the groove wall of the groove in a cross section perpendicular to the step surface and perpendicular to the first wall surface.

By controlling the length of the first wall 301 within the above range, it can be ensured that the step surface 302 is located close to the area where the side wall of the multi-quantum well layer 22 is located. In this way, the damaged area formed on the side wall of the multi-quantum well layer 22 by the first etching can be removed by the second etching, thereby reducing non-radiative recombination and being more beneficial to the luminous efficiency of the light-emitting diode.

By controlling the length of the first wall surface 301 within the above range, it can be ensured that during the second etching, the multi-quantum well layer 22 is etched through to expose the first semiconductor layer 21 , and etching through the first semiconductor layer 21 can be avoided.

Exemplarily, the length of the first wall surface 301 is 1 μm, and the length of the second wall surface 303 is 0.8 μm.

Optionally, as shown in FIG2 , the light emitting diode includes an epitaxial layer 20, a transparent conductive layer 41, a passivation layer 42, and an electrode 50 stacked in sequence. The surface of the second semiconductor layer 23 has a groove 30 exposing the first semiconductor layer 21. The transparent conductive layer 41 is located on the surface of the second semiconductor layer 23 away from the first semiconductor layer 21, and the passivation layer 42 is located on the surface of the second semiconductor layer 23 away from the first semiconductor layer 21, the surface of the transparent conductive layer 41, and in the groove 30; the passivation layer 42 has a through hole exposing the transparent conductive layer 41 and the bottom of the groove 30, respectively, and the electrode 50 is connected to the transparent conductive layer 41 and the first semiconductor layer 21 through the through hole.

In the embodiment of the present disclosure, one of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer.

Exemplarily, the first semiconductor layer 21 is an n-type layer, and the second semiconductor layer 23 is a p-type layer.

The following is an illustrative description of each layer structure by taking the blue light epitaxial structure as an example in which the epitaxial layer 20 is an epitaxial structure of blue light. In the epitaxial structure of blue light, the p-type layer includes a p-type GaN layer.

The multi-quantum well layer 22 may include alternately grown InGaN quantum well layers and GaN quantum barrier layers. The third light emitting layer may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

The n-type layer includes an n-type GaN layer.

Optionally, the epitaxial layer 20 has a thickness of 2 μm to 10 μm.

Exemplarily, the thickness of the epitaxial layer 20 is 6 μm.

The transparent conductive layer 41 is a film layer connected to the electrode 50. The transparent conductive layer 41 can laterally expand the current injected by the electrode 50, so that the current can be injected into various regions of the epitaxial layer 20, thereby improving the luminous efficiency.

Exemplarily, the transparent conductive layer 41 may be an indium tin oxide (ITO) layer. The ITO layer has good transmittance and low resistivity. Using the ITO layer as the transparent conductive layer 41 can allow more light to be transmitted from the transparent conductive layer 41, thereby ensuring the light output effect; at the same time, due to the low resistivity, it is also convenient for carrier conduction and improves injection efficiency.

For example, the transparent conductive layer 41 may be an indium zinc oxide (IZO) layer. The IZO layer has good transmittance and low resistivity. Using the IZO layer as the transparent conductive layer 41 can allow more light to be transmitted from the transparent conductive layer 41, thereby ensuring the light emitting effect; at the same time, due to the low resistivity, it is also convenient for carrier conduction and improves the injection efficiency.

As an example, the thickness of the transparent conductive layer 41 may be 1000 angstroms to 5000 angstroms. For example, the thickness of the transparent conductive layer 41 is 2000 angstroms.

Optionally, the passivation layer 42 includes at least one of a silicon oxide layer, a silicon nitride layer, and a titanium oxide layer.

By way of example, the passivation layer 42 may be a silicon oxide layer.

The thickness of the silicon oxide layer may be 5000 angstroms.

Optionally, the electrodes of the light emitting diode include a p-electrode and an n-electrode, wherein the p-electrode is used to connect to the p-type layer, and the n-electrode is used to connect to the n-type layer.

An embodiment of the present disclosure provides a display panel, which includes a light-emitting functional layer and a driving backplane. The light-emitting functional layer is located on the driving backplane and is electrically connected to the driving backplane. The light-emitting functional layer includes a plurality of light-emitting diodes as described above.

Optionally, the driving backplane may be a TFT (Thin Film Transistor) substrate, the driving backplane includes a plurality of driving circuits arranged in an array, and each driving circuit on the driving backplane includes at least two TFTs for controlling the light emission of the connected light emitting layer.

Exemplarily, the driving circuit includes an active layer, a gate insulating layer, a gate layer, an interlayer dielectric layer and a source-drain electrode layer sequentially stacked on a substrate, and the light-emitting layer is connected to the source-drain electrode layer of the corresponding driving circuit.

The TFT of the driving backplane may be made of a variety of materials such as polysilicon and metal oxide, which is not limited in the embodiments of the present disclosure.

The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

FIG5 is a flow chart of a method for preparing a light emitting diode provided by an embodiment of the present disclosure. As shown in FIG5 , the preparation method includes:

Step S11: providing a substrate.

Step S12: forming an epitaxial layer 20 on the substrate.

The epitaxial layer 20 includes a first semiconductor layer 21 , a multi-quantum well layer 22 , and a second semiconductor layer 23 stacked in sequence.

Step S13 : etching the second semiconductor layer 23 to form a groove 30 exposing the first semiconductor layer 21 .

The groove wall of the groove 30 exposing the multi-quantum well layer 22 includes at least one step, and each step includes a first wall surface, a step surface, and a second wall surface sequentially connected in a direction from the second semiconductor layer to the first semiconductor layer.

The second semiconductor layer 23 of the light-emitting diode prepared by the preparation method provided by the embodiment of the present disclosure has a groove 30 exposing the first semiconductor layer 21, and the groove wall of the groove 30 exposing the multi-quantum well layer 22 includes at least one step, and each step includes a first wall surface 301, a step surface 302, and a second wall surface 303 connected in sequence. When making the groove 30, at least two etchings are required to make the groove wall of the groove 30 have at least one step. In this way, even if damage is caused on the side of the epitaxial layer 20 and a non-radiative recombination center is formed when the groove 30 is etched for the first time, the damaged area formed by the first etching is removed by the second etching, thereby reducing the non-radiative recombination and being more conducive to the luminous efficiency of the light-emitting diode.

In the related art, in order to reduce the damage caused by etching, the etching rate is usually reduced. However, this method will make the morphology of the groove 30 difficult to control.

In the embodiment of the present disclosure, the groove 30 is formed by etching twice, wherein the upper power and lower power of the etching device are larger during the first etching, and the etching rate is faster, so the first etching has a greater impact on the morphology. During the second etching, the upper power and lower power of the etching device are smaller, and the etching rate is slower, so the second etching has almost no effect on the morphology. Therefore, in the method of etching twice to form the groove, a higher etching rate is still used during the first etching, and the etching rate is not reduced, so the morphology of the groove 30 after etching can be effectively controlled, so that the morphology of the groove 30 meets the morphology required by the design.

In step S11, the substrate may be a GaAs substrate, a silicon substrate or a silicon carbide substrate. The substrate may be a flat substrate or a patterned substrate.

Step S12 may include: sequentially forming a first semiconductor layer 21 , a multi-quantum well layer 22 , and a second semiconductor layer 23 on the substrate by using MOCVD technology.

One of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer.

Exemplarily, the epitaxial layer 20 includes an n-type GaN layer, a multi-quantum well layer 22 , and a p-type GaN layer stacked in sequence.

Optionally, the thickness of the n-type GaN layer may be 0.5 μm to 3 μm.

The growth temperature of the n-type GaN layer may be 1000° C. to 1100° C., and the growth pressure of the n-type GaN layer may be 100 torr to 300 torr.

Optionally, the multi-quantum well layer 22 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers. The multi-quantum well layer 22 may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

When growing the multi-quantum well layer 22, the pressure of the MOCVD reaction chamber is controlled at 200 torr. When growing the InGaN quantum well layer, the temperature of the reaction chamber is 760° C. to 780° C. When growing the GaN quantum barrier layer, the temperature of the reaction chamber is 860° C. to 890° C.

As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

Optionally, the p-type GaN layer may have a thickness of 0.5 μm to 3 μm.

When growing the p-type GaN layer, the growth pressure of the p-type GaN layer may be 200 Torr to 600 Torr, and the growth temperature of the p-type GaN layer may be 800° C. to 1000° C.

Step S13 may include the following steps:

In the first step, a first etching is performed on the surface of the second semiconductor layer 23 to form a first groove body that at least exposes the multi-quantum well layer 22 .

Specifically, the method may include: forming a mask on the surface of the second semiconductor layer 23 by photolithography, and then forming a first groove on the surface of the second semiconductor layer 23 by plasma etching through the mask.

During the etching process, the upper power of the etching equipment is controlled to be 300W to 600W, and the lower power is controlled to be 100W to 300W.

Exemplarily, when etching the first groove body, the groove depth of the first groove body is controlled to be 1 μm to 2 μm, so that the first groove 30 at least exposes the multi-quantum well layer 22 .

In the second step, a second etching is performed on the bottom of the first trench to form a second trench exposing the first semiconductor layer 21 .

Specifically, it may include: forming a mask at the bottom of the first groove body by photolithography, and then forming a second groove body at the bottom of the first groove body by plasma etching through the mask.

During the etching process, the upper power of the etching equipment is controlled to be 200W to 300W, and the lower power is controlled to be 50W to 150W.

Exemplarily, when etching the second groove, the distance between the groove wall of the first groove and the groove wall of the second groove is controlled to be 0.5 μm to 3 μm. At the same time, the groove depth of the second groove is controlled to be 0.6 μm to 1 μm to ensure that the second groove can expose the first semiconductor layer 21 .

The above two steps are performed through two etchings, and the size of the pattern etched in the second etching is smaller than that in the first etching, so that a groove 30 with a stepped groove wall is formed.

After step S13, the preparation method may further include the following steps:

In the first step, a transparent conductive layer 41 is formed on the surface of the second semiconductor layer 23 away from the first semiconductor layer 21 .

Exemplarily, the transparent conductive layer 41 may be an indium tin oxide layer or an indium zinc oxide layer.

As an example, the thickness of the transparent conductive layer 41 may be 1000 angstroms to 5000 angstroms. For example, the thickness of the transparent conductive layer 41 is 2000 angstroms.

In the second step, a passivation layer 42 is formed on the surface of the transparent conductive layer 41 away from the substrate and in the groove 30 .

Optionally, the passivation layer 42 includes at least one of a silicon oxide layer, a silicon nitride layer, and a titanium oxide layer.

By way of example, the passivation layer 42 may be a silicon oxide layer, wherein the thickness of the silicon oxide layer may be 5000 angstroms.

In the third step, the passivation layer 42 is etched to form through holes on the surface of the passivation layer 42 to expose the transparent conductive layer 41 and the groove 30 .

Etching can be achieved by dry etching, or by using photolithography combined with wet etching, such as etching with a mixed solution of H ₃ PO ₄ /H ₂ SO ₄ , or by laser front scribing.

In the fourth step, an electrode 50 is formed on the surface of the passivation layer 42 away from the substrate, and the electrode 50 is connected to the transparent conductive layer 41 and the first semiconductor layer 21 in the groove 30 through the through hole.

Specifically, it may include: using photolithography and evaporation methods to make a p-electrode and an n-electrode.

The n-electrode is located in the groove 30 and is connected to the n-type layer through a through hole, and the p-electrode is connected to the transparent conductive layer 41 through a through hole.

Finally, the substrate is peeled off from the epitaxial layer 20 by laser lift-off, and then invisible cutting and cleaving are performed, which can effectively reduce the loss of brightness. Then, the light emitting diode is obtained by testing.

The above does not limit the present disclosure in any form. Although the present disclosure has been disclosed as above through the embodiments, it is not used to limit the present disclosure. Any technician familiar with the profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present disclosure. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present disclosure without departing from the content of the technical solution of the present disclosure still fall within the scope of the technical solution of the present disclosure.

Claims (10)

1. A light emitting diode, characterized in that the light emitting diode comprises an epitaxial layer (20), the epitaxial layer (20) comprises a first semiconductor layer (21), a multiple quantum well layer (22) and a second semiconductor layer (23) which are sequentially stacked, the second semiconductor layer (23) is provided with a groove (30) exposing the first semiconductor layer (21), the groove wall exposing the multiple quantum well layer (22) of the groove (30) comprises at least one step, each step comprises a first wall surface (301), a step surface (302) and a second wall surface (303) which are sequentially connected in the direction from the second semiconductor layer (23) to the first semiconductor layer (21), and the first wall surface (301) and the second wall surface (303) of the adjacent steps are the same wall surface.

2. The light emitting diode according to claim 1, wherein an angle between the first wall surface (301) and the step surface (302) is greater than or equal to 90 degrees, and an angle between the second wall surface (303) and the step surface (302) is greater than or equal to 90 degrees.

3. The light emitting diode of claim 1, wherein at least one of said step surfaces (302) is located in a region of a sidewall of said multiple quantum well layer (22).

4. A light emitting diode according to any one of claims 1 to 3, wherein the step surface (302) has a width (L1) of 0.5 μm to 3 μm.

5. A light emitting diode according to any one of claims 1 to 3, wherein the length (L2) of the first wall surface (301) is 1 μm to 2 μm and the length (L3) of the second wall surface (303) is 0.6 μm to 1 μm.

6. A display panel, characterized in that the display panel comprises a light emitting functional layer and a driving back plate, the light emitting functional layer is located on the driving back plate and is electrically connected with the driving back plate, and the light emitting functional layer comprises a plurality of light emitting diodes according to any one of claims 1 to 5.

7. A method of manufacturing a light emitting diode, the method comprising:

providing a substrate;

forming an epitaxial layer on the substrate, wherein the epitaxial layer is sequentially laminated with a first semiconductor layer, a multiple quantum well layer and a second semiconductor layer;

etching the second semiconductor layer to form a groove exposing the first semiconductor layer, wherein the groove wall exposing the multiple quantum well layer comprises at least one step, and each step comprises a first wall surface, a step surface and a second wall surface which are sequentially connected in the direction from the second semiconductor layer to the first semiconductor layer.

8. The method of manufacturing according to claim 7, wherein etching the second semiconductor layer to form a recess exposing the first semiconductor layer comprises:

Performing first etching on the surface of the second semiconductor layer to form a first groove body exposing at least the multiple quantum well layer;

and performing second etching on the bottom of the first groove body to form a second groove body exposing the first semiconductor layer.

9. The production method according to claim 8, wherein the groove depth of the first groove body is 1 μm to 2 μm, the pitch of the groove wall of the first groove body to the groove wall of the second groove body is 0.5 μm to 3 μm, and the groove depth of the second groove body is 0.6 μm to 1 μm.

10. The method according to claim 8, wherein the etching apparatus is controlled to have an upper power of 300W to 600W and a lower power of 100W to 300W when the surface of the second semiconductor layer is etched for the first time;

And when the bottom of the first groove body is etched for the second time, controlling the upper power of the etching equipment to be 200W to 300W and the lower power of the etching equipment to be 50W to 150W.