CN108573862B - Semiconductor structure and method of forming the same - Google Patents

Abstract

A semiconductor structure and a method of forming the same, the method comprising: the device comprises a substrate, a first electrode, a second electrode and a third electrode, wherein the substrate is provided with a device structure which comprises an initial side wall structure; forming an initial first dielectric layer on the substrate, the device structure and the initial side wall structure; flattening the initial first dielectric layer to form a first dielectric layer; removing part of the initial side wall structure to form a side wall structure, wherein the top surface of the side wall structure is lower than or level to the lowest point of the top surface of the first medium layer; after the side wall structure is formed, densifying the first medium layer to form an initial second medium layer, wherein the bottom surface of the initial second medium layer is lower than the top surface of the side wall structure, and the density of the initial second medium layer is greater than that of the first medium layer; after the initial second dielectric layer is formed, the device removing structure forms an opening structure, and a material layer is formed in the opening structure and on the initial second dielectric layer; and flattening the material layer and the initial second dielectric layer until the top surface of the side wall structure is exposed to form a grid structure and a second dielectric layer. The second dielectric layer has good isolation performance.

Description

Semiconductor structure and method of forming the same

technical field

The present invention relates to the technical field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background technique

With the reduction of technology nodes, the traditional gate dielectric layer is continuously thinner, and the leakage of transistors increases accordingly, causing problems such as waste of power consumption of semiconductor devices. In order to solve the above problems, the prior art provides a solution of replacing the polysilicon gate with a metal gate. Among them, the gate last process is a main process for forming the metal gate.

However, during the gate-last process, the metal material of the metal gate deteriorates the isolation performance of the dielectric layer in the semiconductor structure, thereby affecting the performance of the semiconductor structure.

SUMMARY OF THE INVENTION

The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can improve the performance of the semiconductor structure.

In order to solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate with a device structure on the substrate, the device structure including an initial spacer structure; forming an initial first dielectric layer on the top surface of the initial spacer structure; planarizing the initial first dielectric layer until the top surface of the initial spacer structure is exposed to form a first dielectric layer; removing part of the initial spacer structure to form a spacer structure, the top surface of the sidewall structure is lower than or flush with the lowest point of the top surface of the first dielectric layer; after the sidewall structure is formed, part of the first dielectric layer is densified to form an initial the second dielectric layer, the bottom surface of the initial second dielectric layer is lower than the top surface of the spacer structure, and the density of the initial second dielectric layer is greater than the density of the first dielectric layer; forming the initial second dielectric layer After the second dielectric layer, the device structure is removed to form an opening structure; a material layer is formed in the opening structure and on the initial second dielectric layer; the material layer and the initial second dielectric layer are planarized until the top of the spacer structure is exposed On the surface, a gate structure and a second dielectric layer are formed.

Optionally, the substrate includes: a first area and a second area.

Optionally, the device structure includes a first dummy gate structure located in the first region and a second dummy gate structure located in the second region; the first dummy gate structure includes: a first dummy gate structure a gate dielectric layer and a first dummy gate layer located on the first dummy gate dielectric layer; the second dummy gate structure includes: a second dummy gate dielectric layer and a gate dielectric layer located on the second dummy gate dielectric layer the second dummy gate layer.

Optionally, the size of the first dummy gate structure along the channel length direction is smaller than the size of the second dummy gate structure along the channel length direction.

Optionally, the top surface of the first dummy gate layer has a first mask layer; the top surface of the second dummy gate layer has a second mask layer; the thickness of the first mask layer is thicker than that of the third mask layer. The thickness of the second mask layer is thin.

Optionally, the initial spacer structure includes an initial first spacer and an initial second spacer, and the initial first spacer is located on sidewalls of the first dummy gate dielectric layer and the first dummy gate layer, The initial second spacers are located on sidewalls of the second dummy gate dielectric layer and the second dummy gate layer.

Optionally, the process of planarizing the initial first dielectric layer further includes: removing the first mask layer and the second mask layer.

Optionally, the material of the initial first dielectric layer includes: silicon oxide.

Optionally, the formation process of the initial first dielectric layer includes: a fluid chemical vapor deposition process.

Optionally, the process of planarizing the initial first dielectric layer includes: a chemical mechanical polishing process.

Optionally, the process for removing part of the initial spacer structure includes: an isotropic dry etching process or a wet etching process.

Optionally, the process parameters of the isotropic dry etching process include: the etching gas includes: CH ₃ F, CH ₂ F ₂ and O ₂ , wherein the flow rate of CH ₃ F is: 10 standard ml/min ~500 standard ml/min, flow rate of CH ₂ F ₂ : 10 standard ml/min ~ 200 standard ml/min, flow rate of O ₂ : 10 standard ml/min ~ 300 standard ml/min, pressure: 2 mm Torr to 50 mtorr, power: 100 watts to 200 watts.

Optionally, the removal amount of the initial spacer structure along a direction perpendicular to the top surface of the substrate is: 3 nanometers to 10 nanometers.

Optionally, the process of densifying the first dielectric layer to form the initial second dielectric layer includes: high temperature plasma treatment; the process parameters of the high temperature plasma treatment process include: gases include: helium, helium The flow rate is: 100 standard ml/min ~ 1000 standard ml/min, temperature: 300 degrees Celsius ~ 500 degrees Celsius, power 100 watts ~ 1000 watts, pressure: 0.2 Torr ~ 5 Torr.

Optionally, the minimum thickness of the second dielectric layer is 5 nanometers to 20 nanometers.

Optionally, the process of planarizing the material layer and the initial second dielectric layer includes: a chemical mechanical polishing process.

Correspondingly, the present invention also provides a semiconductor structure formed by the above method, comprising: a substrate having a gate structure on the substrate, the gate structure including a spacer structure, and a top surface of the spacer structure flush with the top surface of the gate structure; a first dielectric layer on the substrate, the top surface of the first dielectric layer is lower than the top surface of the spacer structure; located on the first dielectric layer The second dielectric layer on the top surface of the second dielectric layer is flush with the top surface of the sidewall structure.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following beneficial effects:

In the method for forming a semiconductor structure provided by the technical solution of the present invention, by removing part of the initial spacer structure, the top surface of the spacer structure formed is lower than or flush with the lowest point of the top surface of the first dielectric layer. A part of the first dielectric layer is subsequently densified to form an initial second dielectric layer, and the top surface of the formed initial second dielectric layer is higher than or flush with the top surface of the sidewall. Even if the surface of the initial second dielectric layer has depressions, after subsequent planarization, the surface of the formed second dielectric layer is still flat. The bottom surface of the initial second dielectric layer is lower than the top surface of the spacer structure, so that when the material layer is subsequently planarized until the top surface of the spacer structure is exposed, the top surface of the first dielectric layer is still completely covered by the second dielectric layer. In addition, the density of the initial second dielectric layer is higher than that of the first dielectric layer, so it is more beneficial to flatten the top surface of the second dielectric layer formed after planarization, so that the second dielectric layer is isolated The performance between different devices of the semiconductor is better, thereby improving the performance of the semiconductor structure.

In the semiconductor structure provided by the technical solution of the present invention, the density of the second dielectric layer on the first dielectric layer is higher than that of the first dielectric layer, the top surface of the second dielectric layer is flat, and the first dielectric layer has a flat top surface. The performance of the two dielectric layers separating different semiconductor devices is better, thereby improving the performance of the semiconductor structure.

Description of drawings

1 to 2 are schematic structural diagrams of each step of a method for forming a semiconductor structure;

3 to 8 are schematic structural diagrams of each step of a method for forming a semiconductor structure according to an embodiment of the present invention.

Detailed ways

As mentioned in the background art, the isolation performance of the dielectric layer in the semiconductor structure is not good.

FIG. 1 to FIG. 2 are schematic structural diagrams of various steps of a method for forming a semiconductor structure.

Referring to FIG. 1, a substrate is provided, the substrate includes a first region A and a second region B, the first region A has a first dummy gate structure 101 on the substrate, and the first dummy gate structure 101 includes a first dummy gate structure 101. A dummy gate spacer 102 and a first dummy gate layer (not shown in the figure), the top surface of the first dummy gate structure 101 has a first mask layer (not shown in the figure), the second The region B has a second dummy gate structure 103 on the substrate, the second dummy gate structure 103 includes a second dummy gate spacer 104 and a second dummy gate layer (not shown in the figure), the second dummy gate The top surface of the gate structure 103 has a second mask layer (not marked in the figure), and the substrate, the first dummy gate structure 101 and the second dummy gate structure 103 have an initial first dielectric layer; The initial first dielectric layer is formed until the top surfaces of the first dummy gate spacers 102 and the second dummy gate spacers 104 are exposed to form a first dielectric layer 105, and the top surface of the first dielectric layer 105 is lower than the Top surfaces of the first dummy gate spacers 102 and the second dummy gate spacers 104 .

Referring to FIG. 2, the first dummy gate structure 101 is removed to form a first opening, and a first gate structure 107 is formed in the first opening; the second dummy gate structure 103 is removed to form a second opening, A second gate structure 108 is formed within the second opening.

The material of the initial first dielectric layer includes: silicon oxide; the process of forming the initial first dielectric layer includes: a fluid chemical vapor deposition process.

The materials of the first mask layer and the second mask layer include: silicon nitride.

However, the semiconductor structures prepared by the above methods have poor performance due to:

In the above method, the first region A is used to form a short channel region, the second region B is used to form a long channel region, and the device spacing in the short channel region is longer and the device spacing in the channel region is small. . In order to form the first dummy gate structure 101 and the second dummy gate structure 103 with good topography, the thickness of the first mask layer on the first dummy gate structure 101 is thicker than that on the second dummy gate structure 101 The thickness of the second mask layer on the gate structure 103 is thin.

Subsequently, the initial first dielectric layer is planarized by chemical mechanical polishing until the top surfaces of the first dummy gate spacers 102 and the second dummy gate spacers 104 are exposed to form the first dielectric layer 105 . In the process of planarizing the initial first dielectric layer, the first mask layer and the second mask layer are also removed. Since the density of the first mask layer and the second mask layer is higher than that of the initial first dielectric layer, the initial first dielectric layer, the first mask layer and the second initial dielectric layer are removed during planarization. In the process of the mask layer, the mechanical polishing rate of the initial first dielectric layer in the planarization process is greater than the mechanical polishing rate of the first mask layer and the second mask layer, so that the planarization process is adopted. The top surface of the first dielectric layer 105 formed by the process has recesses.

Specifically, in the process of planarizing and removing part of the initial first dielectric layer, the first mask layer and the second mask layer, since the thickness of the first mask layer is thinner than that of the second mask layer Therefore, when the first mask layer is completely removed, the second mask layer still remains. When the first mask layer is completely removed, the top surfaces of the first dielectric layer 105 in both the first region A and the second region B are recessed. After the first mask layer is removed, in order to remove the second mask layer, part of the initial first dielectric layer and the second mask layer are continued to be planarized, resulting in the surface of the first dielectric layer in the second region B being flattened. The depression deepens. Therefore, when the second mask layer is completely removed, the top surface of the first dielectric layer 105 located in the first region A has the first depression, and the top surface of the first dielectric layer 105 located in the second region B has the second depression, And the maximum depth of the first recess is smaller than the maximum depth of the second recess.

Subsequently, a first gate structure 107 is formed in the first opening, and a second gate structure 108 is formed in the second opening. The steps of forming the first gate structure 107 and the second gate structure 108 include: forming a material layer in the first opening, the second opening and on the first dielectric layer 105 ; and planarizing the material layer until the top surfaces of the first dummy gate spacers 102 and the second dummy gate spacers 104 are exposed. When the material layer is planarized, the material layers are easily deposited at the first recess and the second recess, so that the performance of the first dielectric layer 105 in isolating different semiconductor devices is poor, thereby affecting the performance of the semiconductor structure.

In order to solve the above-mentioned technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, which includes: providing a substrate with a device structure on the substrate, and the device structure includes an initial spacer structure; forming an initial first dielectric layer on the top surface of the initial spacer structure; planarizing the initial first dielectric layer until the top surface of the initial spacer structure is exposed to form a first dielectric layer; removing part of the initial spacer structure to form a spacer structure, the top surface of the sidewall structure is lower than or flush with the lowest point of the top surface of the first dielectric layer; after the sidewall structure is formed, part of the first dielectric layer is densified to form an initial the second dielectric layer, the bottom surface of the initial second dielectric layer is lower than the top surface of the spacer structure, and the density of the initial second dielectric layer is greater than the density of the first dielectric layer; forming the initial second dielectric layer After the second dielectric layer, the device structure is removed to form an opening structure; a material layer is formed in the opening structure and on the initial second dielectric layer; the material layer and the initial second dielectric layer are planarized until the spacer structure is exposed. On the top surface, a gate structure and a second dielectric layer are formed.

In the method, by removing part of the initial sidewall structure, the top surface of the formed sidewall structure is lower than or flush with the lowest point of the top surface of the first dielectric layer. A part of the first dielectric layer is subsequently densified to form an initial second dielectric layer, and the top surface of the formed initial second dielectric layer is higher than or flush with the top surface of the sidewall. Even if the surface of the initial second dielectric layer has depressions, after subsequent planarization, the surface of the formed second dielectric layer is still flat. The bottom surface of the initial second dielectric layer is lower than the top surface of the spacer structure, so that when the material layer is subsequently planarized until the top surface of the spacer structure is exposed, the top surface of the first dielectric layer is completely covered by a second dielectric layer. In addition, the density of the initial second dielectric layer is higher than that of the first dielectric layer, so it is more beneficial to flatten the top surface of the second dielectric layer formed after planarization, so that the second dielectric layer is isolated The performance between different devices of the semiconductor is better, thereby improving the performance of the semiconductor structure.

In order to make the above objects, features and beneficial effects of the present invention more clearly understood, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

3 to 8 are schematic structural diagrams of each step of a method for forming a semiconductor structure according to an embodiment of the present invention.

Referring to FIG. 3, a substrate 200 is provided, the substrate 200 has a device structure (not shown in the figure), and the device structure includes an initial spacer structure (not shown in the figure); in the substrate 200, the device structure and the An initial first dielectric layer 201 is formed on the initial spacer structure.

In this embodiment, the base 200 includes: a substrate 202 and a fin 203 on the substrate 202 . In other embodiments, the substrate is a planar substrate.

The steps of forming the base 200 include: providing an initial substrate; patterning the initial substrate to form the substrate 202 and the fins 203 on the substrate 202 .

In this embodiment, the material of the initial substrate is silicon. In other embodiments, the initial substrate may also be a germanium substrate, a silicon germanium substrate, a silicon-on-insulator or a germanium-on-insulator or other semiconductor substrate.

The substrate 200 also includes an isolation structure (not shown in the figure) for realizing electrical isolation between different devices of the semiconductor.

In this embodiment, the substrate 200 includes a first region I and a second region II, the first region I is used for forming short-channel devices, and the second region II is used for forming long-channel devices.

In this embodiment, the device structure includes: a first dummy gate structure 204 located in the first region I and a second dummy gate structure 205 located in the second region II, and the first dummy gate structure 205 The size of the gate structure 204 along the channel length direction is smaller than the size of the second dummy gate structure 205 along the channel length direction.

In this embodiment, the method further includes: forming first source-drain doped regions 208 in the fins 203 on both sides of the first dummy gate structure 204 ; A second source-drain doped region 209 is formed in the fin portion 203 .

The size of the first dummy gate structure 204 along the channel length direction refers to the size of the first dummy gate structure 204 along the direction of the connection between the first source and drain doped regions 208 on both sides.

The dimension of the second dummy gate structure 205 along the channel length direction refers to the dimension of the second dummy gate structure 205 along the connection direction of the second source-drain doped regions 209 on both sides.

In this embodiment, the initial sidewall structure includes: an initial first sidewall 206 and an initial second sidewall 207 .

The first dummy gate structure 204 includes: a first dummy gate dielectric layer, a first dummy gate layer on the first dummy gate dielectric layer, sidewalls and a first dummy gate on the first dummy gate dielectric layer The initial first spacer 206 of the sidewall of the pole layer.

The second dummy gate structure 205 includes: a second dummy gate dielectric layer, a second dummy gate layer on the second dummy gate dielectric layer, sidewalls of the second dummy gate dielectric layer and a second dummy gate The initial second spacer 207 of the sidewall of the pole layer.

The initial first sidewall 206 and the initial second sidewall 207 have the same thickness.

In this embodiment, the top surface of the first dummy gate structure 204 has a first mask layer (not shown in the figure), and the first mask layer is used for etching to form the first dummy gate layer mask. The top surface of the second dummy gate structure 205 has a second mask layer (not shown in the figure), the second mask layer serves as a mask for etching to form the second dummy gate layer, and The thickness of the first mask layer is thinner than that of the second mask layer.

The reasons why the thickness of the first mask layer is thinner than that of the second mask layer include: the first region I is used to form a short channel region, the second region II is used to form a long channel region, and the The device pitch in the short channel region is longer, and the device pitch in the channel region is small. In order to form the first dummy gate structure 204 and the second dummy gate structure 205 with good topography, the thickness of the first mask layer on the first dummy gate structure 204 is higher than that on the second dummy gate The thickness of the second mask layer on the structure 205 is thin.

Materials of the first mask layer and the second mask layer include: silicon nitride.

Before forming the initial first dielectric layer 201, the method further includes: performing lightly doped ion implantation on the fins 203 on both sides of the first dummy gate structure 204 and the second dummy gate structure 205; After doping ion implantation, first source and drain doped regions 208 are formed in the fins 203 on both sides of the first dummy gate structure 204 ; the fins on both sides of the second dummy gate structure 205 are formed. A second source and drain doped region 209 is formed in 203; after the first source and drain doped region 208 and the second source and drain doped region 209 are formed, the substrate 200, the first source and drain A stop layer 210 is formed on the two source and drain doped regions 209 , the first mask layer and the second mask layer.

The steps of forming the first source-drain doped region 208 include: using an etching process to form openings in the fins 203 on both sides of the first dummy gate structure 204; using a selective epitaxial deposition process to form openings in the openings An epitaxial layer is formed; P-type ions or N-type ions are doped in the epitaxial layer to form the first source-drain doped region 208 .

The steps of forming the second source and drain doped regions 209 include: using an etching process to form openings in the fins 203 on both sides of the second dummy gate structure 205; using a selective epitaxial deposition process to form openings in the openings An epitaxial layer is formed; P-type ions or N-type ions are doped in the epitaxial layer to form the second source-drain doped region 209 .

The material of the stop layer 210 includes: silicon nitride.

The material of the initial first dielectric layer 201 includes: silicon oxide. The formation process of the initial first dielectric layer 201 includes: a fluid chemical vapor deposition process. The initial first dielectric layer 201 is used to achieve electrical isolation between different semiconductor devices.

Referring to FIG. 4 , the initial first dielectric layer 201 is planarized until the top surface of the initial spacer structure is exposed to form a first dielectric layer 211 .

In the process of planarizing the initial first dielectric layer 201, the process further includes: removing the first mask layer and the second mask layer.

The planarization process includes: a chemical mechanical polishing process. Since the density of the first mask layer and the second mask layer is higher than that of the initial first dielectric layer 201 , the initial first dielectric layer 201 and the first mask layer are removed during planarization. And in the process of the second mask layer, the mechanical polishing rate of the planarization process for the initial first dielectric layer 201 is greater than the mechanical polishing rate for the first mask layer and the second mask layer, so that the use of The top surface of the first dielectric layer 211 formed by the planarization process has recesses.

The top surface of the first dielectric layer 211 in the first region I has a first recess, and the top surface of the first dielectric layer 211 in the second region II has a second recess. The maximum depth of the first recess is: H1, the maximum depth of the second recess is: H2, and H1 is less than H2.

The maximum depth H1 of the first recess refers to the maximum dimension from the top surface of the first dielectric layer 211 in the first region I to the top surface of the first dummy gate structure 204 .

The maximum depth H2 of the second recess refers to the maximum dimension from the top surface of the first dielectric layer 211 in the second region II to the top surface of the second dummy gate structure 205 .

The reasons why H1 is smaller than H2 and H1 is smaller than H2 include: when the first mask layer is completely removed, the top surfaces of the first dielectric layers 211 in the first region I and the second region II are both depressed. After removing the first mask layer, in order to completely remove the second mask layer, the initial first dielectric layer 201 and the second mask layer are further planarized, resulting in the first dielectric layer 211 in the second region II The depression on the top surface deepens. Therefore, when the second mask layer is completely removed, the maximum depth H1 of the first recess is made smaller than the maximum depth H2 of the second recess.

The depth of the maximum depth H2 of the second recess is 3 nanometers to 10 nanometers.

The maximum depth H2 of the second recess determines the subsequent removal amount of the initial spacer structure along the direction perpendicular to the top surface of the fins 203 .

Referring to FIG. 5 , part of the initial spacer structure is removed to form a spacer structure, and the top surface of the spacer structure is lower than or flush with the lowest point of the top surface of the first dielectric layer 211 .

The process for removing part of the initial spacer structure includes: an isotropic dry etching process or a wet etching process.

The process parameters of the isotropic dry etching process include: the etching gas includes: CH ₃ F, CH ₂ F ₂ and O ₂ , wherein the flow rate of CH ₃ F is: 10 standard milliliters per minute to 500 standard milliliters /min, the flow rate of CH ₂ F ₂ is: 10 standard ml/min ~ 200 standard ml/min, the flow rate of O ₂ is: 10 standard ml/min ~ 300 standard ml/min, the pressure is: 2 mTorr ~ 50 m Support, power: 100 watts to 200 watts.

The lowest point of the top surface of the first dielectric layer 211 is located at the maximum depth H2 of the second recess.

The removal amount of the initial spacer structure in a direction perpendicular to the top surface of the fins 203 is determined by the maximum depth H2 of the second recess.

In the process of removing part of the initial spacer structure, the removal amount of the initial spacer structure along the direction perpendicular to the top surface of the fins 203 is 3 nanometers to 10 nanometers. The significance of selecting the removal amount of the initial spacer structure in the direction perpendicular to the top surface of the fin 203 is that the removal amount of the initial spacer structure in the direction perpendicular to the top surface of the fin 203 is less than 3 nm , a second dielectric layer is subsequently formed on the first dielectric layer 211, and a part of the material layer remains on the top surface of the second dielectric layer when the gate structure is formed, thereby affecting the isolation performance of the second dielectric layer, This further affects the performance of the semiconductor structure; if the removal amount of the initial spacer structure along the direction perpendicular to the top surface of the fins 203 is greater than 10 nanometers, the height of the subsequently formed gate structure is too low, which is not conducive to the performance of the semiconductor structure .

The side wall structure includes: a first side wall 212 and a second side wall 213 .

The forming step of the first sidewall 212 includes: removing part of the initial first sidewall 206 to form a first sidewall 212 , and the top surface of the first sidewall 212 is lower than or flush with the first dielectric layer 211 . The lowest point on the top surface.

The forming step of the second sidewall 213 includes: removing part of the initial second sidewall 207 to form a second sidewall 213 , and the top surface of the second sidewall 213 is lower than or flush with the first dielectric layer 211 The lowest point on the top surface.

The top surface of the sidewall structure is lower than or flush with the lowest point of the top surface of the first dielectric layer 211 , in order to ensure that when the second dielectric layer is subsequently formed on the first dielectric layer 211 , the When the gate structure is formed on the top surface of the second dielectric layer, no material layer remains, thereby improving the isolation performance of the second dielectric layer, thereby improving the performance of the semiconductor structure.

Referring to FIG. 6 , after the sidewall structure is formed, a portion of the first dielectric layer 211 is densified to form an initial second dielectric layer 214 , and the bottom surface of the initial second dielectric layer 214 is lower than the sidewalls. The top surface of the wall structure, and the density of the initial second dielectric layer 214 is greater than the density of the first dielectric layer 211 .

The process of densifying the first dielectric layer 211 to form the initial second dielectric layer 214 includes: a high temperature plasma treatment process; the process parameters of the high temperature plasma treatment process include: gases include: helium, helium The flow rate is: 100 standard ml/min ~ 1000 standard ml/min, temperature: 300 degrees Celsius ~ 500 degrees Celsius, power 100 watts ~ 1000 watts, pressure: 0.2 Torr ~ 5 Torr.

The principle that the density of the initial second medium 214 is greater than the density of the first medium layer 211 includes: under the high temperature plasma treatment process, part of the first medium layer 211 is reorganized at high temperature to form an initial first medium layer with a higher density. Two dielectric layers 214 .

The minimum thickness of the initial second dielectric layer 214 is 5 nanometers to 20 nanometers. The significance of selecting the minimum thickness of the initial second dielectric layer 214 is: if the minimum thickness of the initial second dielectric layer 214 is less than 5 nanometers, When the gate structure is subsequently formed, when the material layer on the initial second dielectric layer 214 is planarized, the thickness of the initial second dielectric layer 214 is too thin, so that the initial second dielectric layer 214 is not suitable for the first dielectric layer 214 . The protection strength of a dielectric layer 211 is insufficient. That is, after the initial second dielectric layer is planarized and removed, part of the first dielectric layer 211 is also planarized and removed. Since the first dielectric layer 211 is formed by a fluid chemical vapor deposition process, the texture of the first dielectric layer 211 is relatively soft. In the process of planarizing and removing part of the first dielectric layer 211 , the first dielectric layer 211 is prone to concavities on both sides of the gate structure subsequently formed, and the first dielectric layer 211 with concavities has poor isolation performance and does not It is beneficial to improve the performance of the semiconductor structure; if the minimum thickness of the initial second dielectric layer 214 is greater than 20 nanometers, the process difficulty of the first dielectric layer 211 in the densification treatment part is increased.

The bottom surface of the initial second dielectric layer 214 is lower than the top surface of the spacer structure, and the density of the initial second dielectric layer 214 is greater than the density of the first dielectric layer 211, so that the subsequent planarization material layer The top surface of the formed second dielectric layer 214 has good flatness, so that the electrical isolation performance of the second dielectric layer 214 is good, thereby improving the performance of the semiconductor structure.

Referring to FIG. 7 , the device structure is removed to form an opening structure.

The opening structure includes: a first opening 215 and a second opening 216, and the steps of forming the first opening 215 and the second opening 216 include: removing the first dummy gate structure 204 to form the first opening 215; removing The second dummy gate structure 205 forms a second opening 216 .

The process of removing the first dummy gate structure 204 and the second dummy gate structure 205 includes: an anisotropic dry etching process or a combination of a dry etching process and a wet etching process.

The process parameters of the combination of the anisotropic dry etching process and the wet etching process include: the etching gas includes: hydrogen bromide, chlorine and oxygen, wherein the flow rate of hydrogen bromide is: 10 standard ml/min ～500 standard ml/min, the flow rate of chlorine gas is: 10 standard ml/min～500 standard ml/min, the flow rate of oxygen is: 2 standard ml/min～100 standard ml/min, power: 100 watts～1000 watts, engraved The etchant includes: dilute hydrofluoric acid, the concentration ratio of hydrofluoric acid to water is 50:1-2000:1, and the mass fraction of tetramethylammonium hydroxide is: 0.5%-5%.

Referring to FIG. 8 , after the opening structure is formed, a material layer is deposited in the opening structure, and the material layer and part of the initial second dielectric layer 214 are planarized until the top surface of the spacer structure is exposed to form a gate structure and the second dielectric layer 219.

The gate structure includes: a first gate structure 217 and a second gate structure 218 , and the forming steps of the first gate structure 217 and the second gate structure 218 include: the first opening 215 , the second gate structure 218 A material layer is formed in the two openings 216 and on the initial second dielectric layer 214 ; the material layer is planarized until the top surface of the spacer structure is exposed, a first gate structure 217 is formed in the first opening 215 , and a first gate structure 217 is formed in the first opening 215 . A second gate structure 218 is formed in the two openings 216 .

The material of the material layer includes: a metal layer, and the material of the metal layer includes: tungsten.

The process of planarizing the material layer includes: a chemical mechanical polishing process.

The top surface of the second dielectric layer 219 has good flatness, so that the isolation performance of the second dielectric layer is better, thereby improving the performance of the semiconductor structure.

To sum up, in this embodiment, by removing part of the initial sidewall structure, the top surface of the formed sidewall structure is lower than or flush with the lowest point of the top surface of the first dielectric layer. A part of the first dielectric layer is subsequently densified to form an initial second dielectric layer, and the top surface of the formed initial second dielectric layer is higher than or flush with the top surface of the sidewall. Even if the surface of the initial second dielectric layer has depressions, after subsequent planarization, the surface of the formed second dielectric layer is still flat. The bottom surface of the initial second dielectric layer is lower than the top surface of the spacer structure, so that when the material layer is subsequently planarized until the top surface of the spacer structure is exposed, the top surface of the first dielectric layer is still completely covered by the second dielectric layer. In addition, the density of the initial second dielectric layer is higher than that of the first dielectric layer, so it is more beneficial to flatten the top surface of the second dielectric layer formed after planarization, so that the second dielectric layer is isolated The performance between different devices of the semiconductor is better, thereby improving the performance of the semiconductor structure.

An embodiment of the present invention also provides a semiconductor structure formed by the above method, please refer to FIG. 8 , including:

a substrate 200 having a gate structure on the substrate 200, the gate structure having a spacer structure, and the top surface of the spacer structure is flush with the top surface of the gate structure;

a first dielectric layer 211 on the substrate 200 (see FIG. 5 ), the top surface of the first dielectric layer 211 is lower than the top surface of the gate structure;

For the second dielectric layer 219 on the first dielectric layer 211, the top surface of the second dielectric layer 219 is flush with the top surface of the gate structure.

To sum up, in this embodiment, the density of the second dielectric layer on the first dielectric layer is higher than that of the first dielectric layer, and the top surface of the second dielectric layer is flat. Therefore, the The performance of the second dielectric layer in isolating different semiconductor devices is better, thereby improving the performance of the semiconductor structure.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.

Claims (17)

1. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate is provided with a device structure, and the device structure comprises an initial side wall structure;

forming an initial first dielectric layer on the top surfaces of the substrate, the device structure and the initial side wall structure;

flattening the initial first dielectric layer until the top surface of the initial side wall structure is exposed to form a first dielectric layer;

removing part of the initial side wall structure to form a side wall structure, wherein the top surface of the side wall structure is lower than or flush with the lowest point of the top surface of the first medium layer;

after the side wall structure is formed, performing densification treatment on part of the first dielectric layer to form an initial second dielectric layer, wherein the bottom surface of the initial second dielectric layer is lower than the top surface of the side wall structure, and the density of the initial second dielectric layer is greater than that of the first dielectric layer;

after the initial second dielectric layer is formed, forming an opening structure by removing the device structure;

forming a material layer in the opening structure and on the initial second dielectric layer;

and flattening the material layer and the initial second dielectric layer until the top surface of the side wall structure is exposed to form a grid structure and a second dielectric layer.

2. The method of forming a semiconductor structure of claim 1, wherein the substrate comprises: a first region and a second region.

3. The method of forming a semiconductor structure of claim 2, wherein the device structure comprises a first dummy gate structure in the first region and a second dummy gate structure in the second region; the first dummy gate structure includes: the first dummy gate layer is positioned on the first dummy gate dielectric layer; the second dummy gate structure includes: the second dummy gate dielectric layer and a second dummy gate layer are positioned on the second dummy gate dielectric layer.

4. The method of forming a semiconductor structure of claim 3, wherein a dimension of the first dummy gate structure in a channel length direction is smaller than a dimension of the second dummy gate structure in the channel length direction.

5. The method for forming a semiconductor structure according to claim 4, wherein a top surface of the first dummy gate layer has a first mask layer; the top surface of the second pseudo gate layer is provided with a second mask layer; the thickness of the first mask layer is thinner than that of the second mask layer.

6. The method for forming the semiconductor structure according to claim 3, wherein the initial sidewall structure comprises an initial first sidewall and an initial second sidewall, the initial first sidewall is located on sidewalls of the first dummy gate dielectric layer and the first dummy gate layer, and the initial second sidewall is located on sidewalls of the second dummy gate dielectric layer and the second dummy gate layer.

7. The method of forming a semiconductor structure of claim 5, wherein planarizing the initial first dielectric layer further comprises: and removing the first mask layer and the second mask layer.

8. The method of forming a semiconductor structure of claim 1, wherein a material of the initial first dielectric layer comprises: silicon oxide.

9. The method of forming a semiconductor structure of claim 1, wherein the forming of the initial first dielectric layer comprises: a fluid chemical vapor deposition process.

10. The method of forming a semiconductor structure of claim 1, wherein planarizing the initial first dielectric layer comprises: and (5) carrying out a chemical mechanical polishing process.

11. The method of claim 1, wherein the step of removing a portion of the initial sidewall spacer structure comprises: an isotropic dry etching process or a wet etching process.

12. The method of forming a semiconductor structure of claim 11, wherein the process parameters of the isotropic dry etch process comprise: the etching gas includes: CH (CH)₃F、CH₂F₂And O₂In which CH₃The flow rate of F is: 10-500 ml/min, CH₂F₂The flow rate of (A) is as follows: 10-200 ml/min, O₂The flow rate of (A) is as follows: 10-300 standard ml/min, pressure: 2 mtorr to 50 mtorr, power: 100-200 watts.

13. The method for forming a semiconductor structure of claim 1, wherein the removal amount of the initial sidewall structure in a direction perpendicular to the top surface of the substrate is: 3 to 10 nanometers.

14. The method of claim 1, wherein the densifying the first dielectric layer to form an initial second dielectric layer comprises: a high-temperature plasma treatment process; the technological parameters of the high-temperature plasma treatment process comprise: the gas comprises: helium, the flow rate of helium is: 100-1000 ml/min, temperature: 300-500 ℃, 100-1000W of power, pressure: 0.2 to 5 torr.

15. The method of forming a semiconductor structure of claim 1, wherein the minimum thickness of the second dielectric layer is: 5 to 20 nanometers.

16. The method of claim 1, wherein planarizing the material layer and the initial second dielectric layer comprises: and (3) a chemical mechanical polishing process.

17. A semiconductor structure formed by the method of any of claims 1 to 16, comprising:

the grid structure comprises a side wall structure, and the top surface of the side wall structure is flush with the top surface of the grid structure;

the first dielectric layer is positioned on the substrate, and the top surface of the first dielectric layer is lower than that of the side wall structure;

and the top surface of the second dielectric layer is flush with the top surface of the side wall structure.

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