CN108550675A - A kind of LED epitaxial slice and preparation method thereof - Google Patents
A kind of LED epitaxial slice and preparation method thereof Download PDFInfo
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- DJPURDPSZFLWGC-UHFFFAOYSA-N alumanylidyneborane Chemical group [Al]#B DJPURDPSZFLWGC-UHFFFAOYSA-N 0.000 claims abstract description 15
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052738 indium Inorganic materials 0.000 claims abstract description 11
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical group [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 9
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical group [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims description 5
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- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/81—Bodies
- H10H20/819—Bodies characterised by their shape, e.g. curved or truncated substrates
- H10H20/821—Bodies characterised by their shape, e.g. curved or truncated substrates of the light-emitting regions, e.g. non-planar junctions
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- H—ELECTRICITY
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- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/01—Manufacture or treatment
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Abstract
本发明公开了一种发光二极管外延片及其制备方法,属于半导体技术领域。外延片包括衬底以及依次层叠在衬底上的缓冲层、N型半导体层、有源层、电子阻挡层和P型半导体层,缓冲层,电子阻挡层包括依次层叠的多个复合结构,每个复合结构包括依次层叠的第一子层和第二子层,第一子层的材料采用氮化硼铝,第二子层的材料采用氮化铟镓。本发明氮化硼铝提高电子阻挡层的能级,升高导带的能级,同时降低价带的能级,增大导带和价带之间的禁带宽度,增强对电子的阻挡效果,同时增加空穴的注入,从而在有效阻挡电子跃迁到P型半导体层的情况下,有利于空穴注入有源层,增加注入有源层的空穴数量,提高LED的发光效率。
The invention discloses a light-emitting diode epitaxial wafer and a preparation method thereof, belonging to the technical field of semiconductors. The epitaxial wafer includes a substrate and a buffer layer, an N-type semiconductor layer, an active layer, an electron blocking layer, and a P-type semiconductor layer stacked on the substrate in sequence. The buffer layer and the electron blocking layer include multiple composite structures stacked in sequence, each A composite structure includes a first sublayer and a second sublayer stacked in sequence, the material of the first sublayer is aluminum boron nitride, and the material of the second sublayer is indium gallium nitride. The aluminum boron nitride of the present invention increases the energy level of the electron blocking layer, raises the energy level of the conduction band, reduces the energy level of the valence band, increases the forbidden band width between the conduction band and the valence band, and enhances the blocking effect on electrons At the same time, the injection of holes is increased, so that under the condition of effectively blocking the transition of electrons to the P-type semiconductor layer, it is beneficial to inject holes into the active layer, increase the number of holes injected into the active layer, and improve the luminous efficiency of the LED.
Description
技术领域technical field
本发明涉及半导体技术领域,特别涉及一种发光二极管外延片。The invention relates to the technical field of semiconductors, in particular to a light-emitting diode epitaxial wafer.
背景技术Background technique
发光二极管(英文:Light Emitting Diode,简称:LED)是一种能发光的半导体电子组件。LED具有节能环保、可靠性高、使用寿命长等优点,因此目前受到越来越多的关注和研究。A light-emitting diode (English: Light Emitting Diode, referred to as: LED) is a semiconductor electronic component that can emit light. LED has the advantages of energy saving and environmental protection, high reliability, long service life, etc., so it is currently receiving more and more attention and research.
外延片是LED制备过程中的初级成品。现有的LED外延片包括衬底、缓冲层、N型半导体层、有源层、电子阻挡层和P型半导体层,缓冲层、N型半导体层、有源层、电子阻挡层和P型半导体层依次层叠在衬底上。衬底用于为外延材料提供生长表面,缓冲层用于缓解衬底和N型半导体层之间的晶格失配,N型半导体层用于提供进行复合发光的电子,P型半导体层用于提供进行复合发光的空穴,有源层用于进行电子和空穴的复合发光,电子阻挡层用于阻挡电子跃迁到P型半导体层与空穴进行非辐射复合。Epitaxial wafers are the primary products in the LED manufacturing process. Existing LED epitaxial wafers include substrate, buffer layer, N-type semiconductor layer, active layer, electron blocking layer and P-type semiconductor layer, buffer layer, N-type semiconductor layer, active layer, electron blocking layer and P-type semiconductor layer Layers are stacked sequentially on the substrate. The substrate is used to provide a growth surface for epitaxial materials, the buffer layer is used to alleviate the lattice mismatch between the substrate and the N-type semiconductor layer, the N-type semiconductor layer is used to provide electrons for recombination and light emission, and the P-type semiconductor layer is used for Holes for recombination luminescence are provided, the active layer is used for recombination luminescence of electrons and holes, and the electron blocking layer is used for blocking electrons from transitioning to the P-type semiconductor layer for non-radiative recombination with holes.
在实现本发明的过程中,发明人发现现有技术至少存在以下问题:In the process of realizing the present invention, the inventor finds that there are at least the following problems in the prior art:
电子阻挡层通常采用厚度大于50nm的氮化铝镓(AlGaN)实现。如果电子阻挡层的厚度太小,则可能无法有效阻挡电子跃迁到P型半导体层,导致P型半导体层中发生非辐射复合。如果电子阻挡层的厚度太大,虽然可以有效阻挡电子跃迁到P型半导体层,但是同时也可能限制P型半导体层的空穴注入有源层与电子进行辐射复合发光。The electron blocking layer is usually implemented with aluminum gallium nitride (AlGaN) with a thickness greater than 50nm. If the thickness of the electron blocking layer is too small, it may not be able to effectively block the transition of electrons to the P-type semiconductor layer, resulting in non-radiative recombination in the P-type semiconductor layer. If the thickness of the electron blocking layer is too large, although it can effectively block the transition of electrons to the P-type semiconductor layer, it may also limit the hole injection of the P-type semiconductor layer into the active layer and electrons to perform radiative recombination and light emission.
发明内容Contents of the invention
本发明实施例提供了一种发光二极管外延片及其制备方法,能够解决无法有效阻挡电子跃迁到P型半导体层或者限制P型半导体层的空穴注入有源层与电子进行辐射复合发光的问题。所述技术方案如下:The embodiment of the present invention provides a light-emitting diode epitaxial wafer and a preparation method thereof, which can solve the problem of being unable to effectively block the transition of electrons to the P-type semiconductor layer or limit the hole injection of the P-type semiconductor layer into the active layer and electrons to perform radiative recombination and light emission. . Described technical scheme is as follows:
一方面,本发明实施例提供了一种发光二极管外延片,所述发光二极管外延片包括衬底、缓冲层、N型半导体层、有源层、电子阻挡层和P型半导体层,所述缓冲层,所述N型半导体层、所述有源层、所述电子阻挡层和所述P型半导体层依次层叠在所述衬底上,所述电子阻挡层包括依次层叠的多个复合结构,每个所述复合结构包括依次层叠的第一子层和第二子层,所述第一子层的材料采用氮化硼铝,所述第二子层的材料采用氮化铟镓。On the one hand, an embodiment of the present invention provides a light-emitting diode epitaxial wafer, the light-emitting diode epitaxial wafer includes a substrate, a buffer layer, an N-type semiconductor layer, an active layer, an electron blocking layer, and a P-type semiconductor layer, and the buffer layer, the N-type semiconductor layer, the active layer, the electron blocking layer and the P-type semiconductor layer are sequentially stacked on the substrate, and the electron blocking layer includes a plurality of composite structures stacked in sequence, Each of the composite structures includes a first sublayer and a second sublayer stacked in sequence, the first sublayer is made of aluminum boron nitride, and the second sublayer is made of indium gallium nitride.
可选地,所述电子阻挡层的厚度为10nm~15nm。Optionally, the electron blocking layer has a thickness of 10 nm˜15 nm.
可选地,所述复合结构的数量为2个~4个。Optionally, the number of the composite structures is 2-4.
可选地,每个所述复合结构还包括第三子层,所述第三子层设置在所述第一子层和所述第二子层之间,所述第三子层的材料采用氮化铝镓。Optionally, each of the composite structures further includes a third sublayer, the third sublayer is arranged between the first sublayer and the second sublayer, and the material of the third sublayer adopts Aluminum Gallium Nitride.
优选地,所述第三子层的材料采用AlyGa1-yN,0.2≤y≤0.4。Preferably, the material of the third sublayer is AlyGa1 -yN , 0.2≤y≤0.4.
可选地,所述第一子层的材料采用BxAl1-xN,0.1≤x≤0.2。Optionally, the material of the first sublayer is B x Al 1-x N, 0.1≤x≤0.2.
可选地,所述第二子层的材料采用InzGa1-zN,0.02≤z≤0.2。Optionally, the material of the second sublayer is In z Ga 1-z N, 0.02≤z≤0.2.
另一方面,本发明实施例提供了一种发光二极管外延片的制备方法,所述制备方法包括:On the other hand, an embodiment of the present invention provides a method for preparing a light-emitting diode epitaxial wafer, the preparation method comprising:
提供一衬底;providing a substrate;
在所述衬底上依次生长缓冲层、N型半导体层、有源层、电子阻挡层和P型半导体层;sequentially growing a buffer layer, an N-type semiconductor layer, an active layer, an electron blocking layer, and a P-type semiconductor layer on the substrate;
其中,所述电子阻挡层包括依次层叠的多个复合结构,每个所述复合结构包括依次层叠的第一子层和第二子层,所述第一子层的材料采用氮化硼铝,所述第二子层的材料采用氮化铟镓。Wherein, the electron blocking layer includes a plurality of composite structures stacked in sequence, each of the composite structures includes a first sublayer and a second sublayer stacked in sequence, and the material of the first sublayer is aluminum boron nitride, The material of the second sublayer is InGaN.
可选地,所述电子阻挡层的生长温度为900℃~1200℃。Optionally, the growth temperature of the electron blocking layer is 900°C-1200°C.
可选地,所述电子阻挡层的生长压力为100torr~300torr。Optionally, the growth pressure of the electron blocking layer is 100 torr-300 torr.
本发明实施例提供的技术方案带来的有益效果是:The beneficial effects brought by the technical solution provided by the embodiments of the present invention are:
通过将电子阻挡层设计为依次层叠的多个复合结构,每个复合结构包括第一子层和第二子层,第一子层的材料采用氮化硼铝,与氮化铝镓相比,氮化硼铝可以提高电子阻挡层的能级,升高导带的能级,同时降低价带的能级,增大导带和价带之间的禁带宽度,增强对电子的阻挡效果,同时增加空穴的注入,从而在有效阻挡电子跃迁到P型半导体层的情况下,有利于空穴注入有源层,增加注入有源层的空穴数量,提高LED的发光效率。而且第二子层的材料采用氮化铟镓,可以蓄积空穴,有利于空穴注入有源层,进一步增加注入有源层的空穴数量,提高LED的发光效率。另外,第一子层和第二子层交替层叠形成超晶格结构,可以缓解第一子层和第二子层之间由于异质材料而产生的应力。By designing the electron blocking layer as multiple composite structures stacked in sequence, each composite structure includes a first sublayer and a second sublayer, and the material of the first sublayer is aluminum boron nitride. Compared with aluminum gallium nitride, Aluminum boron nitride can increase the energy level of the electron blocking layer, increase the energy level of the conduction band, reduce the energy level of the valence band, increase the forbidden band width between the conduction band and the valence band, and enhance the blocking effect on electrons. At the same time, the injection of holes is increased, so that under the condition of effectively blocking the transition of electrons to the P-type semiconductor layer, it is beneficial to inject holes into the active layer, increase the number of holes injected into the active layer, and improve the luminous efficiency of the LED. Moreover, the material of the second sub-layer is InGaN, which can accumulate holes, which is beneficial for hole injection into the active layer, further increases the number of holes injected into the active layer, and improves the luminous efficiency of the LED. In addition, the first sublayer and the second sublayer are laminated alternately to form a superlattice structure, which can relieve the stress between the first sublayer and the second sublayer due to heterogeneous materials.
附图说明Description of drawings
为了更清楚地说明本发明实施例中的技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained based on these drawings without creative effort.
图1是本发明实施例提供的一种发光二极管外延片的结构示意图;FIG. 1 is a schematic structural view of a light-emitting diode epitaxial wafer provided by an embodiment of the present invention;
图2是本发明实施例提供的一种电子阻挡层的结构示意图;Fig. 2 is a schematic structural view of an electron blocking layer provided by an embodiment of the present invention;
图3是本发明实施例提供的另一种电子阻挡层的结构示意图;Fig. 3 is a schematic structural diagram of another electron blocking layer provided by an embodiment of the present invention;
图4是本发明实施例提供的一种发光二极管外延片的制备方法的流程图。Fig. 4 is a flow chart of a method for manufacturing a light-emitting diode epitaxial wafer provided by an embodiment of the present invention.
具体实施方式Detailed ways
为使本发明的目的、技术方案和优点更加清楚,下面将结合附图对本发明实施方式作进一步地详细描述。In order to make the object, technical solution and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below in conjunction with the accompanying drawings.
本发明实施例提供了一种发光二极管外延片,图1为本发明实施例提供的发光二极管外延片的结构示意图,参见图1,该发光二极管外延片包括衬底1、缓冲层2、N型半导体层3、有源层4、电子阻挡层5和P型半导体层6,缓冲层2、N型半导体层3、有源层4、电子阻挡层5和P型半导体层6依次层叠在衬底1上。An embodiment of the present invention provides a light-emitting diode epitaxial wafer. FIG. 1 is a schematic structural diagram of a light-emitting diode epitaxial wafer provided by an embodiment of the present invention. Referring to FIG. 1, the light-emitting diode epitaxial wafer includes a substrate 1, a buffer layer 2, an N-type The semiconductor layer 3, the active layer 4, the electron blocking layer 5 and the P-type semiconductor layer 6, the buffer layer 2, the N-type semiconductor layer 3, the active layer 4, the electron blocking layer 5 and the P-type semiconductor layer 6 are sequentially stacked on the substrate 1 on.
图2为本发明实施例提供的一种电子阻挡层的结构示意图。参见图2,在本实施例中,电子阻挡层6包括依次层叠的多个复合结构60,每个复合结构60包括依次层叠的第一子层61和第二子层62,第一子层的61材料采用氮化硼铝(BAlN),第二子层62的材料采用氮化铟镓(InGaN)。FIG. 2 is a schematic structural diagram of an electron blocking layer provided by an embodiment of the present invention. Referring to FIG. 2, in this embodiment, the electron blocking layer 6 includes a plurality of composite structures 60 stacked in sequence, and each composite structure 60 includes a first sublayer 61 and a second sublayer 62 stacked in sequence, and the first sublayer The material of 61 is boron aluminum nitride (BAlN), and the material of the second sublayer 62 is indium gallium nitride (InGaN).
本发明实施例通过将电子阻挡层设计为依次层叠的多个复合结构,每个复合结构包括第一子层和第二子层,第一子层的材料采用氮化硼铝,与氮化铝镓相比,氮化硼铝可以提高电子阻挡层的能级,升高导带的能级,同时降低价带的能级,增大导带和价带之间的禁带宽度,增强对电子的阻挡效果,同时增加空穴的注入,从而在有效阻挡电子跃迁到P型半导体层的情况下,有利于空穴注入有源层,增加注入有源层的空穴数量,提高LED的发光效率。而且第二子层的材料采用氮化铟镓,可以蓄积空穴,有利于空穴注入有源层,进一步增加注入有源层的空穴数量,提高LED的发光效率。另外,第一子层和第二子层交替层叠形成超晶格结构,可以缓解第一子层和第二子层之间由于异质材料而产生的应力。In the embodiment of the present invention, the electron blocking layer is designed as a plurality of composite structures stacked in sequence, each composite structure includes a first sublayer and a second sublayer, the material of the first sublayer is aluminum boron nitride, and aluminum nitride Compared with gallium, aluminum boron nitride can increase the energy level of the electron blocking layer, increase the energy level of the conduction band, reduce the energy level of the valence band, increase the forbidden band width between the conduction band and the valence band, and enhance the electron The blocking effect, while increasing the injection of holes, so that in the case of effectively blocking the transition of electrons to the P-type semiconductor layer, it is beneficial to inject holes into the active layer, increase the number of holes injected into the active layer, and improve the luminous efficiency of the LED . Moreover, the material of the second sub-layer is InGaN, which can accumulate holes, which is beneficial for hole injection into the active layer, further increases the number of holes injected into the active layer, and improves the luminous efficiency of the LED. In addition, the first sublayer and the second sublayer are laminated alternately to form a superlattice structure, which can relieve the stress between the first sublayer and the second sublayer due to heterogeneous materials.
在具体实现时,电子阻挡层中可以掺杂P型掺杂剂,如镁(Mg),也不可以不掺杂P型掺杂剂。具体地,当电子阻挡层中掺杂P型掺杂剂时,电子阻挡层中P型掺杂剂的掺杂浓度可以为3*1017/cm3~8*1017/cm3。In a specific implementation, the electron blocking layer may be doped with a P-type dopant, such as magnesium (Mg), or may not be doped with a P-type dopant. Specifically, when the electron blocking layer is doped with a P-type dopant, the doping concentration of the P-type dopant in the electron blocking layer may be 3*10 17 /cm 3 -8*10 17 /cm 3 .
可选地,电子阻挡层6的厚度可以为10nm~15nm,优选为12nm或15nm。Optionally, the thickness of the electron blocking layer 6 may be 10 nm˜15 nm, preferably 12 nm or 15 nm.
为了有效避免电子跃迁到P型半导体层中与空穴进行非辐射发光,电子阻挡层的厚度通常会大于50nm,导致电子阻挡层的厚度太大,一方面会影响有源层发出光线从LED内射出,另一方面还会增大LED内的串联电阻,造成LED的正向导通电压升高。本发明实施例利用氮化硼铝对电子较强的阻挡作用,将电子阻挡层的厚度减小至10nm~15nm,可以有效避免对LED的出光效率和正向导通电压造成不良影响,提高了LED的出光效率,降低了LED的正向导通电压。In order to effectively prevent electrons from transitioning into the P-type semiconductor layer and holes for non-radiative luminescence, the thickness of the electron blocking layer is usually greater than 50nm, resulting in too large a thickness of the electron blocking layer. On the one hand, it will affect the light emitted by the active layer from the inside of the LED. On the other hand, it will increase the series resistance in the LED, causing the forward voltage of the LED to increase. The embodiment of the present invention utilizes the strong blocking effect of aluminum boron nitride on electrons to reduce the thickness of the electron blocking layer to 10nm to 15nm, which can effectively avoid adverse effects on the light extraction efficiency and forward conduction voltage of the LED, and improve the performance of the LED. The light extraction efficiency reduces the forward conduction voltage of the LED.
如果电子阻挡层的厚度小于10nm,则可能由于电子阻挡层的厚度太小而无法有效阻挡电子跃迁到P型半导体层中,造成LED溢流,影响LED的可靠性和使用寿命;如果电子阻挡层的厚度大于15nm,则可能无法进一步有效提升对电子的阻挡作用和空穴的注入效率,造成材料的浪费,若电子阻挡层的厚度大于50nm,还可能影响LED的出光效率和正向导通电压。If the thickness of the electron blocking layer is less than 10nm, the electronic blocking layer may not be able to effectively block the transition of electrons into the P-type semiconductor layer due to the thickness of the electron blocking layer, which will cause LED overflow and affect the reliability and service life of the LED; if the electron blocking layer If the thickness of the electron blocking layer is greater than 15nm, it may not be able to further effectively improve the blocking effect on electrons and the injection efficiency of holes, resulting in waste of materials. If the thickness of the electron blocking layer is greater than 50nm, it may also affect the light extraction efficiency and forward conduction voltage of the LED.
可选地,复合结构60的数量可以为2个~4个,优选为3个。Optionally, the number of composite structures 60 may be 2 to 4, preferably 3.
如果复合结构的数量小于2个,则无法形成超晶格结构,导致电子阻挡层内的应力较大,进而影响外延片的晶体质量,降低LED的发光效率,还可能由于复合结构的数量太少而无法有效阻挡电子跃迁到P型半导体层中,造成LED溢流;如果复合结构的数量大于4个,则可能由于复合结构的数量太多而造成电子阻挡层的厚度增大,一方面会影响有源层发出光线从LED内射出,另一方面还会增大LED内的串联电阻,造成LED的正向导通电压升高。If the number of composite structures is less than 2, the superlattice structure cannot be formed, resulting in greater stress in the electron blocking layer, which in turn affects the crystal quality of the epitaxial wafer and reduces the luminous efficiency of the LED. It may also be due to the fact that the number of composite structures is too small However, it cannot effectively block the transition of electrons into the P-type semiconductor layer, causing LED overflow; if the number of composite structures is greater than 4, the thickness of the electron blocking layer may increase due to the large number of composite structures, which will affect the The active layer emits light from the LED, and on the other hand, it also increases the series resistance in the LED, resulting in an increase in the forward conduction voltage of the LED.
可选地,第一子层61的材料可以采用BxAl1-xN,0.1≤x≤0.2,优选x=0.14。Optionally, the material of the first sublayer 61 can be B x Al 1-x N, 0.1≤x≤0.2, preferably x=0.14.
如果x<0.1,则可能由于第一子层中硼组分的摩尔含量太低而无法有效阻挡电子跃迁到P型半导体层中,造成LED溢流,影响LED的可靠性和使用寿命,还可能为了有效避免阻挡电子跃迁到P型半导体层中与空穴进行非辐射复合而增大电子阻挡层的厚度,导致电子阻挡层的厚度太大,进而影响LED的出光效率和正向导通电压;如果x>0.2,则可能由于第一子层中硼组分的摩尔含量太高而导致电子阻挡层内部应力太大,影响外延片的晶体质量,反而会降低LED的发光效率。If x<0.1, it may be that the molar content of the boron component in the first sublayer is too low to effectively block electrons from transitioning into the P-type semiconductor layer, causing LED overflow, affecting the reliability and service life of the LED, and possibly In order to effectively avoid preventing electrons from jumping into the P-type semiconductor layer for non-radiative recombination with holes, the thickness of the electron blocking layer is increased, resulting in too large thickness of the electron blocking layer, which affects the light extraction efficiency and forward conduction voltage of the LED; if x >0.2, it may be that the internal stress of the electron blocking layer is too high due to too high molar content of the boron component in the first sub-layer, which affects the crystal quality of the epitaxial wafer and reduces the luminous efficiency of the LED on the contrary.
可选地,第二子层62的材料可以采用InzGa1-zN,0.02≤z≤0.2,优选z=0.1。Optionally, the material of the second sublayer 62 may be In z Ga 1-z N, 0.02≤z≤0.2, preferably z=0.1.
如果z<0.02,则可能由于第二子层中铟组分的摩尔含量太低而无法起到蓄积作用,从而达不到增加注入有源层的空穴数量的效果;如果z>0.2,则可能由于第二子层中铟组分的摩尔含量太高而导致电子阻挡层的晶体质量较差,进而影响外延片整体的晶体质量,造成LED的发光效率降低。If z<0.02, the molar content of the indium component in the second sublayer may be too low to play a role in accumulation, thereby failing to achieve the effect of increasing the number of holes injected into the active layer; if z>0.2, then It may be that the crystal quality of the electron blocking layer is poor because the molar content of the indium component in the second sublayer is too high, which further affects the crystal quality of the epitaxial wafer as a whole, resulting in a decrease in the luminous efficiency of the LED.
在上述实现方式中,即复合结构60由如图2所示的第一子层61和第二子层62组成时,第一子层61的厚度可以为2nm~3nm,优选为2nm;第二子层62的厚度可以为2nm~5nm,优选为2nm。In the above implementation manner, that is, when the composite structure 60 is composed of the first sublayer 61 and the second sublayer 62 as shown in FIG. 2 , the thickness of the first sublayer 61 can be 2 nm to 3 nm, preferably 2 nm; The thickness of the sublayer 62 may be 2nm˜5nm, preferably 2nm.
如果第一子层的厚度小于2nm,则可能由于第一子层太薄而无法有效阻挡电子跃迁到P型半导体层中,造成LED溢流,影响LED的可靠性和使用寿命,还可能为了有效避免阻挡电子跃迁到P型半导体层中与空穴进行非辐射复合而增大第一子层中硼组分的摩尔含量,导致硼组分的摩尔含量太高,进而造成电子阻挡层内部应力太大,影响外延片的晶体质量,反而会降低LED的发光效率;如果第一子层的厚度大于3nm,则可能由于第一子层太厚而导致电子阻挡层的厚度太大,进而影响LED的出光效率和正向导通电压。If the thickness of the first sub-layer is less than 2nm, it may be that the first sub-layer is too thin to effectively block the transition of electrons into the P-type semiconductor layer, resulting in LED overflow, which affects the reliability and service life of the LED. Avoid blocking the transition of electrons to the P-type semiconductor layer for non-radiative recombination with holes to increase the molar content of the boron component in the first sublayer, resulting in too high a molar content of the boron component, which in turn causes too much internal stress in the electron blocking layer. If the thickness of the first sublayer is greater than 3nm, it may cause the thickness of the electron blocking layer to be too large due to the thickness of the first sublayer, which will affect the LED's luminous efficiency. Light extraction efficiency and forward voltage.
如果第二子层的厚度小于2nm,则可能由于第二子层太薄而无法起到蓄积作用,从而达不到增加注入有源层的空穴数量的效果;如果第二子层的厚度大于5nm,则可能由于第三子层太厚而导致电子阻挡层的厚度太大,进而影响LED的出光效率和正向导通电压,同时还可能造成电子阻挡层的晶体质量较差,进而影响外延片整体的晶体质量,造成LED的发光效率降低。If the thickness of the second sublayer is less than 2nm, it may not be able to accumulate because the second sublayer is too thin to achieve the effect of increasing the number of holes injected into the active layer; if the thickness of the second sublayer is greater than 5nm, the thickness of the electron blocking layer may be too large because the third sublayer is too thick, which will affect the light extraction efficiency and forward conduction voltage of the LED. At the same time, the crystal quality of the electron blocking layer may be poor, which will affect the overall epitaxial wafer The quality of the crystal will reduce the luminous efficiency of the LED.
图3为本发明实施例提供的另一种电子阻挡层的结构示意图。参见图3,可选地,每个复合结构60除了包括第一子层61和第二子层62之外,还可以包括第三子层63,第三子层63设置在第一子层61和第二子层62之间,第三子层63的材料采用氮化铝镓。FIG. 3 is a schematic structural diagram of another electron blocking layer provided by an embodiment of the present invention. Referring to FIG. 3 , optionally, each composite structure 60 may include a third sublayer 63 in addition to the first sublayer 61 and the second sublayer 62, and the third sublayer 63 is arranged on the first sublayer 61. Between the second sublayer 62 and the third sublayer 63 is made of AlGaN.
采用氮化硼铝形成的第一子层和采用氮化铟镓形成的第二子层之间存在较大的晶格失配,导致电子阻挡层的晶体质量较差,进而造成外延片整体的晶体质量较差,影响LED的发光效率。本发明实施例采用氮化铝镓形成的第三子层插在第一子层和第二子层中间,可以有效缓解第一子层和第二子层之间的晶格失配,提高电子阻挡层的晶体质量,避免对LED的发光效率造成不良影响。而且氮化铝镓的能级较高,还可以加强对电子的阻挡作用,进一步避免电子跃迁到P型半导体层中与空穴进行非辐射复合。There is a large lattice mismatch between the first sublayer formed with aluminum boron nitride and the second sublayer formed with indium gallium nitride, resulting in poor crystal quality of the electron blocking layer, which in turn causes the overall epitaxial wafer The quality of the crystal is poor, which affects the luminous efficiency of the LED. In the embodiment of the present invention, the third sublayer formed by aluminum gallium nitride is inserted between the first sublayer and the second sublayer, which can effectively alleviate the lattice mismatch between the first sublayer and the second sublayer, and improve the electron density. The crystal quality of the barrier layer can avoid adverse effects on the luminous efficiency of the LED. Moreover, AlGaN has a higher energy level, which can also strengthen the blocking effect on electrons, and further prevent electrons from transitioning into the P-type semiconductor layer to perform non-radiative recombination with holes.
优选地,第三子层63的材料可以采用AlyGa1-yN,0.2≤y≤0.4,优选y=0.3。Preferably, the material of the third sublayer 63 may be AlyGa1 -yN , 0.2≤y≤0.4, preferably y=0.3.
如果y<0.2,则可能由于第三子层中铝组分的摩尔含量太低而造成与采用氮化硼铝形成的第一子层之间晶格不匹配,影响电子阻挡层的晶体质量,最终造成LED的发光效率较低;如果y>0.4,则可能由于第三子层中镓组分的摩尔含量太低而造成与采用氮化铟镓形成的第二子层之间晶格不匹配,同样也会影响电子阻挡层的晶体质量,最终造成LED的发光效率较低。If y<0.2, the lattice mismatch between the first sublayer formed by aluminum boron nitride may be caused due to the low molar content of the aluminum component in the third sublayer, which affects the crystal quality of the electron blocking layer, Finally, the luminous efficiency of the LED is low; if y>0.4, the molar content of the gallium component in the third sublayer may be too low to cause a lattice mismatch with the second sublayer formed by using InGaN , will also affect the crystal quality of the electron blocking layer, and finally cause the luminous efficiency of the LED to be low.
在上述实现方式中,即复合结构60由如图3所示的第一子层61、第三子层63和第二子层62组成时,第一子层61的厚度可以为2nm~3nm,优选为2nm;第三子层63的厚度为1nm~3.5nm,优选为1nm;第二子层62的厚度为2nm~4.5nm,优选为2nm。In the above implementation manner, that is, when the composite structure 60 is composed of the first sublayer 61, the third sublayer 63 and the second sublayer 62 as shown in FIG. It is preferably 2 nm; the thickness of the third sublayer 63 is 1 nm˜3.5 nm, preferably 1 nm; the thickness of the second sublayer 62 is 2 nm˜4.5 nm, preferably 2 nm.
如果第三子层的厚度小于1nm,则可能由于第三子层太薄而无法有效缓解第一子层和第二子层之间的晶格失配,造成电子阻挡层的晶体质量较差,最终造成LED的发光效率较低;如果第三子层的厚度大于3.5nm,则可能由于第三子层太厚而导致电子阻挡层整体的厚度太大,进而影响LED的出光效率和正向导通电压。If the thickness of the third sublayer is less than 1 nm, it may be that the third sublayer is too thin to effectively alleviate the lattice mismatch between the first sublayer and the second sublayer, resulting in poor crystal quality of the electron blocking layer, Finally, the luminous efficiency of the LED is low; if the thickness of the third sublayer is greater than 3.5nm, the overall thickness of the electron blocking layer may be too large due to the thickness of the third sublayer, which will affect the light extraction efficiency and forward conduction voltage of the LED. .
另外,与复合结构60由如图2所示的第一子层61和第二子层62组成时一样,如果第一子层的厚度小于2nm,则可能由于第一子层太薄而无法有效阻挡电子跃迁到P型半导体层中,造成LED溢流,影响LED的可靠性和使用寿命,还可能为了有效避免阻挡电子跃迁到P型半导体层中与空穴进行非辐射复合而增大第一子层中硼组分的摩尔含量,导致硼组分的摩尔含量太高,进而造成电子阻挡层内部应力太大,影响外延片的晶体质量,反而会降低LED的发光效率;如果第一子层的厚度大于3nm,则可能由于第一子层太厚而导致电子阻挡层的厚度太大,进而影响LED的出光效率和正向导通电压。In addition, as when the composite structure 60 is composed of the first sublayer 61 and the second sublayer 62 as shown in FIG. Prevent electrons from transitioning into the P-type semiconductor layer, causing LED overflow, affecting the reliability and service life of the LED, and may also increase the first The molar content of the boron component in the sublayer causes the molar content of the boron component to be too high, which in turn causes too much internal stress in the electron blocking layer, affects the crystal quality of the epitaxial wafer, and reduces the luminous efficiency of the LED instead; if the first sublayer If the thickness is greater than 3nm, the thickness of the electron blocking layer may be too large because the first sub-layer is too thick, thereby affecting the light extraction efficiency and forward conduction voltage of the LED.
如果第二子层的厚度小于2nm,则可能由于第二子层太薄而无法起到蓄积作用,从而达不到增加注入有源层的空穴数量的效果;如果第二子层的厚度大于4.5nm,则可能由于第三子层太厚而导致电子阻挡层整体的厚度太大,进而影响LED的出光效率和正向导通电压。If the thickness of the second sublayer is less than 2nm, it may not be able to accumulate because the second sublayer is too thin to achieve the effect of increasing the number of holes injected into the active layer; if the thickness of the second sublayer is greater than 4.5nm, the overall thickness of the electron blocking layer may be too large because the third sub-layer is too thick, thereby affecting the light extraction efficiency and forward conduction voltage of the LED.
具体地,衬底1的材料可以采用蓝宝石,优选为[0001]晶向的蓝宝石。缓冲层2的材料可以采用氮化铝或者氮化镓。N型半导体层3的材料可以采用N型掺杂(如硅)的氮化镓。有源层4可以包括多个量子阱和多个量子垒,多个量子阱和多个量子垒交替层叠设置;量子阱的材料可以采用氮化铟镓,如IntGa1-tN,0<t<1;量子垒的材料可以采用氮化镓。P型半导体层6的材料可以采用P型掺杂(如镁)的氮化镓。Specifically, the material of the substrate 1 can be sapphire, preferably sapphire with [0001] crystal orientation. The material of the buffer layer 2 can be aluminum nitride or gallium nitride. The material of the N-type semiconductor layer 3 can be N-type doped (such as silicon) gallium nitride. The active layer 4 can include multiple quantum wells and multiple quantum barriers, and multiple quantum wells and multiple quantum barriers are alternately stacked; the material of the quantum wells can be indium gallium nitride, such as In t Ga 1-t N,0 <t<1; gallium nitride can be used as the material of the quantum barrier. The material of the P-type semiconductor layer 6 can be P-type doped (such as magnesium) gallium nitride.
进一步地,缓冲层2的厚度可以为15nm~35nm,优选为25nm。N型半导体层3的厚度可以为1μm~5μm,优选为3μm;N型半导体层3中N型掺杂剂的掺杂浓度可以为1018cm-3~1019cm-3,优选为5*1018cm-3。量子阱的厚度可以为2.5nm~3.5nm,优选为3nm;量子垒的厚度可以为9nm~20nm,优选为15nm;量子阱的数量与量子垒的数量相同,量子垒的数量可以为5个~11个,优选为8个。P型半导体层6的厚度可以为100nm~800nm,优选为450nm;P型半导体层6中P型掺杂剂的掺杂浓度可以为3*1017/cm3~8*1017/cm3。Further, the thickness of the buffer layer 2 may be 15nm-35nm, preferably 25nm. The thickness of the N-type semiconductor layer 3 can be 1 μm to 5 μm, preferably 3 μm; the doping concentration of the N-type dopant in the N-type semiconductor layer 3 can be 10 18 cm -3 to 10 19 cm -3 , preferably 5* 10 18 cm -3 . The thickness of quantum well can be 2.5nm~3.5nm, is preferably 3nm; The thickness of quantum barrier can be 9nm~20nm, is preferably 15nm; The quantity of quantum well is identical with the quantity of quantum barrier, and the quantity of quantum barrier can be 5~ 11, preferably 8. The thickness of the P-type semiconductor layer 6 may be 100nm-800nm, preferably 450nm; the doping concentration of the P-type dopant in the P-type semiconductor layer 6 may be 3*10 17 /cm 3 -8*10 17 /cm 3 .
可选地,如图1所示,该发光二极管外延片还可以包括未掺杂氮化镓层7,未掺杂氮化镓层7设置在缓冲层2和N型半导体层3之间,以进一步缓解衬底和N型半导体层之间的晶格失配,提高外延片整体的晶体质量,进而提高LED的发光效率。Optionally, as shown in FIG. 1, the light-emitting diode epitaxial wafer may further include an undoped gallium nitride layer 7, and the undoped gallium nitride layer 7 is arranged between the buffer layer 2 and the N-type semiconductor layer 3, so as to Further alleviate the lattice mismatch between the substrate and the N-type semiconductor layer, improve the overall crystal quality of the epitaxial wafer, and then improve the luminous efficiency of the LED.
进一步地,未掺杂氮化镓层7的厚度可以为1μm~5μm,优选为3μm。Further, the thickness of the undoped gallium nitride layer 7 may be 1 μm˜5 μm, preferably 3 μm.
可选地,如图1所示,该发光二极管外延片还可以包括P型接触层8,P型接触层8设置在P型半导体层6上,实现外延片与芯片制作过程中形成的电极或者透明导电薄膜之间的欧姆接触。Optionally, as shown in FIG. 1, the light emitting diode epitaxial wafer may also include a P-type contact layer 8, which is disposed on the P-type semiconductor layer 6, so as to realize the electrodes or electrodes formed during the fabrication process of the epitaxial wafer and the chip. Ohmic contact between transparent conductive films.
具体地,P型接触层8的材料可以采用P型掺杂的氮化铟镓。Specifically, the material of the P-type contact layer 8 can be P-type doped InGaN.
进一步地,P型接触层8的厚度可以为5nm~300nm,优选为150nm;P型接触层8中P型掺杂剂的掺杂浓度可以为3*1017/cm3~8*1017/cm3。Further, the thickness of the P-type contact layer 8 may be 5 nm to 300 nm, preferably 150 nm; the doping concentration of the P-type dopant in the P-type contact layer 8 may be 3*10 17 /cm 3 to 8*10 17 /cm 3 cm 3 .
本发明实施例提供了一种发光二极管外延片的制备方法,适用于制备图1所示的发光二极管外延片。图4为本发明实施例提供的发光二极管外延片的制备方法的流程图,参见图4,该制备方法包括:An embodiment of the present invention provides a method for preparing a light emitting diode epitaxial wafer, which is suitable for preparing the light emitting diode epitaxial wafer shown in FIG. 1 . Fig. 4 is a flowchart of a method for preparing a light-emitting diode epitaxial wafer provided by an embodiment of the present invention. Referring to Fig. 4, the preparation method includes:
步骤201:提供一衬底。Step 201: Provide a substrate.
可选地,该步骤201可以包括:Optionally, this step 201 may include:
控制温度为1000℃~1200℃(优选为1100℃),在氢气气氛中对衬底进行6分钟~10分钟(优选为8分钟)退火处理;Controlling the temperature to 1000°C to 1200°C (preferably 1100°C), annealing the substrate in a hydrogen atmosphere for 6 minutes to 10 minutes (preferably 8 minutes);
对衬底进行氮化处理。The substrate is nitrided.
通过上述步骤清洁衬底的表面,避免杂质掺入外延片中,有利于提高外延片的生长质量。Cleaning the surface of the substrate through the above steps prevents impurities from being mixed into the epitaxial wafer, which is beneficial to improving the growth quality of the epitaxial wafer.
步骤202:在衬底上依次生长缓冲层、N型半导体层、有源层、电子阻挡层和P型半导体层。Step 202: growing a buffer layer, an N-type semiconductor layer, an active layer, an electron blocking layer and a P-type semiconductor layer sequentially on the substrate.
在本实施例中,电子阻挡层包括依次层叠的多个复合结构,每个复合结构包括依次层叠的第一子层和第二子层,第一子层的材料采用氮化硼铝,第二子层的材料采用氮化铟镓。In this embodiment, the electron blocking layer includes a plurality of composite structures stacked in sequence, and each composite structure includes a first sublayer and a second sublayer stacked in sequence, the material of the first sublayer is aluminum boron nitride, and the second sublayer is made of aluminum boron nitride. The material of the sublayer is InGaN.
可选地,电子阻挡层的生长温度可以为900℃~1200℃。Optionally, the growth temperature of the electron blocking layer may be 900°C-1200°C.
如果电子阻挡层的生长温度低于900℃,则可能由于电子阻挡层的生长温度较低而导致电子阻挡层的晶体质量较差,进而影响外延片整体的晶体质量,造成LED的发光效率降低;如果电子阻挡层的生长温度高于1200℃,则可能由于电子阻挡层的生长温度较高而导致铟的析出,第二子层中铟组分的摩尔含量太低,无法起到蓄积作用,从而达不到增加注入有源层的空穴数量的效果,或者为了保证电子阻挡层中具有一定含量的铟而增大电子阻挡层的厚度,导致电子阻挡层的厚度太大,进而影响LED的出光效率和正向导通电压。If the growth temperature of the electron blocking layer is lower than 900°C, the crystal quality of the electron blocking layer may be poor due to the low growth temperature of the electron blocking layer, which will affect the overall crystal quality of the epitaxial wafer, resulting in a decrease in the luminous efficiency of the LED; If the growth temperature of the electron blocking layer is higher than 1200°C, the precipitation of indium may be caused by the high growth temperature of the electron blocking layer, and the molar content of the indium component in the second sublayer is too low to play the role of accumulation, thus The effect of increasing the number of holes injected into the active layer cannot be achieved, or the thickness of the electron blocking layer is increased in order to ensure a certain content of indium in the electron blocking layer, resulting in the thickness of the electron blocking layer being too large, which in turn affects the light output of the LED efficiency and forward voltage.
进一步地,电子阻挡层的生长温度可以为1090℃~1200℃,优选为1150℃。Further, the growth temperature of the electron blocking layer may be 1090°C to 1200°C, preferably 1150°C.
可选地,电子阻挡层的生长压力可以为100torr~300torr。Optionally, the growth pressure of the electron blocking layer may be 100 torr to 300 torr.
如果电子阻挡层的生长压力低于100torr,则可能由于电子阻挡层的生长压力太低而影响电子阻挡层的生长速率,进而影响外延片整体的生产效率;如果电子阻挡层的生长压力高于300torr,则可能由于电子阻挡层的生长压力太高而影响电子阻挡层的生长质量,进而影响外延片整体的晶体质量,造成LED的发光效率降低。If the growth pressure of the electron blocking layer is lower than 100torr, it may affect the growth rate of the electron blocking layer due to the too low growth pressure of the electron blocking layer, thereby affecting the overall production efficiency of the epitaxial wafer; if the growth pressure of the electron blocking layer is higher than 300torr , it may affect the growth quality of the electron blocking layer because the growth pressure of the electron blocking layer is too high, and then affect the overall crystal quality of the epitaxial wafer, resulting in a decrease in the luminous efficiency of the LED.
进一步地,电子阻挡层的生长压力可以为100torr~190torr,优选为150torr。Further, the growth pressure of the electron blocking layer may be 100 torr to 190 torr, preferably 150 torr.
具体地,该步骤202可以包括:Specifically, this step 202 may include:
第一步,控制温度为400℃~600℃(优选为500℃),压力为400torr~600torr(优选为500torr),在衬底上生长缓冲层;In the first step, the temperature is controlled at 400°C to 600°C (preferably 500°C), the pressure is 400torr to 600torr (preferably 500torr), and a buffer layer is grown on the substrate;
第二步,控制温度为1000℃~1200℃(优选为1100℃),压力为100torr~500torr(优选为300torr),在缓冲层上生长N型半导体层;In the second step, the temperature is controlled at 1000°C to 1200°C (preferably 1100°C), the pressure is 100torr to 500torr (preferably 300torr), and an N-type semiconductor layer is grown on the buffer layer;
第三步,在N型半导体层上生长有源层;其中,量子阱的生长温度为720℃~829℃(优选为770℃),压力为100torr~500torr(优选为300torr);量子垒的生长温度为850℃~959℃(优选为900℃),压力为100torr~500torr(优选为300torr);The third step is to grow an active layer on the N-type semiconductor layer; wherein, the growth temperature of the quantum well is 720°C to 829°C (preferably 770°C), and the pressure is 100torr to 500torr (preferably 300torr); the growth of the quantum barrier The temperature is 850°C to 959°C (preferably 900°C), and the pressure is 100torr to 500torr (preferably 300torr);
第四步,在有源层上生长电子阻挡层;The fourth step is to grow an electron blocking layer on the active layer;
第五步,控制温度为850℃~1080℃(优选为930℃),压力为100torr~300torr(优选为200torr),在电子阻挡层上生长P型半导体层。In the fifth step, control the temperature to 850°C-1080°C (preferably 930°C), and the pressure to 100torr-300torr (preferably 200torr), and grow a P-type semiconductor layer on the electron blocking layer.
可选地,在第一步之后,该制备方法还可以包括:Optionally, after the first step, the preparation method may also include:
控制温度为1000℃~1200℃(优选为1100℃),压力为400torr~600torr(优选为500torr),对缓冲层进行5分钟~10分钟(优选为8分钟)的原位退火处理。The control temperature is 1000°C-1200°C (preferably 1100°C), the pressure is 400torr-600torr (preferably 500torr), and the buffer layer is annealed in situ for 5-10 minutes (preferably 8 minutes).
可选地,在第二步之前,该制备方法还可以包括:Optionally, before the second step, the preparation method may also include:
控制温度为1000℃~1100℃(优选为1050℃),压力为100torr~500torr(优选为300torr),在缓冲层上生长未掺杂氮化镓层。The temperature is controlled to be 1000°C-1100°C (preferably 1050°C), the pressure is 100torr-500torr (preferably 300torr), and an undoped gallium nitride layer is grown on the buffer layer.
相应地,N型半导体层生长在未掺杂氮化镓层上。Accordingly, an N-type semiconductor layer is grown on the undoped GaN layer.
可选地,在第六步之后,该制备方法还可以包括:Optionally, after the sixth step, the preparation method may also include:
控制温度为850℃~1050℃(优选为950℃),压力为100torr~300torr(优选为200torr),在P型半导体层上生长P型接触层。Control the temperature to 850°C-1050°C (preferably 950°C), and the pressure to 100torr-300torr (preferably 200torr), and grow a P-type contact layer on the P-type semiconductor layer.
需要说明的是,在上述外延生长结束之后,会先将温度降低至650℃~850℃(优选为750℃),在氮气气氛中对外延片进行5分钟~15分钟(优选为10分钟)的退火处理,然后再将外延片的温度降低至室温。It should be noted that after the above-mentioned epitaxial growth is completed, the temperature will be lowered to 650° C. to 850° C. (preferably 750° C.), and the epitaxial wafer is grown in a nitrogen atmosphere for 5 minutes to 15 minutes (preferably 10 minutes). Annealing treatment, and then reduce the temperature of the epitaxial wafer to room temperature.
对得到的外延片进行清洗、沉积、光刻和刻蚀等芯片制作工艺,形成单颗大小为9mil*7mil的LED芯片。对LED芯片在工作电流为20mA下进行测试,发现本发明实施例得到的外延片制成的LED芯片,与现有技术得到的外延片制成的LED芯片相比,发光亮度提高了1%-1.5%。The obtained epitaxial wafer is subjected to chip manufacturing processes such as cleaning, deposition, photolithography, and etching to form a single LED chip with a size of 9mil*7mil. The LED chip was tested under a working current of 20mA, and it was found that the LED chip made of the epitaxial wafer obtained in the embodiment of the present invention, compared with the LED chip made of the epitaxial wafer obtained in the prior art, the luminous brightness increased by 1%- 1.5%.
以上所述仅为本发明的较佳实施例,并不用以限制本发明,凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection of the present invention. within range.
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