CN108831974A - A light-emitting diode epitaxial wafer and its manufacturing method - Google Patents

Abstract

The invention discloses a light-emitting diode epitaxial wafer and a manufacturing method thereof, belonging to the technical field of semiconductors. Including substrate, buffer layer, undoped GaN layer, N-type layer, active layer, low-temperature P-type layer, electron blocking layer, high-temperature P-type layer and P-type contact layer, and the electron blocking layer includes N periods Al _x Ga _1‑x N/AlN/GaN/In _y Ga _{1‑ y} N superlattice structure, N is a positive integer greater than or equal to 2, and the thickness of the electron blocking layer is 10-25 nm. Compared with the existing electron blocking layer with a thickness greater than 50nm, the thickness of the electron blocking layer provided by the present invention is greatly reduced, thereby reducing the polarization and stress between materials, and reducing the electron blocking layer in the valence band heterojunction. The valence band order generated by the interface enables holes to be better injected into the active layer, and the concentration of holes increases, and more holes can recombine with electrons in the active layer to emit light, which improves the luminous efficiency of the LED.

Description

A light-emitting diode epitaxial wafer and its manufacturing method

technical field

The invention relates to the technical field of semiconductors, in particular to a light-emitting diode epitaxial wafer and a manufacturing method thereof.

Background technique

LED (Light Emitting Diode, Light Emitting Diode) is a semiconductor electronic component that can emit light. As an efficient, environmentally friendly and green new solid-state lighting source, it is being rapidly and widely used, such as traffic lights, car interior and exterior lights, urban landscape lighting, mobile phone backlights, etc.

The epitaxial wafer is the main component of the LED. The existing GaN-based LED epitaxial wafer includes a substrate and a GaN-based epitaxial layer arranged on the substrate. The GaN-based epitaxial layer includes a buffer layer stacked on the substrate, an undoped Doped GaN layer, N-type layer (N-type region), active layer, electron blocking layer, high-temperature P-type layer (P-type region) and P-type contact layer. The electrons provided by the N-type region and the holes provided by the P-type region recombine and emit light in the active layer. The electron blocking layer is usually an AlGaN layer or a multi-period AlGaN/InGaN superlattice structure, and the thickness of the electron blocking layer is greater than 50 nm.

In the process of realizing the present invention, the inventor finds that there are at least the following problems in the prior art:

In the existing LED epitaxial wafers, the electron blocking layer is designed to be thicker (usually greater than 50nm), and the thicker electron blocking layer will cause polarization and stress between materials, and at the same time, a high valence band will be generated to hinder the direction of holes. The active layer migrates, so the concentration of electrons provided by the N-type region is higher than the concentration of holes provided by the P-type region, and the mobility of electrons is much faster than that of holes, resulting in a decrease in the recombination luminescence efficiency of electrons and holes, thus making The luminous efficiency of the LED decreases.

Contents of the invention

In order to solve the problem in the prior art that the electron blocking layer is designed to be relatively thick, which reduces the luminous efficiency of the LED, an embodiment of the present invention provides a light emitting diode epitaxial wafer and a manufacturing method thereof. Described technical scheme is as follows:

In one aspect, the present invention provides a light-emitting diode epitaxial wafer, the light-emitting diode epitaxial wafer includes a substrate, and a buffer layer, an undoped GaN layer, an N-type layer, an active layer, a low-temperature P-type layer, an electron blocking layer, a high-temperature P-type layer and a P-type contact layer, the low-temperature P-type layer is a GaN layer,

The electron blocking layer is an Al _x Ga _1-x N/AlN/GaN/In _y Ga _1-y N superlattice structure including N periods, 0.05<x<0.15, 0.2<y<0.4, and N is greater than It is a positive integer equal to 2, and the thickness of the electron blocking layer is 10-25 nm.

Further, the thickness of each AlxGa1 _{- xN} sublayer in the AlxGa1 _{- xN} /AlN/GaN/InyGa1 _{-yN superlattice} structure is 0.5-1.5nm.

Further, the thickness of each AlN sublayer in the Al _x Ga _1-x N/AlN/GaN/In _y Ga _1-y N superlattice structure is 0.5-1.5 nm.

Further, the thickness of each GaN sublayer in the Al _x Ga _1-x N/AlN/GaN/In _y Ga _1-y N superlattice structure is 1-2 nm.

Further, the thickness of each In _y Ga _1-y N sublayer in the Al _x Ga _1-x N/AlN/GaN/In _y Ga _1-y N superlattice structure is 1-2 nm.

Further, 2≤N≤5.

Further, x=0.1, y=0.38.

On the other hand, an embodiment of the present invention provides a method for manufacturing a light-emitting diode epitaxial wafer, the manufacturing method comprising:

providing a substrate;

sequentially growing a buffer layer, an undoped GaN layer, an N-type layer, an active layer, and a low-temperature P-type layer on the substrate, the low-temperature P-type layer being a GaN layer;

An electron blocking layer is grown on the low-temperature P-type layer, and the electron blocking layer is an _{AlxGa1 - xN} /AlN/GaN/InyGa1 _{-yN superlattice} structure including N periods, 0.05<x<0.15,0.2<y<0.4, N is a positive integer greater than or equal to 2, and the thickness of the electron blocking layer is 10-25nm;

A high-temperature P-type layer and a P-type contact layer are grown on the electron blocking layer.

Further, the growth temperature of the electron blocking layer is 850-1080°C.

Further, the growth pressure of the electron blocking layer is 200-500 Torr.

The beneficial effects brought by the technical solution provided by the embodiments of the present invention are:

The electron blocking layer is set to include N periods of Al _x Ga _1-x N/AlN/GaN/In _y Ga _1-y N superlattice structure, wherein, because the low-temperature P-type layer is a GaN layer, and the electron blocking layer The AlN layer and the low-temperature P-type GaN layer have a lattice mismatch, so setting Al _x Ga _1-x N as a buffer layer can reduce the lattice mismatch between the electron blocking layer and the low-temperature P-type layer. The AlN layer can form a higher barrier energy level to block the migration of electrons. At the same time, due to the large interface lattice mismatch between the AlN layer and the GaN layer, certain two-dimensional electrons can be generated between the AlN layer and the GaN layer. gas to provide more holes and increase the mobility of carriers. The In _y Ga _1-y N layer can enhance the generation of two-dimensional electron gas, further provide more holes, and increase the mobility of carriers. And the thickness of the electron blocking layer in the present invention is 10-25nm, compared with the existing electron blocking layer with a thickness greater than 50nm, the thickness is greatly reduced, thereby reducing the polarization and stress between materials, reducing the high Al The electronic blocking layer of the component produces a valence band band level at the valence band heterojunction interface, so that holes can be better injected into the active layer, and the concentration of holes increases, and more holes can be in the active layer Combined with electrons to emit light, the luminous efficiency of LED is improved.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained based on these drawings without creative effort.

FIG. 1 is a schematic structural view of a light-emitting diode epitaxial wafer provided by an embodiment of the present invention;

Fig. 2 is a method flowchart of a method for manufacturing a light emitting diode epitaxial wafer provided by an embodiment of the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below in conjunction with the accompanying drawings.

An embodiment of the present invention provides a light-emitting diode epitaxial wafer. FIG. 1 is a schematic structural view of a light-emitting diode epitaxial wafer provided by an embodiment of the present invention. As shown in FIG. 1, the light-emitting diode epitaxial wafer includes a substrate 1, and sequentially stacked Buffer layer 2, undoped GaN layer 3, N-type layer 4, active layer 5, low-temperature P-type layer 6, electron blocking layer 7, high-temperature P-type layer 8 and P-type contact layer 9 on substrate 1 , the low-temperature P-type layer 6 is a GaN layer.

Wherein, the electron blocking layer 7 is an AlxGa1 _{- xN} /AlN/GaN/InyGa1 _{-yN superlattice} structure including N periods, 0.05<x<0.15, 0.2<y<0.4, and N is A positive integer greater than or equal to 2, and the thickness of the electron blocking layer 7 is 10-25 nm.

By setting the electron blocking layer as an Al _x Ga _1-x N/AlN/GaN/In _y Ga _1-y N superlattice structure including N periods, wherein, since the low-temperature P-type layer is a GaN layer, the electron blocking The AlN layer in the layer has a lattice mismatch with the low-temperature P-type GaN layer, so setting AlxGa1 _{- xN} as a buffer layer can reduce the lattice mismatch between the electron blocking layer and the low-temperature P-type layer. The AlN layer can form a higher barrier energy level to block the migration of electrons. At the same time, due to the large interface lattice mismatch between the AlN layer and the GaN layer, certain two-dimensional electrons can be generated between the AlN layer and the GaN layer. gas to provide more holes and increase the mobility of carriers. The In _y Ga _1-y N layer can enhance the generation of two-dimensional electron gas, further provide more holes, and increase the mobility of carriers. And the thickness of the electron blocking layer in the present invention is 10-25nm, compared with the existing electron blocking layer with a thickness greater than 50nm, the thickness is greatly reduced, thereby reducing the polarization and stress between materials, reducing the high Al The electronic blocking layer of the component produces a valence band band level at the valence band heterojunction interface, so that holes can be better injected into the active layer, and the concentration of holes increases, and more holes can be in the active layer Combined with electrons to emit light, the luminous efficiency of LED is improved.

Preferably, x=0.1, y=0.38. At this time, the luminous efficiency of the LED is the best.

Specifically, each AlxGa1 _{- xN} /AlN/GaN/InyGa1 _{-yN superlattice} structure of the electron blocking layer 7 includes AlxGa1 _{-xN sublayers} 71, AlN sublayers layer 72 , GaN sublayer 73 and In _y Ga _1-y N sublayer 74 .

Further, the thickness of each Al _x Ga _1-x N sublayer 71 is 0.5-1.5 nm. If the thickness of each AlxGa1 _{-xN sublayer} 71 is less than 0.5nm, it will not be effective in reducing the lattice mismatch between the electron blocking layer 7 and the low-temperature P-type layer 6. If each _AlxGa1 - _xN sublayer 71 If the thickness of the _x N sublayer 71 is greater than 1.5 nm, it will cause waste, and also cause the thickness of the electron blocking layer 7 to be too thick, which will affect the luminous efficiency of the LED.

Preferably, the thickness of each AlxGa1 _{-xN sublayer} 71 is 1 nm. At this time, it can not only reduce the lattice mismatch between the electron blocking layer 7 and the low-temperature P-type layer 6 , but also ensure that the thickness of the electron blocking layer 7 will not be too thick, resulting in waste.

Further, the thickness of each AlN sub-layer 72 is 0.5-1.5 nm. If the thickness of each AlN sublayer 72 is less than 0.5 nm, it will not be able to block electrons. If the thickness of each AlN sub-layer 72 is greater than 1.5 nm, it will cause waste, and also cause the thickness of the electron blocking layer 7 to be too thick, which will affect the luminous efficiency of the LED.

Preferably, each AlN sublayer 72 has a thickness of 1 nm. At this time, it can not only block electrons, but also ensure that the thickness of the electron blocking layer 7 will not be too thick, resulting in waste.

Further, the thickness of each GaN sub-layer 73 is 1-2 nm. If the thickness of each GaN sublayer 73 is less than 1nm, a certain two-dimensional electron gas cannot be generated to provide more holes and increase the mobility of carriers. If the thickness of each GaN sublayer 73 is greater than 2nm, It will cause waste, and also cause the thickness of the electron blocking layer 7 to be too thick, which will affect the luminous efficiency of the LED.

Preferably, the thickness of each GaN sub-layer 73 is 1 nm. At this time, a certain two-dimensional electron gas can be generated with the AlN sublayer 72 to provide more holes and increase the mobility of carriers, and it can also ensure that the thickness of the electron blocking layer 7 will not be too thick, resulting in waste.

Further, the thickness of each In _y Ga _1-y N sublayer 74 is 1-2 nm. If the thickness of each In _y Ga _1-y N sub-layer 74 is less than 1 nm, the generation of two-dimensional electron gas cannot be enhanced, and if the thickness of each In _y Ga _1-y N sub-layer 74 is greater than 2 nm, it will cause waste , will also cause the thickness of the electron blocking layer 7 to be too thick, which will affect the luminous efficiency of the LED.

Preferably, the thickness of each In _y Ga _1-y N sublayer 74 is 2 nm. At this time, it can not only help to generate more two-dimensional electron gas between the AlN sublayer 72 and the GaN sublayer 73, further provide more holes, improve the mobility of carriers, but also ensure the thickness of the electron blocking layer 7 It will not be too thick and cause waste.

Among them, 2≤N≤5. If N is less than 2, the thickness of the electron blocking layer 7 will be too thin, which cannot block electrons, increase holes, and increase the mobility of carriers. If N is greater than 5, the thickness of the electron blocking layer 7 will be too thick, reducing the luminous efficiency of the LED.

Optionally, the substrate 1 may be a sapphire substrate with a (0001) crystal orientation.

Optionally, the buffer layer 2 may be a GaN layer with a thickness of 15-35 nm.

Optionally, the thickness of the undoped GaN layer 3 may be 1-5 um.

Optionally, the N-type layer 4 may be a Si-doped GaN layer, wherein the doping concentration of Si ranges from 10 ¹⁸ cm ⁻³ to 10 ¹⁹ cm ⁻³ ; the thickness of the N-type layer 4 may be 1-5 um.

Optionally, the active layer 5 may be composed of 5-11 periods of In _x Ga _1-x N well layer 51 and GaN barrier layer 52 superlattice structure, wherein each layer of In _x Ga _1-x N well layer The thickness of 51 may be 2-3 nm, and the thickness of each GaN barrier layer 52 may be 9-20 nm.

Optionally, the high-temperature P-type layer 8 may be a GaN layer with a thickness of 20-50 nm.

Optionally, the P-type contact layer 9 may be a GaN layer with a thickness of 5-300 nm.

Embodiment two

An embodiment of the present invention provides a method for manufacturing a light-emitting diode epitaxial wafer, which is used to manufacture the light-emitting diode epitaxial wafer provided in Embodiment 1. FIG. 2 is a process flow of a method for manufacturing a light-emitting diode epitaxial wafer provided by an embodiment of the present invention. Figure, as shown in Figure 2, the manufacturing method comprises:

Step 201, providing a substrate.

Optionally, the substrate is an Al ₂ O ₃ sapphire substrate with a (0001) crystal orientation.

Specifically, this step 201 includes:

Under the hydrogen atmosphere, the substrate was treated at high temperature for 8 minutes. Wherein, the temperature of the reaction chamber is 1000-1200° C., and the pressure of the reaction chamber is controlled at 200-500 torr.

Step 202, growing a buffer layer on the substrate.

Specifically, the buffer layer is a GaN layer with a thickness of 15-35 nm. The temperature of the reaction chamber is 400-600° C., and the pressure of the reaction chamber is controlled at 400-600 torr.

Further, step 202 also includes:

The pressure of the reaction chamber is controlled to be constant, the temperature is raised to 1000° C. to 1200° C., and the buffer is annealed in situ for 5 to 10 minutes.

Step 203 , growing an undoped GaN layer on the buffer layer.

In this embodiment, the thickness of the undoped GaN layer is 1-5 um. When growing the undoped GaN layer, the temperature of the reaction chamber is 1000-1100° C., and the pressure of the reaction chamber is controlled at 100-500 torr.

Step 204 , growing an N-type layer on the undoped GaN layer.

In this embodiment, the N-type layer is a GaN layer doped with Si, the Si doping concentration is between 10 ¹⁸ cm ⁻³ and 10 ¹⁹ cm ⁻³ , and the thickness is 1˜5 μm. When growing the N-type layer, the temperature of the reaction chamber is 1000-1200° C., and the pressure of the reaction chamber is controlled at 100-500 torr.

Step 205 , growing an active layer on the N-type layer.

The active layer may be a superlattice structure including 5-11 periods of In _x Ga _1-x N well layers and GaN barrier layers, 0≤x≤1. Wherein, the thickness of each In _x Ga _1-x N well layer is 2-3 nm, and the thickness of each GaN barrier layer is 9-20 nm.

Specifically, when growing the active layer, the pressure in the reaction chamber is controlled at 100-500 torr. When growing the In _x Ga _1-x N well layer, the temperature of the reaction chamber is 720-829°C. When growing the GaN barrier layer, the temperature of the reaction chamber is 850-959°C.

Step 206 , growing a low-temperature P-type layer on the active layer.

In this embodiment, the low-temperature P-type layer is a GaN layer with a thickness of 20-100 nm. When growing a high-temperature P-type layer, the temperature of the reaction chamber is 700-900° C., and the pressure of the reaction chamber is controlled at 100-300 torr.

Step 207 , growing an electron blocking layer on the low-temperature P-type layer.

Specifically, the electron blocking layer is an Al _x Ga _1-x N/AlN/GaN/In _y Ga _1-y N superlattice structure including N periods, 0.05<x<0.15, 0.2<y<0.4, and N is A positive integer greater than or equal to 2.

Preferably, x=0.1, y=0.38. At this time, the luminous efficiency of the LED is the best.

Further, the thickness of each _{AlxGa1 - xN} sublayer in the AlxGa1 _- xN/AlN/GaN/InyGa1 _{-yN superlattice} structure is 0.5-1.5nm. If the thickness of each Al _x Ga _1-x N sublayer is less than 0.5nm, it will not be effective in reducing the lattice mismatch between the electron blocking layer and the low-temperature P-type layer. If each Al _x Ga _1-x N sublayer If the thickness of the layer is greater than 1.5nm, it will cause waste, and also cause the thickness of the electron blocking layer to be too thick, which will affect the luminous efficiency of the LED.

Further, the thickness of each AlN sublayer in the AlxGa1 _{- xN} /AlN/GaN/InyGa1 _{-yN superlattice} structure is 0.5-1.5nm. If the thickness of each AlN sub-layer is less than 0.5nm, it will not play the role of blocking electrons. If the thickness of each AlN sub-layer is greater than 1.5 nm, it will cause waste, and also cause the thickness of the electron blocking layer to be too thick, which will affect the luminous efficiency of the LED.

Further, the thickness of each GaN sublayer in the Al _x Ga _1-x N/AlN/GaN/In _y Ga _1-y N superlattice structure is 1-2 nm. If the thickness of each GaN sublayer is less than 1nm, a certain two-dimensional electron gas cannot be generated to provide more holes and increase the mobility of carriers. If the thickness of each GaN sublayer is greater than 2nm, it will It causes waste, and also causes the thickness of the electron blocking layer to be too thick, which affects the luminous efficiency of the LED.

Further, the thickness of each In _y Ga _1-y N sublayer in the Al _x Ga _1-x N/AlN/GaN/In _y Ga _1-y N superlattice structure is 1-2 nm. If the thickness of each In _y Ga _1-y N sublayer is less than 1 nm, the generation of two-dimensional electron gas cannot be enhanced, and if the thickness of each In _y Ga _1-y N sublayer is greater than 2 nm, it will cause waste, and also It will cause the thickness of the electron blocking layer to be too thick, which will affect the luminous efficiency of the LED.

Among them, 2≤N≤5. If N is less than 2, the thickness of the electron blocking layer will be too thin, which cannot block electrons, increase holes, and increase the mobility of carriers. If N is greater than 5, the thickness of the electron blocking layer will be too thick, reducing the luminous efficiency of the LED.

In this embodiment, each AlxGa1 _{- xN} sublayer has a thickness of 1nm, each AlN sublayer has a thickness of 1nm, each GaN sublayer has a thickness of 1nm, and each InyGa1 _{- y} The thickness of the N sublayer is 2nm, 2≤N≤5, and the thickness of the electron blocking layer 6 is 10-25nm.

Step 208 , growing a high-temperature P-type layer on the electron blocking layer.

In this embodiment, the high-temperature P-type layer is a GaN layer with a thickness of 20-50 nm. When growing a high-temperature P-type layer, the temperature of the reaction chamber is 850-1080° C., and the pressure of the reaction chamber is controlled at 100-300 torr.

Step 209 , growing a P-type contact layer on the high-temperature P-type layer.

In this embodiment, the P-type contact layer is a GaN layer with a thickness of 5-300 nm. When growing the P-type layer, the temperature of the reaction chamber is 850-1050° C., and the pressure of the reaction chamber is controlled at 100-300 torr.

After the growth of the epitaxial wafer is completed, the temperature of the reaction chamber is lowered to 650° C. to 850° C., and the epitaxial wafer is annealed in a nitrogen atmosphere for 5 to 15 minutes, and then lowered to room temperature, and the epitaxial growth ends.

After the growth of the above-mentioned light-emitting diode epitaxial wafer is completed, the temperature of the reaction chamber is lowered to 600-900 ° C, annealing is performed in a PN ₂ atmosphere for 10-30 minutes, and then gradually lowered to room temperature, and then, after cleaning, deposition, photolithography and A single 9*27mil chip is made by the subsequent etching process.

After testing, it is found that the light intensity of the LED chip made by using the prior art is 104mW under the driving current of 20mA, and the light intensity of the LED chip made by the manufacturing method provided by the embodiment of the present invention is 104mW under the driving current of 20mA. 106mW, the luminous efficiency has increased by about 2%.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection of the present invention. within range.

Claims (10)

1. a kind of LED epitaxial slice, the LED epitaxial slice includes substrate, and is sequentially laminated on the lining Buffer layer, undoped GaN layer, N-type layer, active layer, low temperature P-type layer, electronic barrier layer, high temperature P-type layer and p-type on bottom connect Contact layer, the low temperature P-type layer are GaN layer, which is characterized in that

The electronic barrier layer is the Al for including N number of period_xGa_1-xN/AlN/GaN/In_yGa_1-yN superlattice structure, 0.05<x< 0.15,0.2<y<0.4, N is positive integer more than or equal to 2, the electronic barrier layer with a thickness of 10~25nm.

2. LED epitaxial slice according to claim 1, which is characterized in that in the Al_xGa_1-xN/AlN/GaN/ In_yGa_1-yEach Al in N superlattice structure_xGa_1-xN sublayer with a thickness of 0.5~1.5nm.

3. LED epitaxial slice according to claim 1 or 2, which is characterized in that in the Al_xGa_1-xN/AlN/ GaN/In_yGa_1-yEach AlN sublayer with a thickness of 0.5~1.5nm in N superlattice structure.

4. LED epitaxial slice according to claim 1 or 2, which is characterized in that in the Al_xGa_1-xN/AlN/ GaN/In_yGa_1-yEach GaN sublayer with a thickness of 1~2nm in N superlattice structure.

5. LED epitaxial slice according to claim 1 or 2, which is characterized in that in the Al_xGa_1-xN/AlN/ GaN/In_yGa_1-yEach In in N superlattice structure_yGa_1-yN sublayer with a thickness of 1~2nm.

6. LED epitaxial slice according to claim 1 or 2, which is characterized in that 2≤N≤5.

7. LED epitaxial slice according to claim 1 or 2, which is characterized in that x=0.1, y=0.38.

8. a kind of manufacturing method of LED epitaxial slice, which is characterized in that the manufacturing method includes：

One substrate is provided；

Successively grown buffer layer, undoped GaN layer, N-type layer, active layer and low temperature P-type layer over the substrate, the low temperature P-type layer is GaN layer；

Electronic barrier layer is grown in the low temperature P-type layer, the electronic barrier layer is the Al for including N number of period_xGa_1-xN/AlN/ GaN/In_yGa_1-yN superlattice structure, 0.05<x<0.15,0.2<y<0.4, N is the positive integer more than or equal to 2, the electronics resistance Barrier with a thickness of 10~25nm；

High temperature P-type layer and p-type contact layer are grown on the electronic barrier layer.

9. manufacturing method according to claim 8, which is characterized in that the growth temperature of the electronic barrier layer be 850~ 1080℃。

10. manufacturing method according to claim 8 or claim 9, which is characterized in that the growth pressure of the electronic barrier layer is 200~500Torr.