CN108535951B - Mask and metal wiring of semiconductor device formed using the same - Google Patents

Abstract

A mask and a metal wiring of a semiconductor device are provided. The mask includes: a mask substrate including a unit exposure region configured to expose the metal layer in the unit region of the semiconductor device and a peripheral exposure region configured to expose the metal layer in the peripheral region of the semiconductor device, the first mask pattern configured to expose the metal layer in the peripheral exposure region of the mask substrate to form a signal metal pattern, the second mask pattern configured to expose the metal layer in the peripheral exposure region of the mask substrate to form a dummy metal pattern, the second mask pattern being adjacent to the first mask pattern, the second mask pattern having a width substantially the same as a width of the first mask pattern.

Description

Mask and metal wiring of semiconductor device formed using the same

Technical Field

Example embodiments relate to a mask and/or a metal wiring of a semiconductor device formed using the mask. More particularly, example embodiments relate to a mask for forming metal wirings in a peripheral region of a semiconductor device, and/or a metal wiring of a semiconductor device formed using the mask.

Background

In general, a metal wiring of a semiconductor device may be formed through an exposure process using a mask. The metal wiring may be arranged in a cell region and a peripheral region of the semiconductor device. The pitch between the metal wirings in the peripheral region may be wider than the pitch between the metal wirings in the cell region. In addition, the metal wiring in the cell region may have a uniform pitch. Instead, the metal wiring in the peripheral region may have various pitches. As the pitch between metal wirings of a semiconductor device becomes narrower, an off-axis illumination (off-axis illumination) exposure process has been used to form metal wirings with a narrow pitch.

According to the prior art, off-axis illumination may have a focus corresponding to the pitch between metal wires in the cell area. Conversely, the focus of the off-axis illumination may not correspond to the pitch (or pitches) between the metal wires in the peripheral region. Thus, metal wiring formed in the peripheral region using off-axis illumination may not have a desired shape or pattern. For example, the metal wiring in the peripheral region may have a size larger than the design size, so as to be connected to the adjacent metal wiring. In contrast, the metal wiring in the peripheral region may have a smaller size than the design size, resulting in the metal wiring being cut off.

Disclosure of Invention

Some example embodiments provide a mask capable of precisely forming a metal wiring having a design size in a peripheral region.

Some example embodiments also provide metal wiring of a semiconductor device using the above mask.

According to an example embodiment, a mask includes: a mask substrate including a unit exposure region configured to expose the metal layer in the unit region of the semiconductor device and a peripheral exposure region configured to expose the metal layer in the peripheral region of the semiconductor device, the first mask pattern configured to expose the metal layer in the peripheral exposure region of the mask substrate to form a signal metal pattern, the second mask pattern configured to expose the metal layer in the peripheral exposure region of the mask substrate to form a dummy metal pattern, the second mask pattern being adjacent to the first mask pattern, the second mask pattern having a width substantially the same as a width of the first mask pattern.

In some example embodiments, the second mask pattern may have a center line that coincides with a center line of the first mask pattern along a straight line.

In some example embodiments, the mask may include a first mask pattern group, the first mask pattern group may include a plurality of first mask patterns arranged on a straight line, the second mask pattern may be located between the plurality of first mask patterns along the straight line, and a distance between the second mask pattern and one of the plurality of first mask patterns may be substantially the same as a distance between the second mask pattern and another of the plurality of first mask patterns.

In some example embodiments, the center lines of the plurality of first mask patterns and the center lines of the second mask patterns may coincide with each other along the straight line.

In some example embodiments, the mask may include a first mask pattern group, the first mask pattern group may include a plurality of first mask patterns parallel to each other, the second mask pattern may be parallel to and between the plurality of first mask patterns, and a distance between the second mask pattern and one of the plurality of first mask patterns may be substantially the same as a distance between the second mask pattern and another of the plurality of first mask patterns.

In some example embodiments, a distance between the second mask pattern and the one of the plurality of first mask patterns may be substantially the same as a distance between adjacent mask patterns in the unit exposure field.

In some example embodiments, the plurality of first mask patterns may have different widths, and the second mask pattern may have substantially the same width as a shortest width among the plurality of first mask patterns.

In some example embodiments, the mask may include a second mask pattern group, and the second mask pattern group may include a plurality of second mask patterns, each of which may be located between two adjacent first mask patterns of the plurality of first mask patterns, the plurality of second mask patterns may be parallel to each other, and a distance between the plurality of second mask patterns may be substantially the same as a distance between the second mask pattern and the first mask pattern adjacent to the second mask pattern.

According to an example embodiment, a metal wiring of a semiconductor device includes: a signal metal pattern located in a peripheral region of the semiconductor substrate; and a dummy metal pattern located in the peripheral region, the dummy metal pattern being adjacent to the signal metal pattern, the dummy metal pattern having a width substantially the same as a width of the signal metal pattern.

In some example embodiments, the dummy metal pattern may have a center line that coincides with a center line of the signal metal pattern along a straight line.

In some example embodiments, the metal wiring may include a signal metal pattern group, the signal metal pattern group may include a plurality of signal metal patterns arranged on a straight line, the dummy metal pattern may be located between the plurality of signal metal patterns along the straight line, and a distance between the dummy metal pattern and one of the plurality of signal metal patterns may be substantially the same as a distance between the dummy metal pattern and another of the plurality of signal metal patterns.

In some example embodiments, the center lines of the plurality of signal metal patterns and the center lines of the dummy metal patterns may coincide with each other along a straight line.

In some example embodiments, the metal wiring may include a signal metal pattern group, the signal metal pattern group may include a plurality of signal metal patterns parallel to each other, the dummy metal pattern may be parallel to and located between the plurality of signal metal patterns, and a distance between the dummy metal pattern and one of the plurality of signal metal patterns may be substantially the same as a distance between the dummy metal pattern and another of the plurality of signal metal patterns.

In some example embodiments, the plurality of signal metal patterns may have different widths, and the dummy metal pattern may have substantially the same width as a shortest width among the plurality of signal metal patterns.

In some example embodiments, the metal wiring may include a dummy metal pattern group, and the dummy metal pattern group may include a plurality of dummy metal patterns disposed between the plurality of signal metal patterns, and a distance between the plurality of dummy metal patterns may be substantially the same as a distance between the dummy metal patterns and signal metal patterns adjacent to the dummy metal patterns.

According to an example embodiment, a metal wiring of a semiconductor device includes: at least one signal metal pattern located in a peripheral region of the semiconductor substrate, the at least one signal metal pattern being electrically connected to a circuit of the semiconductor substrate; at least one dummy metal pattern located in the peripheral region and filling a region not occupied by the at least one signal metal pattern, the at least one dummy metal pattern being electrically insulated from a circuit of the semiconductor substrate, the at least one dummy metal pattern having a width substantially the same as a width of the at least one signal metal pattern, a distance between adjacent two of the at least one dummy metal pattern and the at least one signal metal pattern being substantially the same as a distance between unit metal patterns in the unit region.

In some example embodiments, the at least one signal metal pattern may be parallel to the at least one dummy metal pattern.

In some example embodiments, the at least one signal metal pattern may include a first signal metal pattern and a second signal metal pattern, and the at least one dummy metal pattern may be located between the first signal metal pattern and the second signal metal pattern such that a center line of the first signal metal pattern and the second signal metal pattern and a center line of the at least one dummy metal pattern form a straight line.

In some example embodiments, a first distance between the first signal metal pattern and the at least one dummy metal pattern may be substantially the same as a second distance between the second signal metal pattern and the at least one dummy metal pattern.

In some example embodiments, the at least one signal metal pattern may include a plurality of signal metal patterns having different widths, and the at least one dummy metal pattern may have a width substantially the same as a shortest width of the plurality of signal metal patterns.

According to example embodiments, the second mask pattern for forming the dummy metal pattern in the peripheral region of the semiconductor substrate may be disposed between the first mask patterns for forming the signal metal pattern in the peripheral region of the semiconductor substrate. The width of the second mask pattern may be substantially the same as the width of the first mask pattern. Accordingly, the metal wiring formed in the peripheral region using the mask may have a minute and uniform pitch corresponding to the pitch of the metal wiring in the cell region. As a result, the metal wirings formed in the peripheral region by using the mask and the off-axis illumination may have a shape and size designed such that a short circuit between the metal wirings and/or a cutting-off of the metal wirings may be suppressed or prevented.

Drawings

Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. Fig. 1-15 represent non-limiting example embodiments as described herein.

FIG. 1 is a plan view illustrating a mask according to an example embodiment;

FIG. 2 is an enlarged plan view of portion "II" in FIG. 1;

FIG. 3 is an enlarged plan view of portion "III" in FIG. 1;

FIG. 4 is an enlarged plan view of portion "IV" in FIG. 1;

FIG. 5 is an enlarged plan view of portion "V" in FIG. 1;

FIG. 6 is an enlarged plan view of portion "VI" of FIG. 1;

fig. 7 to 9 are cross-sectional views illustrating a method of forming a metal wiring of a semiconductor device using the mask of fig. 1 according to an example embodiment;

fig. 10 is a plan view showing a metal wiring of the semiconductor device using the mask in fig. 1;

FIG. 11 is an enlarged plan view of portion "XI" in FIG. 10;

fig. 12 is an enlarged plan view of a portion "XII" in fig. 10;

FIG. 13 is an enlarged plan view of portion "XIII" in FIG. 10;

FIG. 14 is an enlarged plan view of portion "XIV" in FIG. 10;

fig. 15 is an enlarged plan view of a portion "XV" in fig. 10.

Detailed Description

Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments are shown. The inventive concept may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. These example embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the inventive concept to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity.

It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. Like numbers refer to like elements throughout. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present inventive concept.

Spatially relative terms, such as "under … …," "under … …," "below," "over … …," "above," and the like, may be used herein for ease of explanation to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "under" or "beneath" other elements or features would then be oriented "over" the other elements or features. Thus, the exemplary term "below … …" may encompass both an orientation of above and below. The device may be otherwise positioned (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concepts. As used herein, the singular forms "a", "an", "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Example embodiments are described herein with reference to cross-sectional views, which are schematic illustrations of idealized example embodiments (and intermediate structures). As such, variations from the illustrated shapes, such as those caused by manufacturing techniques and/or tolerances, are expected to occur. Thus, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or gradients of implant concentration at its edges rather than a binary change from implanted to non-implanted regions. Likewise, a buried region formed by implantation may result in some implantation occurring in the region between the buried region and the surface through which implantation occurs. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the inventive concept.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which these inventive concepts belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Hereinafter, example embodiments will be explained in detail with reference to the accompanying drawings.

Mask for mask

Fig. 1 is a plan view showing a mask according to an exemplary embodiment, fig. 2 is an enlarged plan view of a portion "II" in fig. 1, fig. 3 is an enlarged plan view of a portion "III" in fig. 1, fig. 4 is an enlarged plan view of a portion "IV" in fig. 1, fig. 5 is an enlarged plan view of a portion "V" in fig. 1, and fig. 6 is an enlarged plan view of a portion "VI" in fig. 1.

Referring to fig. 1, the mask 100 of this example embodiment includes a mask substrate 110, a unit mask pattern 120, first mask patterns 130, 132, 133, 134, 135, and 136 (e.g., first mask pattern 130, second first mask pattern 132, third first mask pattern 133, fourth first mask pattern 134, fifth first mask pattern 135, and sixth first mask pattern 136) and second mask patterns 140, 142, 144, 146, 147, and 148 (e.g., first second mask pattern 140, second mask pattern 142, third second mask pattern 144, fourth second mask pattern 146, fifth second mask pattern 147, and sixth second mask pattern 148).

The mask substrate 110 may have a cell exposure region CER and a peripheral exposure region PER. The cell mask pattern 120 may be formed in the cell exposure region CER. The unit mask pattern 120 in the unit exposure region CER may be used to expose the metal layer in the unit region of the semiconductor device to form a main metal pattern. The first mask patterns 130, 132, 133, 134, 135 and 136 and the second mask patterns 140, 142, 144, 146, 147 and 148 may be formed in the peripheral exposure region PER. The first mask patterns 130, 132, 133, 134, 135 and 136 in the peripheral exposure region PER may be used to expose the metal layer in the peripheral region of the semiconductor device to form a signal metal pattern. The second mask patterns 140, 142, 144, 146, 147 and 148 in the peripheral exposure region PER may be used to expose the metal layer in the peripheral region to form a dummy metal pattern.

The unit mask pattern 120 may include an opening through which light may pass. The unit mask pattern 120 may have an elongated bar shape. The unit mask patterns 120 may be disposed apart from each other at substantially the same pitch. Accordingly, the pitches between the unit mask patterns 120 may be substantially the same as each other.

The first mask patterns 130, 132, 133, 134, 135 and 136 may include openings through which light may pass. The first mask patterns 130, 132, 133, 134, 135 and 136 may have an elongated bar shape. The first mask patterns 130, 132, 133, 134, 135 and 136 may have a first width OW1 or a third width OW3. The first width OW1 of the first mask patterns 130, 132, 133, 134, 135 and 136 may be substantially the same as the width of the unit mask pattern 120. According to some example embodiments, the first width OW1 of the first mask patterns 130, 132, 133, 134, 135, and 136 may be different from the width of the unit mask pattern 120.

As described above, the pitch between the unit mask patterns 120 in the unit exposure region CER may be uniform. In contrast, the pitch between the first mask patterns 130, 132, 133, 134, 135, and 136 in the peripheral exposure region PER may be non-uniform. That is, pitches between the first mask patterns 130, 132, 133, 134, 135, and 136 in the peripheral exposure region PER may be different from each other. In addition, the first mask patterns 130, 132, 133, 134, 135 and 136 may have different lengths. As a result, there may be portions in the peripheral exposure region PER of the mask substrate 110 where the first mask patterns 130, 132, 133, 134, 135 and 136 are not disposed.

Here, light incident to the mask 100 from off-axis illumination may be configured to form a focus corresponding to a fine pitch between main metal patterns to be formed in a cell region of the semiconductor device using the cell mask pattern 120. However, the focus of light does not correspond to a pitch between signal metal patterns to be formed in a peripheral region of the semiconductor device using the first mask patterns 130, 132, 133, 134, 135 and 136. Therefore, the signal metal pattern in the peripheral region is not formed to have a designed shape or a desired pattern.

The second mask pattern 140 may be formed in a portion of the peripheral exposure region PER of the mask substrate 110 where the first mask pattern 130 is not disposed. The second mask pattern 140 may correspond to a pitch between a focus of light emitted from the off-axis illumination and the signal metal pattern.

The second mask patterns 140, 142, 144, 146, 147, and 148 may include openings through which light may pass. The second mask patterns 140, 142, 144, 146, 147, and 148 may be disposed adjacent to the first mask patterns 130, 132, 133, 134, 135, and 136. The second mask pattern 140 may have a second width OW2 substantially the same as the first width OW1 of the first mask pattern 130. Accordingly, the signal metal pattern formed through the first mask pattern 130 may have substantially the same width as the dummy metal pattern formed through the second mask pattern 140. The dummy metal patterns between the signal metal patterns may provide the metal wiring in the peripheral region of the semiconductor device with a pitch substantially the same as a pitch between the main metal patterns in the cell region of the semiconductor device.

Referring to fig. 2, the second mask pattern 140 may be disposed adjacent to the first mask pattern 132 having a relatively short length. The first mask pattern 132 and the second mask pattern 140 may be located on a straight line. Because the first width OW1 of the first mask pattern 132 may be substantially the same as the second width OW2 of the second mask pattern 140, the first mask pattern 132 and the second mask pattern 140 may have the same center line CL along the straight line. The second mask pattern 140 may be separated from the first mask pattern 132 by a gap OG. The gap OG may be a distance between adjacent side surfaces of the first and second mask patterns 132 and 140.

Referring to fig. 3, the second mask pattern 142 having a relatively short length may be disposed between the two first mask patterns 134 and 135 located on a straight line and each having a relatively short length. The second mask pattern 142 may be located on the straight line. Accordingly, the first mask patterns 134 and 135 and the second mask pattern 142 may have a common center line CL along the straight line.

In addition, a gap between the second mask pattern 142 and the first mask pattern 134 may be substantially the same as a gap between the second mask pattern 142 and the first mask pattern 135. For example, the first gap OG1 between adjacent side surfaces of the second mask pattern 142 and the first mask pattern 134 may be substantially the same as the second gap OG2 between adjacent side surfaces of the second mask pattern 142 and the first mask pattern 135. The first and second gaps OG1 and OG2 may be substantially the same as the gaps OG between the first and second mask patterns 132 and 140 in fig. 2. The gap OG, the first gap OG1, and the second gap OG2 may be determined according to design rules of metal wirings in the semiconductor device.

Referring to fig. 4, two first mask patterns 130 in the peripheral exposure region PER may be parallel to each other. The first mask pattern 130 may have a first width OW1. In fig. 4, the upper first mask pattern 130 may have a first center line CL1. The lower first mask pattern 130 may have a second center line CL2. The pitch between the first mask patterns 130 in the peripheral exposure region PER may be wider than the pitch between the unit mask patterns 120 in the unit exposure region CER.

The second mask pattern 144 may be disposed between the first mask patterns 130. The second mask pattern 144 may have a length substantially the same as that of the first mask pattern 130. The second mask pattern 144 may have a second width OW2 substantially the same as the first width OW1 of the first mask pattern 130. The second mask pattern 144 may be substantially parallel to the first mask pattern 130. Accordingly, the second mask pattern 144 may have a third center line CL3 substantially parallel to the first and second center lines CL1 and CL2 of the first mask pattern 130.

The first mask pattern 130 and the second mask pattern 140 may be arranged at substantially the same pitch. For example, the first pitch OP1 between the second mask pattern 144 and the upper first mask pattern 130 may be substantially the same as the second pitch OP2 between the second mask pattern 144 and the lower first mask pattern 130. That is, the distance between the upper surface of the second mask pattern 144 and the lower surface of the upper first mask pattern 130 may be substantially the same as the distance between the lower surface of the second mask pattern 144 and the upper surface of the lower first mask pattern 130.

Referring to fig. 5, the first mask pattern 130 and the first mask pattern 136 in the peripheral exposure region PER may be parallel to each other. In fig. 5, the upper first mask pattern 130 may have a first width OW1, and the lower first mask pattern 136 may have a third width OW3 wider than the first width OW 1. The upper first mask pattern 130 may have a first center line CL1. The lower first mask pattern 136 may have a second center line CL2. The pitch between the first mask patterns 130 and 136 in the peripheral exposure region PER may be wider than the pitch between the unit mask patterns 120 in the unit exposure region CER.

The second mask pattern 146 may be disposed between the first mask patterns 130 and 136. The second mask pattern 146 may have a length substantially the same as that of the first mask patterns 130 and 136. The second mask pattern 146 may have a second width OW2 substantially the same as the first width OW1 of the first mask pattern 130. According to some example embodiments, the second width OW2 of the second mask pattern 146 may be substantially the same as the third width OW3 of the first mask pattern 136. The second mask pattern 146 may be parallel to the first mask patterns 130 and 136. Thus, the method is applicable to a variety of applications. The second mask pattern 146 may have a third center line CL3 substantially parallel to the first center line CL1 of the first mask pattern 130 and the second center line CL2 of the first mask pattern 136.

The first mask patterns 130 and 136 and the second mask pattern 146 may be arranged at substantially the same pitch. For example, the third pitch OP3 between the second mask pattern 146 and the upper first mask pattern 130 may be substantially the same as the fourth pitch OP4 between the second mask pattern 146 and the lower first mask pattern 136. That is, the distance between the upper surface of the second mask pattern 146 and the lower surface of the upper first mask pattern 130 may be substantially the same as the distance between the lower surface of the second mask pattern 146 and the upper surface of the lower first mask pattern 136.

Referring to fig. 6, two first mask patterns 130 in the peripheral exposure region PER may be parallel to each other. The first mask pattern 130 may have a first width OW1. In fig. 6, the upper first mask pattern 130 may have a first center line CL1. The lower first mask pattern 130 may have a second center line CL2. The pitch between the first mask patterns 130 in the peripheral exposure region PER may be wider than the pitch between the unit mask patterns 120 in the unit exposure region CER. For example, the pitch between the first mask patterns 130 in fig. 6 may be wider than the pitch between the first mask patterns 130 in fig. 4.

Because the pitch between the first mask patterns 130 is relatively wide, for example, two second mask patterns 147 and 148 may be disposed between the first mask patterns 130. The second mask patterns 147 and 148 may have substantially the same length as the first mask pattern 130. The second mask patterns 147 and 148 may each have a second width OW2 substantially the same as the first width OW1 of the first mask pattern 130. The second mask patterns 147 and 148 may be parallel to the first mask pattern 130. Accordingly, the second mask patterns 147 and 148 may have third and fourth centerlines CL3 and CL4 that are substantially parallel to the first and second centerlines CL1 and CL2 of the first mask pattern 130, respectively.

The first mask patterns 130 and 136 and the second mask patterns 147 and 148 may be arranged at substantially the same pitch. For example, the fifth pitch OP5 between the upper second mask pattern 147 and the upper first mask pattern 130, the sixth pitch OP6 between the lower second mask pattern 148 and the lower first mask pattern 130, and the seventh pitch OP7 between the second mask patterns 147 and 148 may be substantially the same as each other. That is, the distance between the upper surface of the upper second mask pattern 147 and the lower surface of the upper first mask pattern 130, the distance between the lower surface of the upper second mask pattern 147 and the upper surface of the lower second mask pattern 148, and the distance between the lower surface of the lower second mask pattern 148 and the upper surface of the lower first mask pattern 130 may be substantially the same as each other.

In the present exemplary embodiment, two second mask patterns 147 and 148 are disposed between the first mask patterns 130. However, the number of second mask patterns between the first mask patterns is not limited to or within a specific number. The number of second mask patterns between the first mask patterns 130 may be determined according to the pitch between the first mask patterns.

In order to focus light emitted from the off-axis illumination on the semiconductor device independently of the region (e.g., independently of the cell region or the peripheral region), a pitch between the first mask pattern and the second mask pattern in the peripheral exposure region PER and a pitch between the second mask patterns may be configured to be substantially the same as a pitch between the cell mask patterns in the cell exposure region CER.

Fig. 7 to 9 are cross-sectional views illustrating a method of forming a metal wiring of a semiconductor device using the mask of fig. 1 according to an example embodiment.

Referring to fig. 7, a metal layer 202 may be formed on an upper surface of a semiconductor substrate 210. A photoresist film 250 may be formed on the upper surface of the metal layer 202. The mask 100 of fig. 1 may be disposed over the photoresist film 250.

Light emitted from the off-axis illumination may be obliquely incident to the mask 100. Light incident to the unit exposure regions CER may be irradiated to the photoresist film 250 through the unit mask pattern 120. Light incident to the peripheral exposure region PER may be irradiated to the photoresist film 250 through the first mask pattern 130 and the second mask pattern 140.

Referring to fig. 8, a developing process may be performed on the exposed photoresist film 250 to form a photoresist pattern 252.

Referring to fig. 9, the metal layer 202 may be etched using the photoresist pattern 252 as an etching mask to form the metal wiring 200.

Metal wiring of semiconductor device

Fig. 10 is a plan view showing a metal wiring of the semiconductor device using the mask in fig. 1, fig. 11 is an enlarged plan view of a portion "XI" in fig. 10, fig. 12 is an enlarged plan view of a portion "XII" in fig. 10, fig. 13 is an enlarged plan view of a portion "XIII" in fig. 10, fig. 14 is an enlarged plan view of a portion "XIV" in fig. 10, and fig. 15 is an enlarged plan view of a portion "XV" in fig. 10.

Referring to fig. 10, the metal wiring 200 of the semiconductor device of this example embodiment includes a unit metal pattern 220, signal metal patterns 230, 232, 233, 234, 235, and 236 (e.g., a first signal metal pattern 230, a second signal metal pattern 232, a third signal metal pattern 233, a fourth signal metal pattern 234, a fifth signal metal pattern 235, and a sixth signal metal pattern 236), and dummy metal patterns 240, 242, 244, 246, 247, and 248 (e.g., a first dummy metal pattern 240, a second dummy metal pattern 242, a third dummy metal pattern 244, a fourth dummy metal pattern 246, a fifth dummy metal pattern 247, and a sixth dummy metal pattern 248).

The unit metal pattern 220, the signal metal patterns 230, 232, 233, 234, 235, and 236, and the dummy metal patterns 240, 242, 244, 246, 247, and 248 may be formed on the upper surface of the semiconductor substrate 210. The semiconductor substrate 210 may have a cell region CR and a peripheral region PR. The cell metal pattern 220 may be formed in the cell region CR. The unit metal pattern 220 may be electrically connected to a circuit in the semiconductor substrate 210. The signal metal patterns 230, 232, 233, 234, 235, and 236 and the dummy metal patterns 240, 242, 244, 246, 247, and 248 may be formed in the peripheral region PR. The signal metal patterns 230, 232, 233, 234, 235, and 236 may be electrically connected to circuits in the semiconductor substrate 210. In contrast, the dummy metal patterns 240, 242, 244, 246, 247, and 248 may not be connected to circuits in the semiconductor substrate 210.

Since the shape of the unit metal pattern 220 may be determined according to the shape of the unit mask pattern 120, the unit metal pattern 220 may have an elongated bar shape. The unit metal patterns 220 may be arranged at substantially the same pitch. Accordingly, the pitches between the unit metal patterns 220 may be substantially the same as each other.

Since the shapes of the signal metal patterns 230, 232, 233, 234, 235, and 236 may be determined according to the shapes of the first mask patterns 130, 132, 133, 134, 135, and 136, the signal metal patterns 230, 232, 233, 234, 235, and 236 may have an elongated bar shape. The signal metal patterns 230, 232, 233, 234, 235, and 236 may have a first width MW1 or a third width MW3. The first width MW1 of the signal metal patterns 230, 232, 233, 234, 235, and 236 may be substantially the same as the width of the unit metal pattern 220. According to some example embodiments, the first width MW1 of the signal metal patterns 230, 232, 233, 234, 235, and 236 may be different from the width of the cell metal pattern 220.

The dummy metal patterns 240, 242, 244, 246, 247, and 248 may be formed in portions of the peripheral region PR of the semiconductor substrate 210 where the signal metal patterns 230, 232, 233, 234, 235, and 236 are not formed. Since the shape of the dummy metal patterns 240, 242, 244, 246, 247, and 248 may be determined according to the shape of the second mask patterns 140, 142, 144, 146, 147, and 148, the dummy metal patterns 240, 242, 244, 246, 247, and 248 may have an elongated bar shape. The dummy metal patterns 240, 242, 244, 246, 247, and 248 may be disposed adjacent to the signal metal patterns 230, 232, 233, 234, 235, and 236. The dummy metal patterns 240, 242, 244, 246, 247, and 248 may have a second width MW2 substantially the same as the first width MW1 of the signal metal pattern 230.

Referring to fig. 11, the dummy metal pattern 240 may be placed adjacent to the signal metal pattern 232 having a relatively short length. The signal metal pattern 232 and the dummy metal pattern 240 may be located on a straight line. Since the first width MW1 of the signal metal pattern 232 may be substantially the same as the second width MW2 of the dummy metal pattern 240, the signal metal pattern 232 and the dummy metal pattern 240 may have the same center line CL along the straight line. The dummy metal pattern 240 may be separated from the signal metal pattern 232 by a gap MG. The gap MG may be a distance between adjacent surfaces of the signal metal pattern 232 and the dummy metal pattern 240.

Referring to fig. 12, a dummy metal pattern 242 having a relatively short length may be arranged between two signal metal patterns 234 and 235 that are located on a straight line and each have a relatively short length. The dummy metal pattern 242 may be located on the straight line. Accordingly, the signal metal patterns 234 and 235 and the dummy metal pattern 242 may have a common center line CL along the straight line.

In addition, the gap between the dummy metal pattern 242 and the signal metal pattern 234 may be substantially the same as the gap between the dummy metal pattern 242 and the signal metal pattern 235. For example, the first gap MG1 between adjacent side surfaces of the dummy metal pattern 242 and the signal metal pattern 234 may be substantially the same as the second gap MG2 between adjacent side surfaces of the dummy metal pattern 242 and the signal metal pattern 235. The first and second gaps MG1 and MG2 may be substantially the same as the gaps MG between the signal metal patterns 232 and the dummy metal patterns 240 in fig. 11. The gap MG, the first gap MG1, and the second gap MG2 may be determined according to design rules of metal wirings in the semiconductor device.

Referring to fig. 13, two signal metal patterns 230 in the peripheral region PR may be parallel to each other. The signal metal pattern 230 may have a first width MW1. In fig. 13, the upper signal metal pattern 230 may have a first center line CL1. The lower signal metal pattern 230 may have a second center line CL2. The pitch between the signal metal patterns 230 in the peripheral region PR may be wider than the pitch between the cell metal patterns 220 in the cell region CR.

The dummy metal patterns 244 may be disposed between the signal metal patterns 230. The dummy metal pattern 244 may have a length substantially the same as that of the signal metal pattern 230. The dummy metal pattern 244 may have a second width MW2 substantially the same as the first width MW1 of the signal metal pattern 230. The dummy metal pattern 244 may be substantially parallel to the signal metal pattern 230. Accordingly, the dummy metal pattern 244 may have a third center line CL3 substantially parallel to the first and second center lines CL1 and CL2 of the signal metal pattern 230.

The signal metal pattern 230 and the dummy metal pattern 244 may be arranged at substantially the same pitch. For example, the first pitch MP1 between the dummy metal pattern 244 and the upper signal metal pattern 230 may be substantially the same as the second pitch MP2 between the dummy metal pattern 244 and the lower signal metal pattern 230. That is, the distance between the upper surface of the dummy metal pattern 244 and the lower surface of the upper signal metal pattern 230 may be substantially the same as the distance between the lower surface of the dummy metal pattern 244 and the upper surface of the lower signal metal pattern 230.

Referring to fig. 14, the signal metal pattern 230 and the signal metal pattern 236 in the peripheral region PR may be parallel to each other. In fig. 14, the upper signal metal pattern 230 may have a first width MW1, and the lower signal metal pattern 236 may have a third width MW3 wider than the first width MW 1. The upper signal metal pattern 230 may have a first center line CL1. The lower signal metal pattern 236 may have a second center line CL2. The pitch between the signal metal patterns 230 and 236 in the peripheral region PR may be wider than the pitch between the cell metal patterns 220 in the cell region CR.

The dummy metal pattern 246 may be disposed between the signal metal patterns 230 and 236. The dummy metal pattern 246 may have substantially the same length as the signal metal patterns 230 and 236. The dummy metal pattern 246 may have a second width MW2 substantially the same as the first width MW1 of the signal metal pattern 230. According to some example embodiments, the second width MW2 of the dummy metal pattern 246 may be substantially the same as the third width MW3 of the signal metal pattern 236. The dummy metal pattern 246 may be parallel to the signal metal patterns 230 and 236. Accordingly, the dummy metal pattern 246 may have a third center line CL3 substantially parallel to the first center line CL1 of the signal metal pattern 230 and the second center line CL2 of the signal metal pattern 236.

The signal metal patterns 230 and 236 and the dummy metal pattern 246 may be arranged at substantially the same pitch. For example, the third pitch MP3 between the dummy metal pattern 246 and the upper signal metal pattern 230 may be substantially the same as the fourth pitch MP4 between the dummy metal pattern 246 and the lower signal metal pattern 236. That is, the distance between the upper surface of the dummy metal pattern 246 and the lower surface of the upper signal metal pattern 230 may be substantially the same as the distance between the lower surface of the dummy metal pattern 246 and the upper surface of the lower signal metal pattern 236.

Referring to fig. 15, two signal metal patterns 230 in the peripheral region PR may be parallel to each other. The signal metal pattern 230 may have a first width MW1. In fig. 15, the upper signal metal pattern 230 may have a first center line CL1. The lower signal metal pattern 230 may have a second center line CL2. The pitch between the signal metal patterns 230 in the peripheral region PR may be wider than the pitch between the cell metal patterns 220 in the cell region CR. For example, the pitch between the signal metal patterns 230 in fig. 15 may be wider than the pitch between the signal metal patterns 230 in fig. 13.

Since the pitch between the signal metal patterns 230 is relatively wide, for example, two dummy metal patterns 247 and 248 may be arranged between the signal metal patterns 230. The dummy metal patterns 247 and 248 may have substantially the same length as the signal metal pattern 230. The dummy metal patterns 247 and 248 may each have a second width MW2 substantially the same as the first width MW1 of the signal metal pattern 230. The dummy metal patterns 247 and 248 may be parallel to the signal metal pattern 230. Accordingly, the dummy metal patterns 247 and 248 may have third and fourth centerlines CL3 and CL4 substantially parallel to the first and second centerlines CL1 and CL2 of the signal metal pattern 230, respectively.

The signal metal patterns 230 and 236 and the dummy metal patterns 247 and 248 may be arranged at substantially the same pitch. For example, a fifth pitch MP5 between the upper dummy metal patterns 247 and the upper signal metal patterns 230, a sixth pitch MP6 between the lower dummy metal patterns 248 and the lower signal metal patterns 230, and a seventh pitch MP7 between the dummy metal patterns 247 and 248 may be substantially identical to each other. That is, the distance between the upper surface of the upper dummy metal pattern 247 and the lower surface of the upper signal metal pattern 230, the distance between the lower surface of the upper dummy metal pattern 247 and the upper surface of the lower dummy metal pattern 248, and the distance between the lower surface of the lower dummy metal pattern 248 and the upper surface of the lower signal metal pattern 230 may be substantially the same as each other.

In the present exemplary embodiment, two dummy metal patterns 247 and 248 are arranged between the signal metal patterns 230. However, the number of dummy metal patterns between the signal metal patterns is not limited to or within a specific number. The number of dummy metal patterns between the signal metal patterns 230 may be determined according to the pitch between the signal metal patterns 230.

According to some example embodiments, the second mask pattern for forming the dummy metal pattern in the peripheral region of the semiconductor substrate may be disposed between the first mask patterns for forming the signal metal pattern in the peripheral region of the semiconductor substrate. The width of the second mask pattern may be designed to be substantially the same as the width of the first mask pattern. Accordingly, the metal wiring formed in the peripheral region using the mask including the aforementioned mask pattern may have a minute and uniform pitch corresponding to the pitch of the metal wiring in the cell region. Thus, the metal wiring formed in the peripheral region by using such a mask and off-axis illumination can create a designed shape and size, thereby suppressing or preventing shorting between metal wirings and/or cutting of metal wirings in the peripheral region.

Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of the present inventive concepts. Accordingly, all such modifications are intended to be included within the scope of the present inventive concept as defined in the claims. In the claims means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents, but also equivalent structures. Therefore, it is to be understood that the foregoing is illustrative of various example embodiments and is not to be construed as limited to the specific example embodiments disclosed, and that modifications to the disclosed example embodiments, as well as other example embodiments, are intended to be included within the scope of the appended claims.

Claims (9)

1. A mask, the mask comprising:

a mask substrate including a unit exposure region configured to expose the metal layer in the unit region of the semiconductor device and a peripheral exposure region configured to expose the metal layer in the peripheral region of the semiconductor device;

a first mask pattern including a first sub-mask pattern, a second sub-mask pattern, and a third sub-mask pattern configured to expose a metal layer in a peripheral exposure region of the mask substrate to form a first signal metal pattern, a second signal metal pattern, and a third signal metal pattern, the first sub-mask pattern, the second sub-mask pattern, and the third sub-mask pattern extending in a first direction and being arranged in a second direction perpendicular to the first direction;

A second mask pattern configured to expose the metal layer in the peripheral exposure region of the mask substrate to form a dummy metal pattern, the second mask pattern being adjacent to the second sub-mask pattern in a first direction with a gap between the second mask pattern and the second sub-mask pattern, the second mask pattern being between the first sub-mask pattern and the third sub-mask pattern in a second direction, and the second sub-mask pattern having a width substantially the same as a width of the second mask pattern,

wherein the first mask pattern and the second mask pattern include openings for light passing through to form the first signal metal pattern, the second signal metal pattern, the third signal metal pattern, and the dummy metal pattern.

2. The mask of claim 1, wherein the second mask pattern has a first center line coinciding with a second center line of the second sub-mask pattern along a straight line.

3. The mask of claim 1, further comprising:

another second sub-mask pattern, the second sub-mask pattern and the another second sub-mask pattern being arranged on a straight line;

wherein the second mask pattern is located between the second sub-mask pattern and the other second sub-mask pattern along the straight line; and is also provided with

The first distance between the second mask pattern and the second sub-mask pattern is substantially the same as the second distance between the second mask pattern and the further second sub-mask pattern.

4. A mask according to claim 3, wherein a first center line of the second sub-mask pattern and a second center line of the other second sub-mask pattern in the first direction and a third center line of the second mask pattern coincide with each other along the straight line in the first direction.

5. The mask of claim 1, wherein:

the first, second and third sub-mask patterns extend in the first direction and are parallel to each other;

the second mask pattern extends in the first direction and is located between the first sub-mask pattern and the third sub-mask pattern in the second direction; and is also provided with

The first distance between the second mask pattern and the first sub-mask pattern is substantially the same as the second distance between the second mask pattern and the third sub-mask pattern.

6. The mask of claim 5, wherein the first distance is substantially the same as a third distance between adjacent mask patterns in the unit exposure field.

7. The mask of claim 5, wherein at least two of the first, second, and third sub-mask patterns included in the first mask pattern have different widths, and the second mask pattern has a width substantially the same as a shortest one of the different widths.

8. The mask of claim 5, further comprising:

another first mask pattern including another first sub-mask pattern, another second sub-mask pattern and another third sub-mask pattern;

a further second mask pattern parallel to the second mask pattern and between the further first sub-mask pattern, the further second sub-mask pattern and the further third sub-mask pattern;

a third distance between the another second mask pattern and the another first sub-mask pattern is substantially the same as the first distance.

9. The mask of claim 1, wherein each of the first and third sub-mask patterns has a lateral length in the first direction, the lateral length corresponding to a sum of a first length of the second mask pattern, a second length of the second sub-mask pattern, and a distance of a gap between the second mask pattern and the second sub-mask pattern.

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