CN108535951A - The metal line of mask and the semiconductor device formed using the mask - Google Patents
The metal line of mask and the semiconductor device formed using the mask Download PDFInfo
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- CN108535951A CN108535951A CN201710117177.3A CN201710117177A CN108535951A CN 108535951 A CN108535951 A CN 108535951A CN 201710117177 A CN201710117177 A CN 201710117177A CN 108535951 A CN108535951 A CN 108535951A
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- pattern
- mask
- metal
- metal pattern
- mask pattern
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- 239000002184 metal Substances 0.000 title abstract description 307
- 229910052751 metal Inorganic materials 0.000 title abstract description 307
- 239000004065 semiconductor Substances 0.000 title abstract description 44
- 230000002093 peripheral effect Effects 0.000 abstract description 60
- 239000000758 substrate Substances 0.000 abstract description 11
- 239000011295 pitch Substances 0.000 description 61
- 230000003321 amplification Effects 0.000 description 19
- 238000003199 nucleic acid amplification method Methods 0.000 description 19
- 238000005286 illumination Methods 0.000 description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 9
- 239000010931 gold Substances 0.000 description 9
- 229910052737 gold Inorganic materials 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000004744 fabric Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 239000000571 coke Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
Abstract
Provide a kind of mask and a kind of metal line of semiconductor device.The mask includes：Mask substrate, including unit exposure area and peripheral exposure area, unit exposure area is configured to make the metal layer in the unit area of semiconductor device to expose, peripheral exposure area is configured to make the metal layer in the peripheral region of semiconductor device to expose, first mask pattern is configured to make the exposure of the metal layer in the peripheral exposure area of mask substrate to form signal metal pattern, second mask pattern is configured to make the exposure of the metal layer in the peripheral exposure area of mask substrate to form dummy metal pattern, second mask pattern is adjacent with the first mask pattern, second mask pattern has the width essentially identical with the width of the first mask pattern.
Description
Technical field
Example embodiment is related to the metal line of mask and/or the semiconductor device formed using the mask.More specifically,
Example embodiment is related to the mask for forming metal line in the peripheral region of semiconductor device, and/or uses the mask
The metal line of the semiconductor device of formation.
Background technology
In general, mask can be used to pass through the metal line of exposure technology formation semiconductor device.Metal line may be arranged at
In the unit area and peripheral region of semiconductor device.In pitch comparable cell region between metal line in peripheral region
Metal line between pitch it is wide.In addition, the metal line in unit area can have uniform spacing.On the contrary, external zones
Metal line in domain can have a variety of different spacing.As the pitch between the metal line of semiconductor device narrows,
The narrow metal line of pitch is formed through using the exposure technology of off-axis illumination (off-axis illumination).
According to the prior art, off-axis illumination can have the corresponding coke of pitch between the metal line in unit area
Point.On the contrary, the focus of off-axis illumination can not correspond to the pitch (or a variety of pitches) between the metal line in peripheral region.Cause
This, desired shape or pattern may not had by being formed in the metal line in peripheral region using off-axis illumination.For example, peripheral
Metal line in region can have the size bigger than design size, to be connected to adjacent metal line.On the contrary, peripheral
Metal line in region can have the size smaller than design size, be cut off so as to cause metal line.
Invention content
Some example embodiments provide a kind of mask, and the mask can be formed accurately in peripheral region with design
The metal line of size.
Some example embodiments also provide the metal line of the semiconductor device using aforementioned mask.
According to example embodiment, mask includes：Mask substrate, including unit exposure area and peripheral exposure area, unit
Exposure area is configured to make the metal layer in the unit area of semiconductor device to expose, and peripheral exposure area is configured to make semiconductor
Metal layer exposure in the peripheral region of device, the first mask pattern are configured to make the gold in the peripheral exposure area of mask substrate
Belong to layer exposure to form signal metal pattern, the second mask pattern is configured to make the metal in the peripheral exposure area of mask substrate
To form dummy metal pattern, the second mask pattern is adjacent with the first mask pattern for layer exposure, and the second mask pattern is with the
The essentially identical width of the width of one mask pattern.
In some example embodiments, the second mask pattern can have and be overlapped with the center line of the first mask pattern along straight line
Center line.
In some example embodiments, mask may include that the first mask pattern group, the first mask pattern group may include arranging
Multiple first mask patterns on straight line, the second mask pattern can be located at along the straight line the multiple first mask pattern it
Between, the distance between first mask pattern in the second mask pattern and the multiple first mask pattern can be covered with second
The distance between another the first mask pattern in mould pattern and the multiple first mask pattern is essentially identical.
In some example embodiments, the center line of the center line and the second mask pattern of the multiple first mask pattern
It can coincide with one another along the straight line.
In some example embodiments, mask may include that the first mask pattern group, the first mask pattern group may include each other
Parallel multiple first mask patterns, the second mask pattern can be parallel to the multiple first mask pattern and positioned at the multiple
Between first mask pattern, between first mask pattern in the second mask pattern and the multiple first mask pattern
Distance can be with the distance between another the first mask pattern in the second mask pattern and the multiple first mask pattern base
This is identical.
In some example embodiments, one first in the second mask pattern and the multiple first mask pattern
The distance between mask pattern can be essentially identical with the distance between mask pattern adjacent in unit exposure area.
In some example embodiments, the multiple first mask pattern can have different width, the second mask pattern
There can be the width essentially identical with the shortest width in the width of the multiple first mask pattern.
In some example embodiments, mask may include that the second mask pattern group, the second mask pattern group may include multiple
Second mask pattern, each of the multiple second mask pattern can be located at adjacent in the multiple first mask pattern
Between two the first mask patterns, the multiple second mask pattern can be parallel to each other, between the multiple second mask pattern
Distance can be with the second mask pattern and the basic phase of the distance between the first mask pattern adjacent with second mask pattern
Together.
According to example embodiment, the metal line of semiconductor device includes：Signal metal pattern is located at semiconductor base
In peripheral region；Dummy metal pattern is located in peripheral region, and dummy metal pattern is adjacent with signal metal pattern, illusory gold
Metal patterns have the width essentially identical with the width of signal metal pattern.
In some example embodiments, dummy metal pattern can have and be overlapped with the center line of signal metal pattern along straight line
Center line.
In some example embodiments, metal line may include that signal metal pattern groups, signal metal pattern groups may include
Arrangement multiple signal metal patterns on straight line, dummy metal pattern can be located at along straight line the multiple signal metal pattern it
Between, the distance between signal metal pattern in dummy metal pattern and the multiple signal metal pattern can be with illusory gold
The distance between another signal metal pattern in metal patterns and the multiple signal metal pattern is essentially identical.
In some example embodiments, the center line of the center line and dummy metal pattern of the multiple signal metal pattern
It can coincide with one another along straight line.
In some example embodiments, metal line may include that signal metal pattern groups, signal metal pattern groups may include
Multiple signal metal patterns parallel to each other, dummy metal pattern can be parallel to the multiple signal metal pattern and positioned at described
Between multiple signal metal patterns, a signal metal pattern in dummy metal pattern and the multiple signal metal pattern it
Between distance and dummy metal pattern and the distance between another signal metal pattern in the multiple signal metal pattern
It is essentially identical.
In some example embodiments, the multiple signal metal pattern can have different width, dummy metal pattern
There can be the width essentially identical with shortest width in the width of the multiple signal metal pattern.
In some example embodiments, metal line may include that dummy metal pattern groups, dummy metal pattern groups may include
The multiple dummy metal patterns being arranged between the multiple signal metal pattern, between the multiple dummy metal pattern away from
From can be with dummy metal pattern and the distance between the signal metal pattern adjacent with the dummy metal pattern is essentially identical.
According to example embodiment, the metal line of semiconductor device includes：At least one signal metal pattern, positioned at partly leading
In the peripheral region of body substrate, at least one signal metal pattern is electrically connected to the circuit of semiconductor base；It is at least one
Dummy metal pattern in peripheral region and fills the region that do not occupied by least one signal metal pattern, described
At least one dummy metal pattern is electrically insulated with the circuit of semiconductor base, and at least one dummy metal pattern has and institute
State the essentially identical width of the width of at least one signal metal pattern, at least one dummy metal pattern and it is described at least
The distance between the unit metal pattern in adjacent distance and unit area between the two in one signal metal pattern
It is essentially identical.
In some example embodiments, at least one signal metal pattern can be parallel at least one illusory gold
Metal patterns.
In some example embodiments, at least one signal metal pattern may include the first signal metal pattern and
Binary signal metal pattern, at least one dummy metal pattern can be located at the first signal metal pattern and second signal metal figure
So that center line and at least one dummy metal figure of the first signal metal pattern and second signal metal pattern between case
The center line of case forms straight line.
In some example embodiments, between the first signal metal pattern and at least one dummy metal pattern
One distance can be essentially identical with the second distance between second signal metal pattern and at least one dummy metal pattern.
In some example embodiments, at least one signal metal pattern may include multiple letters with different in width
Number metal pattern, at least one dummy metal pattern can have and the shortest width in the multiple signal metal pattern
Essentially identical width.
According to example embodiment, it is used to be formed the second mask of dummy metal pattern in the peripheral region of semiconductor base
Pattern may be arranged at for being formed between the first mask pattern of signal metal pattern in the peripheral region of semiconductor base.The
The width of two mask patterns can be essentially identical with the width of the first mask pattern.Therefore, it is formed in peripheral region using mask
Metal line can have small and uniform pitch corresponding with the pitch of the metal line in unit area.As a result, passing through
Using the metal line that mask and off-axis illumination are formed in peripheral region can have the shape and size of design can inhibit
Or prevent the short circuit between metal line and/or the cut-out of metal line.
Description of the drawings
Through the following detailed description taken in conjunction with the accompanying drawings, it will be more clearly understood that example embodiment.Fig. 1 to Figure 15 is represented such as
Unrestricted example embodiment described here.
Fig. 1 is the plan view for showing mask according to example embodiment；
Fig. 2 is the amplification view of the part " II " in Fig. 1；
Fig. 3 is the amplification view of the part " III " in Fig. 1；
Fig. 4 is the amplification view of the part " IV " in Fig. 1；
Fig. 5 is the amplification view of the part " V " in Fig. 1；
Fig. 6 is the amplification view of the part " VI " in Fig. 1；
Fig. 7 to Fig. 9 is the metal line that semiconductor device is formed using the mask in Fig. 1 shown according to example embodiment
Method sectional view；
Figure 10 is the plan view for the metal line for showing the semiconductor device using the mask in Fig. 1；
Figure 11 is the amplification view of the part " XI " in Figure 10；
Figure 12 is the amplification view of the part " XII " in Figure 10；
Figure 13 is the amplification view of the part " XIII " in Figure 10；
Figure 14 is the amplification view of the part " XIV " in Figure 10；
Figure 15 is the amplification view of the part " XV " in Figure 10.
Specific implementation mode
Reference is hereinafter shown that various example embodiments are more fully described in the attached drawing of some example embodiments.So
And present inventive concept can be implemented in the form of a variety of different and should not be construed as being limited to example implementation set forth herein
Example.However, providing these example embodiments so that the displosure will be thorough and complete and the range of present inventive concept is abundant
Ground is communicated to those skilled in the art.In the accompanying drawings, for clarity, the size and relative size of layer and region can be exaggerated.
It will be appreciated that when element or layer be referred to as on another element or layer, " being connected to " or " being attached to " it is another
When one element or layer, the element or layer can directly on another element or layer, be directly connected to or be bonded directly to institute
Another element or layer are stated, or may exist intermediary element or middle layer.On the contrary, when element or layer are another referred to as " directly existing "
When element or layer "upper", " being directly connected to " or " being bonded directly to " another element or layer, intermediary element or centre is not present
Layer.Same label indicates same element always.As used herein, term "and/or" includes one or more phases
Close the arbitrary of list items and all combination.
Although will be appreciated that can describe various members using term " first ", " second ", " third " etc. herein
Part, component, regions, layers, and/or portions, but these elements, component, regions, layers, and/or portions should not be by these terms
Limitation.These terms only be used for by an element, component, region, layer or part with another element, component, region, layer or
Part distinguishes.Therefore, without departing from the teaching of the inventive concept, first element discussed below, component, area
Domain, layer or part can be named as second element, component, region, layer or part.
For the ease of explaining, can use herein such as " ... under ", " in ... lower section ", " below ",
" in ... top ", " above " etc. spatially relative terms, with describe elements or features as illustrated in the drawing with it is other
The relationship of elements or features.It will be appreciated that other than the orientation described in comprising figure, spatially relative term also attempt to include
Device in use or operation in different direction.For example, if the device in attached drawing is reversed, it is other to be described as " "
The element of elements or features " below " or " under " then will be by positioning " " other elements or features " top ".Therefore,
Illustrative term " in ... lower section " can include above and below two kinds of orientation.Device (can be rotated by 90 ° by addition positioning
Or in other orientation) and space used herein should be interpreted accordingly with respect to description.
Term used herein and is not intended to be limiting of the invention design merely for the purpose of description specific embodiment.
As it is used herein, unless the context clearly dictates otherwise, otherwise " one (kind/person) " of singulative, " should (described) "
Intention includes plural form.It will also be understood that when term "comprising" and/or " comprising " are used in this description, illustrate that there are institutes
Feature, entirety, step, operation, element and/or component are stated, but do not preclude the presence or addition of other one or more features, whole
Body, step, operation, element, component and/or their group.
Herein, example embodiment is described with reference to sectional view, the sectional view is that idealization example embodiment is (and intermediate
Structure) schematic diagram.Like this, it is contemplated that will occur that the variation of shape is for example shown caused by manufacturing technology and/or tolerance.Cause
This, example embodiment should not be construed as being limited to the specific shape in region shown here, but will include for example by making
Deviation caused by making in shape.For example, the injection region for being shown as rectangle usually will be with round or bending spy at its edge
The gradient of sign and/or implantation concentration, rather than the binary variation from injection region to non-injection regions.Similarly, it is formed by injecting
Buried district may result in and occur some injections in region between the buried area and the surface through which implantation occurs.Therefore, attached
Region shown in figure is actually schematical, their shape is not intended to show the true form in the region of device,
It is not intended to limit the range of present inventive concept.
Unless otherwise defined, otherwise all terms (including technical terms and scientific terms) used herein have and this
The identical meaning of meaning that a little inventive concept those of ordinary skill in the art are generally understood.It will be further understood that unless
So clearly define herein, otherwise term (term such as defined in common dictionary) should be interpreted as having and its
The consistent meaning of meaning in the contexts of the association area, without that should be idealized or excessively formally be explained.
Hereinafter, example embodiment is explained in detail with reference to the accompanying drawings.
Mask
Fig. 1 is the plan view for showing mask according to example embodiment, and Fig. 2 is the enlarged plan of the part " II " in Fig. 1
Figure, Fig. 3 is the amplification view of the part " III " in Fig. 1, and Fig. 4 is the amplification view in the part " IV " in Fig. 1, and Fig. 5 is
The amplification view of part " V " in Fig. 1, Fig. 6 are the amplification views in the part " VI " in Fig. 1.
Referring to Fig.1, the mask 100 of this example embodiment includes mask substrate 110, cell mask pattern 120, the first mask
Pattern 130 and the second mask pattern 140.
Mask substrate 110 can have unit exposure area CER and periphery exposure area PER.Cell mask pattern 120 can shape
At in the CER of unit exposure area.Cell mask pattern 120 in the CER of unit exposure area can be used for making semiconductor device
Metal layer in unit area is exposed to form main metal pattern.First mask pattern 130 and the second mask pattern 140 can be formed
In peripheral exposure area PER.The first mask pattern 130 in peripheral exposure area PER can be used for making the outer of semiconductor device
The metal layer enclosed in region is exposed to form signal metal pattern.The second mask pattern 140 in peripheral exposure area PER can be used
It is exposed in making the metal layer in peripheral region to form dummy metal pattern.
Cell mask pattern 120 may include the opening that light can pass through.Cell mask pattern 120 can have elongated strip shaped
Shape.Cell mask pattern 120 can be with essentially identical spacing arrangement separated from one another.Therefore, between cell mask pattern 120
Pitch can be substantially mutually the same.
First mask pattern 130 may include the opening that light can pass through.First mask pattern 130 can have elongated strip shaped
Shape.First mask pattern 130 can have the first width OW1 or third width OW3.First width OW1 of the first mask pattern 130
It can be essentially identical with the width of cell mask pattern 120.According to some example embodiments, the first of the first mask pattern 130 is wide
Spending OW1 can be of different size with cell mask pattern 120.
As described above, the pitch between cell mask pattern 120 in the CER of unit exposure area can be uniform.Phase
Instead, the pitch between the first mask pattern 130 in peripheral exposure area PER can be non-uniform.That is, peripheral exposure area
The pitch between the first mask pattern 130 in PER can be different from each other.In addition, the first mask pattern 130 can have not
Same length.As a result, can have the portion for not arranging the first mask pattern 130 in the peripheral exposure area PER of mask substrate 110
Point.
Here, the light for being incident on mask 100 from off-axis illumination can be configured to form and will be existed using cell mask pattern 120
The corresponding focus of small pitch between the main metal pattern formed in the unit area of semiconductor device.However, light is described
Focus will not with the first mask pattern 130 will be used to be formed in the peripheral region of semiconductor device signal metal pattern between
Pitch correspond to.Therefore, the signal metal pattern in peripheral region will not be formed to have the shape of design or desired pattern.
Second mask pattern 140 may be formed in the peripheral exposure area PER of mask substrate 110 and not arrange the first mask
In the part of pattern 130.Second mask pattern 140 can make between the focus and signal metal pattern for the light that off-axis illumination emits
Pitch correspond to.
Second mask pattern 140 may include the opening that light can pass through.Second mask pattern 140 can be with the first mask pattern
130 are placed adjacent.Second mask pattern 140 can have second essentially identical with the first width OW1 of the first mask pattern 130
Width OW2.Therefore, the signal metal pattern formed by the first mask pattern 130 can have and pass through the second mask pattern 140
The essentially identical width of the width of the dummy metal pattern of formation.Dummy metal pattern between signal metal pattern can be to partly leading
The section between main metal pattern in the unit area of metal line offer in the peripheral region of body device and semiconductor device
Away from essentially identical pitch.
With reference to Fig. 2, the second mask pattern 140 can be placed adjacent with the first mask pattern 132 with relatively short length.
First mask pattern 132 and the second mask pattern 140 can be located on straight line.Because of the first width OW1 of the first mask pattern 132
Can be essentially identical with the second width OW2 of the second mask pattern 140, so the first mask pattern 132 and the second mask pattern 140
There can be same center line CL along the straight line.Second mask pattern 140 can pass through gap OG and the first mask pattern
132 separate.Gap OG can be the distance between the adjacent side surface of the first mask pattern 132 and the second mask pattern 140.
With reference to Fig. 3, the second mask pattern 142 with relatively short length may be arranged on straight line and all have phase
Between two the first mask patterns 134 and 135 of short length.Second mask pattern 142 can be located on the straight line.Cause
This, the first mask pattern 134 and 135 and the second mask pattern 142 can have the common center line CL along the straight line.
In addition, gap between the second mask pattern 142 and the first mask pattern 134 can with the second mask pattern 142 and
Gap between first mask pattern 135 is essentially identical.For example, the second mask pattern 142 and the first mask pattern 134 is adjacent
Side surface between the first gap OG1 can with the adjacent side surface of the second mask pattern 142 and the first mask pattern 135 it
Between the second gap OG2 it is essentially identical.First gap OG1 and the second gap OG2 can in Fig. 2 the first mask pattern 132 and
Gap OG between second mask pattern 140 is essentially identical.It can be true according to the design rule of the metal line in semiconductor device
Fixed gap OG, the first gap OG1 and the second gap OG2.
With reference to Fig. 4, two the first mask patterns 130 in peripheral exposure area PER can be parallel to each other.First mask pattern
130 can have the first width OW1.The first mask pattern 130 can have the first center line CL1 in fig. 4, the upper.Lower first mask
Pattern 130 can have the second center line CL2.The pitch between the first mask pattern 130 in peripheral exposure area PER is than single
The pitch between cell mask pattern 120 in first exposure area CER is wide.
Second mask pattern 144 may be arranged between the first mask pattern 130.Second mask pattern 144 can have and the
The length of the same length of one mask pattern 130.Second mask pattern 144 can have the with the first mask pattern 130
The second essentially identical one width OW1 width OW2.Second mask pattern 144 may be approximately parallel to the first mask pattern 130.Cause
This, the second mask pattern 144 can have the first center line CL1 and the second center line CL2 with the first mask pattern 130 to put down substantially
Capable third centerline CL3.
The first mask pattern 130 and the second mask pattern 140 can be arranged with essentially identical pitch.For example, second covers
First segment between mould pattern 144 and upper first mask pattern 130 can be with the second mask pattern 144 and lower first mask away from OP1
The second pitch OP2 between pattern 130 is essentially identical.That is, the upper surface of the second mask pattern 144 and upper first mask pattern
The distance between 130 lower surface can with the lower surface of the second mask pattern 144 and the upper surface of lower first mask pattern 130 it
Between distance it is essentially identical.
With reference to Fig. 5, the first mask pattern 130 and the first mask pattern 136 in peripheral exposure area PER can be put down each other
Row.In Figure 5, upper first mask pattern 130 can have the first width OW1, lower first mask pattern 136 that can have wider than first
Spend the third width OW3 of OW1 wide.Upper first mask pattern 130 can have the first center line CL1.Lower first mask pattern 136 can
With the second center line CL2.Pitch comparable cell between the first mask pattern 130 and 136 in peripheral exposure area PER exposes
The pitch between cell mask pattern 120 in the CER of light region is wide.
Second mask pattern 146 may be arranged between the first mask pattern 130 and 136.Second mask pattern 146 can have
With the length of the same length of the first mask pattern 130 and 136.Second mask pattern 146 can have and the first mask artwork
The second essentially identical first width OW1 of case 130 width OW2.According to some example embodiments, the second mask pattern 146
Second width OW2 can be essentially identical with the third width OW3 of the first mask pattern 136.Second mask pattern 146 can be covered with first
Mould pattern 130 is parallel with 136.Therefore.Second mask pattern 146 can have the first center line CL1 with the first mask pattern 130
The substantially parallel third centerline CL3 with the second center line CL2 of the first mask pattern 136.
The first mask pattern 130 and 136 and the second mask pattern 146 can be arranged with essentially identical pitch.For example, the
Third pitch OP3 between two mask patterns 146 and upper first mask pattern 130 can be with the second mask pattern 146 and lower first
The 4th pitch OP4 between mask pattern 136 is essentially identical.That is, the upper surface of the second mask pattern 146 and upper first mask artwork
It the distance between lower surface of case 130 can be with the upper surface of the lower surface and lower first mask pattern 136 of the second mask pattern 146
The distance between it is essentially identical.
With reference to Fig. 6, two the first mask patterns 130 in peripheral exposure area PER can be parallel to each other.First mask pattern
130 can have the first width OW1.In figure 6, upper first mask pattern 130 can have the first center line CL1.Lower first mask
Pattern 130 can have the second center line CL2.The pitch between the first mask pattern 130 in peripheral exposure area PER is comparable
The pitch between cell mask pattern 120 in the CER of unit exposure area is wide.For example, in Fig. 6 between the first mask pattern 130
Pitch it is wide than the pitch between the first mask pattern 130 in Fig. 4.
Because the pitch between the first mask pattern 130 is relatively wide, for example, can between the first mask pattern 130 cloth
Set two the second mask patterns 147 and 148.Second mask pattern 147 and 148 can have the length with the first mask pattern 130
Essentially identical length.Second mask pattern 147 and 148 can have basic with the first width OW1 of the first mask pattern 130
Identical second width OW2.Second mask pattern 147 and 148 can be parallel to the first mask pattern 130.Therefore, the second mask artwork
Case 147 and 148 can have the first center line CL1's and the second center line CL2 for being basically parallel to the first mask pattern 130 respectively
Third centerline CL3 and the 4th center line CL4.
The first mask pattern 130 and 136 and the second mask pattern 147 and 148 can be arranged with essentially identical pitch.Example
Such as, the 5th pitch OP5 between upper second mask pattern 147 and upper first mask pattern 130,148 and of lower second mask pattern
The 7th pitch OP7 between the 6th pitch OP6 and the second mask pattern 147 and 148 between lower first mask pattern 130 can
Substantially mutually the same.That is, between the upper surface of upper second mask pattern 147 and the lower surface of upper first mask pattern 130 away from
The distance between upper surface of lower surface and lower second mask pattern 148 from, upper second mask pattern 147 and lower second
The lower surface of mask pattern 148 and the distance between the upper surface of lower first mask pattern 130 can be substantially mutually the same.
In this exemplary embodiment, two the second mask patterns 147 and 148 are arranged between the first mask pattern 130.
However, the quantity of the second mask pattern between the first mask pattern is not limited to specific quantity or is not limited to specific number
Within amount.The number of the second mask pattern between the first mask pattern can be determined according to the pitch between the first mask pattern 130
Amount.
The light emitted from off-axis illumination is gathered for (for example, unrelated with unit area or peripheral region) unrelated with region
It is burnt on semiconductor devices, pitch between the first mask pattern and the second mask pattern in peripheral exposure area PER and the
Pitch between two mask patterns can be configured to the basic phase of pitch between the cell mask pattern in the CER of unit exposure area
Together.
Fig. 7 to Fig. 9 is the metal line that semiconductor device is formed using the mask in Fig. 1 shown according to example embodiment
Method sectional view.
With reference to Fig. 7, metal layer 202 can be formed on the upper surface of semiconductor base 210.It can be in the upper table of metal layer 202
Photoresist film 250 is formed on face.It can be in the mask 100 in the top layout drawing 1 of photoresist film 250.
The light emitted from off-axis illumination can obliquely be incident on mask 100.The light for being incident on unit exposure area CER can
It is irradiated to photoresist film 250 by cell mask pattern 120.The light for being incident on peripheral exposure area PER can be by the first mask
Pattern 130 and the second mask pattern 140 are irradiated to photoresist film 250.
With reference to Fig. 8, developing process can be executed to form photoetching agent pattern 252 to the photoresist film 250 being exposed.
With reference to Fig. 9, photoetching agent pattern 252 can be etched metal layer 202 to form metal line as etching mask
200。
The metal line of semiconductor device
Figure 10 is the plan view for the metal line for showing the semiconductor device using the mask in Fig. 1, and Figure 11 is in Figure 10
Part " XI " amplification view, Figure 12 is the amplification view of the part " XII " in Figure 10, and Figure 13 is the part in Figure 10
The amplification view of " XIII ", Figure 14 are the amplification views of the part " XIV " in Figure 10, and Figure 15 is the part " XV " in Figure 10
Amplification view.
Referring to Fig.1 0, the metal line 200 of the semiconductor device of this example embodiment includes unit metal pattern 220, letter
Number metal pattern 230 and dummy metal pattern 240.
Unit metal pattern 220, signal metal pattern 230 and dummy metal pattern 240 may be formed at semiconductor base 210
Upper surface on.Semiconductor base 210 can have unit area CR and peripheral region PR.Unit metal pattern 220 may be formed at
In the CR of unit area.Unit metal pattern 220 can be electrically connected with the circuit in semiconductor base 210.230 He of signal metal pattern
Dummy metal pattern 240 may be formed in peripheral region PR.Signal metal pattern 230 may be electrically connected in semiconductor base 210
Circuit.On the contrary, dummy metal pattern 240 can be not attached to the circuit in semiconductor base 210.
Due to can be according to the shape of the shape determining unit metal pattern 220 of cell mask pattern 120, unit metal
Pattern 220 can have elongate strip form.Unit metal pattern 220 can be arranged with essentially identical spacing.Therefore, unit metal
Pitch between pattern 220 can be substantially mutually the same.
Due to that can determine the shape of signal metal pattern 230, signal metal according to the shape of the first mask pattern 130
Pattern 230 can have elongate strip form.Signal metal pattern 230 can have the first width MW1 or third width MW3.Signal gold
First width MW1 of metal patterns 230 can be essentially identical with the width of unit metal pattern 220.According to some example embodiments, letter
First width MW1 of number metal pattern 230 can be of different size with unit metal pattern 220.
What dummy metal pattern 240 may be formed at the peripheral region PR of semiconductor base 210 does not form signal metal pattern
In 230 part.It is illusory due to that can determine the shape of dummy metal pattern 240 according to the shape of the second mask pattern 140
Metal pattern 240 can have elongate strip form.Dummy metal pattern 240 can be placed adjacent with signal metal pattern 230.Illusory gold
Metal patterns 240 can have the second width MW2 essentially identical with the first width MW1 of signal metal pattern 230.
Referring to Fig.1 1, dummy metal pattern 240 can be placed adjacent with the signal metal pattern 232 with opposite short length.
Signal metal pattern 232 and dummy metal pattern 240 can be located on straight line.Due to the first width MW1 of signal metal pattern 232
Can be essentially identical with the second width MW2 of dummy metal pattern 240, therefore signal metal pattern 232 and dummy metal pattern 240
There can be the same center line CL along the straight line.Dummy metal pattern 240 can pass through gap MG and signal metal pattern
232 separate.Gap MG can be the distance between the adjacent surface of signal metal pattern 232 and dummy metal pattern 240.
Referring to Fig.1 2, there is the dummy metal pattern 242 of opposite short length may be arranged on straight line and all have phase
Between two signal metal patterns 234 of short length and 235.Dummy metal pattern 242 can be located on the straight line.Therefore,
Signal metal pattern 234 and 235 can be with the common center line CL along the straight line with dummy metal pattern 242.
In addition, gap between dummy metal pattern 242 and signal metal pattern 234 can with dummy metal pattern 242 and
Gap between signal metal pattern 235 is essentially identical.For example, dummy metal pattern 242 and signal metal pattern 234 is adjacent
The first gap MG1 between side surface can be between dummy metal pattern 242 and the adjacent side of signal metal pattern 235
Second gap MG2 is essentially identical.First gap MG1 and the second gap MG2 can be with signal metal pattern 232 in Figure 11 and illusory
Gap MG between metal pattern 240 is essentially identical.It can be determined according to the design rule of the metal line in semiconductor device
Gap MG, the first gap MG1 and the second gap MG2.
Two signal metal patterns 230 in referring to Fig.1 3, peripheral region PR can be parallel to each other.Signal metal pattern 230
There can be the first width MW1.In fig. 13, upper signal metal pattern 230 can have the first center line CL1.Lower signal metal figure
Case 230 can have the second center line CL2.Pitch comparable cell region between signal metal pattern 230 in peripheral region PR
The pitch between unit metal pattern 220 in CR is wide.
Dummy metal pattern 244 may be arranged between signal metal pattern 230.Dummy metal pattern 244 can have and letter
The length of the same length of number metal pattern 230.Dummy metal pattern 244 can have the with signal metal pattern 230
The second essentially identical one width MW1 width MW2.Dummy metal pattern 244 may be approximately parallel to signal metal pattern 230.Cause
This, dummy metal pattern 244 can have the first center line CL1 and the second center line CL2 with signal metal pattern 230 to put down substantially
Capable third centerline CL3.
Signal metal pattern 230 and dummy metal pattern 244 can be arranged with essentially identical pitch.For example, illusory gold
First segment between metal patterns 244 and upper signal metal pattern 230 can be with dummy metal pattern 244 and lower signal metal away from MP1
The second pitch MP2 between pattern 230 is essentially identical.That is, the upper surface of dummy metal pattern 244 and upper signal metal pattern
The distance between 230 lower surface can with the lower surface of dummy metal pattern 244 and the upper surface of lower signal metal pattern 230 it
Between distance it is essentially identical.
Signal metal pattern 230 and signal metal pattern 236 in referring to Fig.1 4, peripheral region PR can be parallel to each other.
In Figure 14, upper signal metal pattern 230 can have the first width MW1, lower signal metal pattern 236 that can have than the first width
The third width MW3 of MW1 wide.Upper signal metal pattern 230 can have the first center line CL1.Lower signal metal pattern 236 can have
There is the second center line CL2.In pitch comparable cell region CR between signal metal pattern 230 and 236 in peripheral region PR
Unit metal pattern 220 between pitch it is wide.
Dummy metal pattern 246 may be arranged between signal metal pattern 230 and 236.Dummy metal pattern 246 can have
With the length of the same length of signal metal pattern 230 and 236.Dummy metal pattern 246 can have and signal metal figure
The second essentially identical first width MW1 of case 230 width MW2.According to some example embodiments, dummy metal pattern 246
Second width MW2 can be essentially identical with the third width MW3 of signal metal pattern 236.Dummy metal pattern 246 can be with signal gold
Metal patterns 230 are parallel with 236.Therefore, dummy metal pattern 246 can have the first center line CL1 with signal metal pattern 230
The substantially parallel third centerline CL3 with the second center line CL2 of signal metal pattern 236.
Signal metal pattern 230 and 236 and dummy metal pattern 246 can be arranged with essentially identical pitch.For example, empty
If the third pitch MP3 between metal pattern 246 and upper signal metal pattern 230 can be with dummy metal pattern 246 and lower signal
The 4th pitch MP4 between metal pattern 236 is essentially identical.That is, the upper surface of dummy metal pattern 246 and upper signal metal figure
It the distance between lower surface of case 230 can be with the upper surface of the lower surface and lower signal metal pattern 236 of dummy metal pattern 246
The distance between it is essentially identical.
Two signal metal patterns 230 in referring to Fig.1 5, peripheral region PR can be parallel to each other.Signal metal pattern 230
There can be the first width MW1.In fig.15, upper signal metal pattern 230 can have the first center line CL1.Lower signal metal figure
Case 230 can have the second center line CL2.Pitch comparable cell region between signal metal pattern 230 in peripheral region PR
The pitch between unit metal pattern 220 in CR is wide.For example, the pitch between signal metal pattern 230 in Figure 15 is comparable
The pitch between signal metal pattern 230 in Figure 13 is wide.
Since the pitch between signal metal pattern 230 is relatively wide, thus for example can between signal metal pattern 230 cloth
Set two dummy metal patterns 247 and 248.Dummy metal pattern 247 and 248 can be with the length with signal metal pattern 230
Essentially identical length.Dummy metal pattern 247 and 248 can all have it is basic with the first width MW1 of signal metal pattern 230
Identical second width MW2.Dummy metal pattern 247 and 248 can be parallel to signal metal pattern 230.Therefore, dummy metal figure
Case 247 and 248 can be respectively provided with the first center line CL1's and the second center line CL2 for being basically parallel to signal metal pattern 230
Third centerline CL3 and the 4th center line CL4.
Signal metal pattern 230 and 236 and dummy metal pattern 247 and 248 can be arranged with essentially identical pitch.Example
Such as, the 5th pitch MP5 between upper dummy metal pattern 247 and upper signal metal pattern 230, lower 248 and of dummy metal pattern
The 7th pitch MP7 between the 6th pitch MP6 and dummy metal pattern 247 and 248 between lower signal metal pattern 230 can
Substantially mutually the same.That is, between the upper surface of upper dummy metal pattern 247 and the lower surface of upper signal metal pattern 230 away from
From the distance between, the lower surface of upper dummy metal pattern 247 and the upper surface of lower dummy metal pattern 248 and under illusory gold
The lower surface of metal patterns 248 and the distance between the upper surface of lower signal metal pattern 230 can be substantially mutually the same.
In this exemplary embodiment, two dummy metal patterns 247 and 248 are arranged between signal metal pattern 230.
However, the quantity of the dummy metal pattern between signal metal pattern is not limited to specific quantity or is confined to specific quantity
Within.The number of the dummy metal pattern between signal metal pattern 230 can be determined according to the pitch between signal metal pattern 230
Amount.
According to some example embodiments, it is used to form the second of dummy metal pattern in the peripheral region of semiconductor base
Mask pattern may be arranged at in the peripheral region of semiconductor base formed signal metal pattern the first mask pattern it
Between.The width of second mask pattern may be designed as essentially identical with the width of the first mask pattern.Therefore, it is covered using including aforementioned
The metal line that the mask of mould pattern is formed in peripheral region can have corresponding with the pitch of the metal line in unit area
Small and uniform pitch.Therefore, the hardware cloth formed in peripheral region by using such mask and off-axis illumination
Line can generate the shape and size of design, to inhibit or prevent the short circuit between metal line and/or metal in peripheral region
The cut-out of wiring.
Although it have been described that some example embodiments, but the person skilled in the art will easily understand substantially not
In the case of the teachings and advantages for being detached from the novelty of present inventive concept, many modifications can be carried out to exemplary embodiment.Cause
This, all such modifications are intended to be included in the range of present inventive concept as defined by the appended claims.In the claims,
Device adds the clause of function to be intended to cover the structure that this is described as executing the function, rather than just equivalent structures, and
And further include equivalent structure.It is understood, therefore, that aforementioned is that the explanation of various example embodiments and should not be construed is limited
In disclosed specific example embodiments, modification and other example embodiments to disclosed example embodiment are also intended to be included in
In scope of the appended claims.
Claims (20)
1. a kind of mask, the mask include：
Mask substrate, including unit exposure area and peripheral exposure area, unit exposure area is configured to make semiconductor device
Metal layer exposure in unit area, peripheral exposure area is configured to make the metal layer in the peripheral region of semiconductor device to expose
Light；
First mask pattern is configured to make the metal layer in the peripheral exposure area of mask substrate to expose to form signal metal figure
Case；
Second mask pattern is configured to make the metal layer in the peripheral exposure area of mask substrate to expose to form dummy metal figure
Case, the second mask pattern is adjacent with the first mask pattern, and the second mask pattern has the basic phase of width with the first mask pattern
Same width.
2. mask according to claim 1, wherein the second mask pattern has along the center of straight line and the first mask pattern
The center line that line overlaps.
3. mask according to claim 1, wherein：
Mask includes the first mask pattern group, and the first mask pattern group includes multiple first mask patterns of arrangement on straight line；
Second mask pattern is along the straight line between the multiple first mask pattern；
The distance between first mask pattern in second mask pattern and the multiple first mask pattern is covered with second
The distance between another the first mask pattern in mould pattern and the multiple first mask pattern is essentially identical.
4. mask according to claim 3, wherein the center line of the center line of the first mask pattern and the second mask pattern
It coincides with one another along the straight line.
5. mask according to claim 1, wherein：
Mask includes the first mask pattern group, and the first mask pattern group includes multiple first mask patterns parallel to each other；
Second mask pattern is parallel to the multiple first mask pattern and between the multiple first mask pattern；
The distance between first mask pattern in second mask pattern and the multiple first mask pattern is covered with second
The distance between another the first mask pattern in mould pattern and the multiple first mask pattern is essentially identical.
6. mask according to claim 5, wherein described in the second mask pattern and the multiple first mask pattern
The distance between the distance between one first mask pattern and adjacent masking patterns in unit exposure area are essentially identical.
7. mask according to claim 5, wherein the multiple first mask pattern has different width, and second covers
Mould pattern has the width essentially identical with the shortest width in the width of the multiple first mask pattern.
8. mask according to claim 5, wherein：
Mask includes the second mask pattern group, and the second mask pattern group includes multiple second mask patterns, and the multiple second covers
Each of mould pattern is located between two adjacent the first mask patterns in the multiple first mask pattern, the multiple
Second mask pattern is parallel to each other；
The distance between the multiple second mask pattern is with the second mask pattern and adjacent with second mask pattern
The distance between one mask pattern is essentially identical.
9. a kind of metal line of semiconductor device, the metal line of the semiconductor device include：
Signal metal pattern is located in the peripheral region of semiconductor base；
Dummy metal pattern is located in peripheral region, and dummy metal pattern is adjacent with signal metal pattern and dummy metal figure
Case has the width essentially identical with the width of signal metal pattern.
10. the metal line of semiconductor device according to claim 9, wherein dummy metal pattern has and signal gold
The center line that the center line of metal patterns is overlapped along straight line.
11. the metal line of semiconductor device according to claim 9, wherein：
Metal line includes signal metal pattern groups, and signal metal pattern groups include the multiple signal metal figures of arrangement on straight line
Case；
Dummy metal pattern is along straight line between the multiple signal metal pattern；
The distance between signal metal pattern in dummy metal pattern and the multiple signal metal pattern and illusory gold
The distance between another signal metal pattern in metal patterns and the multiple signal metal pattern is essentially identical.
12. the metal line of semiconductor device according to claim 11, wherein in the multiple signal metal pattern
The center line of heart line and dummy metal pattern coincides with one another along straight line.
13. the metal line of semiconductor device according to claim 9, wherein：
Metal line includes signal metal pattern groups, and signal metal pattern groups include multiple signal metal patterns parallel to each other；
Dummy metal pattern is parallel to the multiple signal metal pattern and between the multiple signal metal pattern；
The distance between signal metal pattern in dummy metal pattern and the multiple signal metal pattern and illusory gold
The distance between metal patterns and another signal metal pattern in the multiple signal metal pattern are essentially identical.
14. the metal line of semiconductor device according to claim 13, wherein the multiple signal metal pattern has
Different width, dummy metal pattern have essentially identical with shortest width in the width of the multiple signal metal pattern
Width.
15. the metal line of semiconductor device according to claim 13, wherein：
Metal line includes dummy metal pattern groups, dummy metal pattern groups include be arranged in the multiple signal metal pattern it
Between multiple dummy metal patterns；
The distance between the multiple dummy metal pattern is with dummy metal pattern and the letter adjacent with the dummy metal pattern
The distance between number metal pattern is essentially identical.
16. a kind of metal line of semiconductor device, the metal line of the semiconductor device include：
At least one signal metal pattern is located in the peripheral region of semiconductor base, at least one signal metal pattern
It is electrically connected to the circuit of semiconductor base；
At least one dummy metal pattern, in peripheral region and filling is not accounted for by least one signal metal pattern
Some regions, at least one dummy metal pattern are electrically insulated with the circuit of semiconductor base, at least one illusory gold
Metal patterns have the width essentially identical with the width of at least one signal metal pattern, at least one dummy metal
The unit metal in adjacent distance and unit area between the two in pattern and at least one signal metal pattern
The distance between pattern is essentially identical.
17. the metal line of semiconductor device according to claim 16, wherein at least one signal metal pattern
It is parallel at least one dummy metal pattern.
18. the metal line of semiconductor device according to claim 16, wherein：
At least one signal metal pattern includes the first signal metal pattern and second signal metal pattern；
At least one dummy metal pattern is between the first signal metal pattern and second signal metal pattern so that the
The center of the center line and at least one dummy metal pattern of one signal metal pattern and second signal metal pattern is linear
It is in line.
19. the metal line of semiconductor device according to claim 16, wherein the first signal metal pattern and it is described extremely
The first distance between a few dummy metal pattern and second signal metal pattern and at least one dummy metal pattern
Between second distance it is essentially identical.
20. metal line according to claim 16, wherein at least one signal metal pattern includes having difference
Multiple signal metal patterns of width, at least one dummy metal pattern have in the multiple signal metal pattern
The essentially identical width of shortest width.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710117177.3A CN108535951B (en) | 2017-03-01 | 2017-03-01 | Mask and metal wiring of semiconductor device formed using the same |
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| CN201710117177.3A CN108535951B (en) | 2017-03-01 | 2017-03-01 | Mask and metal wiring of semiconductor device formed using the same |
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| CN108535951B CN108535951B (en) | 2023-05-02 |
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| CN1209650A (en) * | 1997-08-25 | 1999-03-03 | 三菱电机株式会社 | Semiconductor device and manufacturing method thereof |
| US20050076320A1 (en) * | 2003-10-02 | 2005-04-07 | Kawasaki Microelectronics, Inc. | Layout structure of semiconductor integrated circuit and method for forming the same |
| JP2006339228A (en) * | 2005-05-31 | 2006-12-14 | Sharp Corp | Wafer of large-scale integrated circuit and method of manufacturing same |
| US20090072322A1 (en) * | 2007-09-18 | 2009-03-19 | Samsung Electronics Co., Ltd. | Semiconductor devices including line patterns separated by cutting regions |
| US20100306727A1 (en) * | 2009-05-28 | 2010-12-02 | Nec Electronics Corporation | Method and design system for semiconductor integrated circuit |
| CN105095561A (en) * | 2014-05-23 | 2015-11-25 | 格罗方德半导体公司 | Mask-aware routing and resulting device |
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2017
- 2017-03-01 CN CN201710117177.3A patent/CN108535951B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1209650A (en) * | 1997-08-25 | 1999-03-03 | 三菱电机株式会社 | Semiconductor device and manufacturing method thereof |
| US20050076320A1 (en) * | 2003-10-02 | 2005-04-07 | Kawasaki Microelectronics, Inc. | Layout structure of semiconductor integrated circuit and method for forming the same |
| JP2006339228A (en) * | 2005-05-31 | 2006-12-14 | Sharp Corp | Wafer of large-scale integrated circuit and method of manufacturing same |
| US20090072322A1 (en) * | 2007-09-18 | 2009-03-19 | Samsung Electronics Co., Ltd. | Semiconductor devices including line patterns separated by cutting regions |
| US20100306727A1 (en) * | 2009-05-28 | 2010-12-02 | Nec Electronics Corporation | Method and design system for semiconductor integrated circuit |
| CN105095561A (en) * | 2014-05-23 | 2015-11-25 | 格罗方德半导体公司 | Mask-aware routing and resulting device |
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| CN108535951B (en) | 2023-05-02 |
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