CN108470803B - Epitaxial wafer of light emitting diode and manufacturing method thereof - Google Patents

Abstract

The invention discloses an epitaxial wafer of a light-emitting diode and a manufacturing method thereof, belonging to the technical field of optoelectronic manufacturing. The epitaxial wafer includes a substrate and a buffer layer, an undoped gallium nitride layer, an N-type layer, a carrier improvement layer, an active layer, an electron blocking layer, a P-type layer, and a P-type contact stacked sequentially on the substrate. Layer, the carrier improvement layer is a metal conductive layer or a metal oxide conductive layer, by setting the carrier improvement layer between the active layer and the N-type layer, because the carrier improvement layer is a metal conductive layer or a metal oxide Conductive layer, the resistance of the carrier improvement layer is low, and the resistance of each region is relatively uniform, which is conducive to the lateral expansion of electrons in the carrier improvement layer, so that the electrons enter the active layer more uniformly, thereby improving the active layer. The uniformity and consistency of the luminance of each area of the source layer.

Description

Epitaxial wafer of light emitting diode and manufacturing method thereof

technical field

The invention relates to the technical field of optoelectronic manufacturing, in particular to an epitaxial wafer and a manufacturing method of a light emitting diode.

Background technique

LED (Light Emitting Diode, Light Emitting Diode) has the advantages of small size, long life, low power consumption, etc., and is currently widely used in automobile signal lights, traffic signal lights, display screens and lighting equipment.

The existing LED mainly includes a substrate and a buffer layer, an undoped gallium nitride layer, an N-type layer, an active layer, an electron blocking layer, a P-type layer and a P-type contact layer stacked on the substrate in sequence. Finally, carriers (including electrons in the N-type layer and holes in the P-type layer) will migrate to the active layer and recombine in the active layer to emit light.

In the process of realizing the present invention, the inventor finds that there are at least the following problems in the prior art:

Since the mobility of electrons is relatively fast, and the mobility of electrons in different regions on the N-type layer is also inconsistent, this makes the luminance of each region of the active layer uneven.

Contents of the invention

In order to solve the problem of uneven luminance in each area of the active layer, embodiments of the present invention provide an epitaxial wafer of a light emitting diode and a manufacturing method thereof. Described technical scheme is as follows:

On the one hand, an embodiment of the present invention provides an epitaxial wafer of a light-emitting diode. The epitaxial wafer includes a substrate, a buffer layer, an undoped gallium nitride layer, an N-type layer, and a carrier layer sequentially stacked on the substrate. The carrier improving layer, the active layer, the electron blocking layer, the P-type layer and the P-type contact layer, the carrier improving layer is a metal conductive layer, and the metal conductive layer is made of a single metal or alloy, and the single The metal includes any one of Mg, Ca, and Yb, and the alloy includes any one of Mg:Ag, Yb:Ag.

Optionally, the carrier improvement layer has a thickness of 5-100 nm.

On the other hand, an embodiment of the present invention also provides a method for manufacturing an epitaxial wafer, the method comprising:

providing a substrate;

A buffer layer, an undoped gallium nitride layer, an N-type layer, a carrier improvement layer, an active layer, an electron blocking layer, a P-type layer, and a P-type contact layer are epitaxially grown in sequence on the substrate. The flow improvement layer is a metal conductive layer, and the metal conductive layer is made of a single metal or an alloy, the single metal includes any one of Mg, Ca, and Yb, and the alloy includes Mg:Ag, Yb:Ag any of the

Optionally, the carrier improvement layer is fabricated by physical vapor deposition.

Optionally, the growth temperature of the carrier improvement layer is 400-800°C.

Optionally, the growth pressure of the carrier improvement layer is 5-150 mtorr.

The beneficial effect brought by the technical solution provided by the embodiment of the present invention is: by disposing the carrier improvement layer between the active layer and the N-type layer, since the carrier improvement layer is a metal conductive layer or a metal oxide conductive layer, The resistance of the carrier improvement layer is low, and the resistance of each region is relatively uniform, which is conducive to the lateral expansion of electrons in the carrier improvement layer, so that the electrons enter the active layer more uniformly, thereby improving the active layer. The uniformity and consistency of the brightness of each area.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained based on these drawings without creative effort.

Fig. 1 is a structural diagram of an epitaxial wafer of a light emitting diode provided by an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of an active layer provided by an embodiment of the present invention;

Fig. 3 is a flow chart of a method for manufacturing an epitaxial wafer of a light-emitting diode provided by an embodiment of the present invention;

Fig. 4 is a flowchart of another manufacturing method of a light emitting diode provided by an embodiment of the present invention;

5-11 are schematic diagrams of the preparation process of an epitaxial wafer of a light emitting diode provided by an embodiment of the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the implementation manner of the present invention will be further described in detail below in conjunction with the accompanying drawings.

FIG. 1 is a structural diagram of an epitaxial wafer of a light emitting diode provided by an embodiment of the present invention. As shown in FIG. 1, the epitaxial wafer includes a substrate 10 and a buffer layer 20, an undoped gallium nitride layer 30, an N-type layer 40, a carrier improvement layer 50, and an active layer sequentially stacked on the substrate 10. 60. The electron blocking layer 70, the P-type layer 80 and the P-type contact layer 90, the carrier improving layer 50 is a metal conductive layer or a metal oxide conductive layer.

In the embodiment of the present invention, the carrier improvement layer is provided between the active layer and the N-type layer. Since the carrier improvement layer is a metal conductive layer or a metal oxide conductive layer, the resistance of the carrier improvement layer is low, and The resistance of each region is relatively uniform, which is conducive to the lateral expansion of electrons in the carrier improvement layer, so that electrons can enter the active layer more uniformly, thereby improving the uniformity and consistency of the luminous brightness of each region of the active layer.

In an embodiment of the present invention, the metal conductive layer can be made of a single metal.

Specifically, the single metal may include any one of Mg, Ca, and Yb. Mg, Ca, and Yb have good electrical conductivity, which is conducive to more uniform migration of electrons to the active layer.

In another embodiment of the present invention, the metal conductive layer can also be made of alloy.

Specifically, the alloy may include any one of Mg:Ag and Yb:Ag.

In another embodiment of the present invention, the metal conductive layer may be a metal oxide conductive layer, and the metal oxide conductive layer may include any one of oxides of Mg, Ca, and Yb. Oxides of Mg, Ca, and Yb also have good electrical conductivity, which is conducive to more uniform migration of electrons to the active layer.

Optionally, the thickness of the carrier improvement layer 50 may be 5-100 nm. Under this thickness, the carrier improvement layer 50 is translucent, and can reflect the light emitted by the active layer 60 to the side of the P-type layer 70, which is beneficial to improving the light extraction efficiency of the front side of the LED.

Optionally, the substrate 10 may be a sapphire substrate, which is a commonly used substrate with mature technology and low cost.

The buffer layer 20 can be a GaN buffer layer, and the thickness of the buffer layer 20 can be 15-35 nm. The thickness of the grown GaN buffer layer is different, and the quality of the finally formed epitaxial layer will also be different. If the thickness of the GaN buffer layer is too thin, then It will cause the surface of the GaN buffer layer to be relatively loose and rough, which cannot provide a good template for the growth of subsequent structures. As the thickness of the GaN buffer layer increases, the surface of the GaN buffer layer will gradually become denser and smoother, which is conducive to the subsequent structure. However, if the thickness of the GaN buffer layer is too thick, the surface of the GaN buffer layer will be too dense, which is also not conducive to the growth of subsequent structures, and the lattice defects in the epitaxial layer cannot be reduced.

Optionally, the thickness of the undoped GaN layer 30 may be 1-5 μm, and in this embodiment, the thickness of the undoped GaN layer 30 is 3 μm.

Optionally, the N-type layer 40 is an N-type GaN layer, the thickness of the N-type layer 40 may be 1-5 μm, and the doping concentration of Si in the N-type layer 40 may be 10 ¹⁸ -10 ¹⁹ cm ^-3 .

Fig. 2 is a schematic structural diagram of an active layer provided by an embodiment of the present invention. As shown in Fig. 2, the active layer 60 may include alternately stacked 5-11 periods of In _x Ga _1-x N layers 61 and GaN Layer 62, 0<x<1, where the In _x Ga _1-x N layer 61 may have a thickness of 2-4 nm, and the GaN layer 62 may have a thickness of 9-20 nm. In this embodiment, the In _x Ga _1-x The thickness of the N layer 61 is 3 nm, and the thickness of the GaN layer 62 is 15 nm.

It should be noted that the numbers of the In _x Ga _1-x N layer 61 and the GaN layer 62 shown in FIG. 2 are only for illustration and are not intended to limit their respective numbers.

The electron blocking layer 70 may be a P-type Al _y Ga _1-y N layer, where 0.1<y<0.5. The thickness of the electron blocking layer 70 may be 50-150 nm, and in this embodiment, the thickness of the electron blocking layer 70 is 100 nm.

Optionally, the P-type layer 80 is a P-type GaN layer, and the thickness of the P-type layer 80 may be 100-800 nm. In this embodiment, the thickness of the P-type layer 80 is 500 nm.

Optionally, the thickness of the P-type contact layer 90 may be 5-300 nm. In this embodiment, the thickness of the P-type contact layer 90 is 200 nm.

Fig. 3 is a flow chart of a method for manufacturing an epitaxial wafer of a light-emitting diode provided by an embodiment of the present invention, which is used to manufacture the epitaxial wafer shown in Fig. 1 , as shown in Fig. 3 , the manufacturing method includes:

S11: Provide a substrate.

In this embodiment, a sapphire substrate is selected.

S12: epitaxially growing a buffer layer, an undoped gallium nitride layer, an N-type layer, a carrier improvement layer, an active layer, an electron blocking layer, a P-type layer, and a P-type contact layer on the substrate in sequence.

Wherein, the carrier improvement layer is a metal conductive layer or a metal oxide conductive layer.

In the embodiment of the present invention, the carrier improvement layer is provided between the active layer and the N-type layer. Since the carrier improvement layer is a metal conductive layer or a metal oxide conductive layer, the resistance of the carrier improvement layer is low, and The resistance of each region is relatively uniform, which is conducive to the lateral expansion of electrons in the carrier improvement layer, so that electrons can enter the active layer more uniformly, thereby improving the uniformity and consistency of the luminous brightness of each region of the active layer.

Fig. 4 is a flow chart of another light-emitting diode manufacturing method provided by an embodiment of the present invention. The manufacturing method provided in Fig. 4 will be described in detail below in conjunction with accompanying drawings 5-11:

S21: Provide a substrate.

When implemented, the substrate may be a sapphire substrate, which is a common substrate with mature technology and low cost.

In step S21, the sapphire substrate may be pretreated, which may specifically include annealing the sapphire substrate in a hydrogen atmosphere for 8 minutes at an annealing temperature of 1000-1200° C., and then nitriding the sapphire substrate.

S22: epitaxially growing a buffer layer on the substrate.

As shown in FIG. 5 , a GaN buffer layer 20 is grown on the substrate 10 .

Wherein, the thickness of the GaN buffer layer may be 15nm-35nm. The thickness of the grown GaN buffer layer is different, and the quality of the final epitaxial layer will also be different. If the thickness of the GaN buffer layer is too thin, the surface of the GaN buffer layer will be relatively loose and rough, which cannot provide a solid foundation for the growth of subsequent structures. For a good template, as the thickness of the GaN buffer layer increases, the surface of the GaN buffer layer gradually becomes denser and smoother, which is conducive to the growth of subsequent structures. However, if the thickness of the GaN buffer layer is too thick, it will cause the GaN buffer layer The surface is too dense, which is also not conducive to the growth of subsequent structures, and cannot reduce the lattice defects in the epitaxial layer.

Specifically, when growing the GaN buffer layer, the growth temperature may be 400-600° C., and the growth pressure may be 400 torr-600 torr.

After growing the GaN buffer layer, in-situ annealing can also be performed on the buffer layer, the temperature is 1000-1200°C, the annealing time is 5-10 minutes, and the annealing pressure is 400torr-600torr.

S23: growing an undoped gallium nitride layer on the buffer layer.

As shown in FIG. 6 , an undoped GaN layer 30 is grown on the buffer layer 20 . The thickness of the undoped GaN layer 30 may be 1-5 μm, and in this embodiment, the thickness of the undoped GaN layer 30 is 3 μm.

The growth temperature of the undoped gallium nitride layer 30 may be 1000-1100° C., and the growth pressure may be 100 torr-500 torr.

S24: growing an N-type layer on the undoped GaN layer.

As shown in FIG. 7 , an N-type layer 40 is grown on the undoped GaN layer 30 .

Realistically, the N-type layer 40 is an N-type GaN layer, the thickness of the N-type layer 40 can be 1-5 μm, and the doping concentration of Si in the N-type layer 40 can be 10 ¹⁸ -10 ¹⁹ cm ⁻³ .

The growth temperature of the N-type layer 40 may be 1000-1200° C., and the growth pressure may be 100 torr-500 torr.

S25: growing a carrier improvement layer on the N-type layer.

As shown in FIG. 8 , a carrier improving layer 50 is grown on the N-type layer 40 . The carrier improvement layer 50 can be a metal conductive layer or a metal oxide conductive layer.

In an embodiment of the present invention, the metal conductive layer can be made of a single metal.

Specifically, the single metal may include any one of Mg, Ca, and Yb. Mg, Ca, and Yb have good electrical conductivity, which is conducive to more uniform migration of electrons to the active layer.

In another embodiment of the present invention, the metal conductive layer can also be made of alloy.

Specifically, the alloy may include any one of Mg:Ag and Yb:Ag.

In another embodiment of the present invention, the metal conductive layer may be a metal oxide conductive layer, and the metal oxide conductive layer may include any one of oxides of Mg, Ca, and Yb. Oxides of Mg, Ca, and Yb also have good electrical conductivity, which is conducive to more uniform migration of electrons to the active layer.

Specifically, the carrier improvement layer 50 can be fabricated by physical vapor deposition. The carrier improving layer 50 can be fabricated in an argon atmosphere, the distance between the substrate and the target can be 4-15 cm, the power can be 2500-4000 W, and the rotation speed can be 30-200 r/min.

When it is realized, the purity of the target material is not less than 99.99%, so as to ensure the quality of the manufactured metal conductive layer.

The growth temperature of the carrier improving layer 50 may be 400-800°C.

The growth pressure of the carrier improvement layer 50 may be 5-150 mtorr.

S26: growing an active layer on the carrier improvement layer.

As shown in FIG. 9 , an active layer 60 is grown on the carrier improving layer 50 .

Specifically, the active layer 60 may include 5-11 periods of In _x Ga _1-x N layers 61 and GaN layers 62 stacked alternately, where 0<x<1.

Optionally, the thickness of the In _x Ga _1-x N layer 61 may be 2-4 nm, and the thickness of the GaN layer 62 may be 9-20 nm. In this embodiment, the thickness of the In _x Ga _1-x N layer 61 is 3 nm , the thickness of the GaN layer 62 is 15 nm.

When implemented, the growth temperature of the In _x Ga _1-x N layer 61 may be 720-829° C., and the growth pressure may be 100-500 torr. The growth temperature of the GaN layer 62 may be 850-959° C., and the growth pressure may be 100-500 torr.

It should be noted that the numbers of the In _x Ga _1-x N layer 61 and the GaN layer 62 shown in FIG. 9 are only for illustration and are not intended to limit their respective numbers of layers.

S27: growing an electron blocking layer on the active layer.

As shown in FIG. 10 , an electron blocking layer 70 is grown on the active layer 60 . The electron blocking layer 70 may be a P-type Al _y Ga _1-y N layer, where 0.1<y<0.5.

The growth temperature of the electron blocking layer 70 may be 850-1080° C., and the growth pressure may be 200-500 torr. The thickness of the grown electron blocking layer 70 may be 50-150 nm, and in this embodiment, the thickness of the electron blocking layer 70 is 100 nm. If the thickness of the electron blocking layer 70 is too thin, electrons can easily pass through the electron blocking layer 70 , and if the electron blocking layer 70 is too thick, the absorption of light by the electron blocking layer 70 will be increased, resulting in reduced brightness.

S28: growing a P-type layer on the electron blocking layer.

As shown in FIG. 11 , a P-type layer 80 is grown on the electron blocking layer 70 .

Specifically, the P-type layer 80 is a P-type GaN layer, and the thickness of the P-type layer 80 may be 100-800 nm. In this embodiment, the thickness of the P-type layer 80 is 500 nm.

The growth temperature of the P-type layer 80 may be 850-1080° C., and the growth pressure may be 100-300 torr.

S29: growing a P-type contact layer on the P-type layer.

Referring to FIG. 1 , a P-type contact layer 90 is grown on the P-type layer 80 .

Specifically, the thickness of the P-type contact layer 90 may be 5-300 nm. In this embodiment, the thickness of the P-type contact layer 90 is 200 nm.

The growth temperature of the P-type contact layer 90 may be 850-1080° C., and the growth pressure may be 100-300 torr.

After the growth of the P-type contact layer 90 is completed, annealing treatment may be performed in an ammonia atmosphere, the annealing temperature is 650-850° C., and the annealing treatment time is 5-15 minutes.

After step S29 is completed, subsequent processing can be performed on the epitaxial wafer to complete the fabrication of the LED chip.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection of the present invention. within range.

Claims (6)

1. An epitaxial wafer of a light-emitting diode, characterized in that the epitaxial wafer includes a substrate and a buffer layer, an undoped gallium nitride layer, an N-type layer, and a carrier-improving layer sequentially stacked on the substrate. Layer, active layer, electron blocking layer, P-type layer and P-type contact layer, the carrier improvement layer is a metal conductive layer, the metal conductive layer is made of a single metal or alloy, and the single metal includes Mg , Ca, Yb, the alloy includes any one of Mg:Ag, Yb:Ag. 2 . The epitaxial wafer according to claim 1 , wherein the thickness of the carrier improvement layer is 5-100 nm. 3. A method for making an epitaxial wafer of a light-emitting diode, characterized in that, the method for making comprises: providing a substrate; A buffer layer, an undoped gallium nitride layer, an N-type layer, a carrier improvement layer, an active layer, an electron blocking layer, a P-type layer, and a P-type contact layer are epitaxially grown in sequence on the substrate. The flow improvement layer is a metal conductive layer, and the metal conductive layer is made of a single metal or an alloy, the single metal includes any one of Mg, Ca, and Yb, and the alloy includes Mg:Ag, Yb:Ag any of the 4. The manufacturing method according to claim 3, wherein the carrier improving layer is manufactured by physical vapor deposition. 5 . The manufacturing method according to claim 3 , wherein the growth temperature of the carrier improving layer is 400-800° C. 5 . 6 . The manufacturing method according to claim 3 , wherein the growth pressure of the carrier improving layer is 5-150 mtorr.