CN108460296A - SOC chip with debugging interface security mechanism and method - Google Patents
SOC chip with debugging interface security mechanism and method Download PDFInfo
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- CN108460296A CN108460296A CN201611126402.1A CN201611126402A CN108460296A CN 108460296 A CN108460296 A CN 108460296A CN 201611126402 A CN201611126402 A CN 201611126402A CN 108460296 A CN108460296 A CN 108460296A
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- 238000000034 method Methods 0.000 title claims abstract description 28
- 230000007246 mechanism Effects 0.000 title claims abstract description 26
- 238000012544 monitoring process Methods 0.000 claims abstract description 14
- 238000003860 storage Methods 0.000 claims description 23
- 238000010586 diagram Methods 0.000 description 7
- 230000008859 change Effects 0.000 description 3
- 239000000306 component Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 235000013399 edible fruits Nutrition 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000012795 verification Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/30—Authentication, i.e. establishing the identity or authorisation of security principals
- G06F21/31—User authentication
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/60—Protecting data
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/74—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information operating in dual or compartmented mode, i.e. at least one secure mode
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F2221/2141—Access rights, e.g. capability lists, access control lists, access tables, access matrices
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computer Security & Cryptography (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Health & Medical Sciences (AREA)
- General Health & Medical Sciences (AREA)
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- Storage Device Security (AREA)
- Microcomputers (AREA)
Abstract
The invention provides an SOC chip with a debugging interface security mechanism and a method, wherein the chip comprises: debugging a port; a microprocessor including a debug interface; the memory unit is used for pre-storing the security access password of the debugging interface; the safety control unit is connected between the debugging port and the debugging interface and used for monitoring the input time sequence of external equipment connected with the debugging port; when the input time sequence is correct, comparing the input password with the debugging interface security access password; if the comparison result is consistent, opening a channel from the debugging port to the debugging interface; if the comparison result is not consistent, the channel is closed. The security control unit is added between the physical debugging port and the internal debugging interface, the security control unit is isolated from physical connection, and the debugging port and the internal debugging interface can be physically communicated only when a time sequence waveform signal containing a correct password is input on the debugging port, so that the authority of accessing internal resources is obtained.
Description
Technical field
The invention belongs to system on chip fields, are related to a kind of SOC chip and method with debugging interface security mechanism.
Background technology
System on chip (System on Chip, abbreviation SOC), says, it is the chip of information system core from narrow sense angle
It is integrated, it is that system core component is integrated on one chip；It is said from broadest scope, SOC is a mini system, will be micro-
Processor, Analog IP core, digital IP kernel and memory (or piece external storage control interface) are integrated on one chip, typically objective
Family customization, or the standardized product towards special-purpose.
Hardware debugging interface provides effective method for the system testing of SoC chip and sheet sand covered, however
Cause security risk.
Current SoC chip all can integrated debugging interface be used for chip testing and system debug, user can be very convenient
Using upper computer software carry out application development or use cd-rom recorder programming user program.But after providing conveniently,
Also security risk is brought.Debugging interface is known as back door by industry always, i.e., by applying specific excitation to debugging port,
It may be implemented to obtain and change chip interior resource and the purpose of memory data.
Therefore, how SOC chip and method with debugging interface security mechanism are provided, to improve chip security, at
For those skilled in the art's important technological problems urgently to be resolved hurrily.
Invention content
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide one kind having debugging interface safe machine
The SOC chip and method of system, for solving the problems, such as that SOC chip security risk is higher in the prior art.
In order to achieve the above objects and other related objects, the present invention provides a kind of SOC with debugging interface security mechanism
Chip and method, including：
Debug port；
Microprocessor, including debugging interface；
Storage unit has secure access to password for prestoring debugging interface；
Security control unit is connected between the debugging port and the debugging interface, is connected to for monitoring described
Debug the input timing of the external equipment of port；When input timing is correct, then input password is visited safely with the debugging interface
Ask that password is compared；If comparison result is consistent, the debugging port to the channel between the debugging interface is opened；Such as
Fruit comparison result is inconsistent, then closes the debugging port to the channel between the debugging interface.
Optionally, the security control unit includes：
First password register is connect with the storage unit, for being received after chip powers on and completes to reset operation
And the temporary debugging interface from the storage unit has secure access to password；
Second password register, for the temporary input password from the external equipment；
Input timing monitoring unit is connected with the debugging port and the second password register, for monitoring connection
It is in the input timing of the external equipment of the debugging port, and when input timing is correct that the write-in described second of input password is close
Code memory；
Comparator, two input terminals of the comparator respectively with the first password register and the second password register
It is connected, for the input password to be compared with debugging interface secure access password.
Optionally, chip is powered on and is completed after resetting operation, and the debugging interface secure access from the storage unit is close
Code is to be written to the first password register by pure hardware logic, and the first password register can not be by the microprocessor
Device accesses.
Optionally, the security control unit is arranged to when password compares number be more than preset times, then locks chip.
Optionally, the security control unit is arranged to after locking chip, no longer receives password comparison data, only receives
Memory scrub instructions.
Optionally, the preset times are 1~10.
Optionally, the debugging interface secure access password is 128 bits.
Optionally, the storage unit is nonvolatile memory.
Optionally, the external equipment of depositing is host computer or cd-rom recorder.
The present invention also provides a kind of method of debugging interface security mechanism, it is applied to having described in any one as above and adjusts
The SOC chip for mouthful security mechanism of trying, the method includes：
Chip is powered on and is completed after resetting operation, and the tune in the storage unit will be stored in advance in by pure hardware logic
Mouth of trying secure access password is written in first password register, and the first password register can not be by the microprocessor
It accesses；
The security control unit moment monitoring is connected to the input timing of the external equipment of the debugging port, works as sequential
Correctly, then the password register is written into input password；
After the completion of inputting password acceptance, the security control unit will input password and be had secure access to the debugging interface
Password is compared；
If comparison result is consistent, the debugging port to the channel between the debugging interface is opened；If compared
As a result inconsistent, then close the debugging port to the channel between the debugging interface.
As described above, the SOC chip with debugging interface security mechanism of the present invention and and method, have below beneficial to imitating
Fruit：The present invention realizes the secure access of debugging interface using digital circuit framework, in physics debugging port and internal debugging interface
Between add security control unit, be isolated from physical connection.Only when input on debugging port includes proper password
It could be physically by debugging port and internal debugging orifice, to obtain the power for accessing internal resource when sequence waveform signal
Limit.Security control unit is responsible for the verification of password and charges to the number of comparison, automatic to lock if it is more than 3 times to compare number.
After chip locking, security control unit no longer receives password comparison data, only receives NVM memory erasing instruction.User can only
Chip controls can be just re-fetched after executing NVM memory erasing instruction to weigh, and the user being stored at this time in NVM memory
Data have been wiped free of, to realize the purpose of user data in protection NVM memory unit.
Description of the drawings
Fig. 1 be shown as the present invention SOC chip with debugging interface security mechanism and structural schematic diagram.
Fig. 2 is shown as the circuit structure diagram of the security control unit.
Fig. 3 is shown as the flow diagram of the method for the debugging interface security mechanism of the present invention.
Component label instructions
1 debugging port
2 microprocessors
201 debugging interfaces
3 storage units
4 security control units
401 first password registers
402 second password registers
403 input timing monitoring unit
404 comparators
5 external equipments
S1~S4 steps
Specific implementation mode
Illustrate that embodiments of the present invention, those skilled in the art can be by this specification below by way of specific specific example
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
It please refers to Fig.1 to Fig.3.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, package count when only display is with related component in the present invention rather than according to actual implementation in schema then
Mesh, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can be a kind of random change, and its
Assembly layout kenel may also be increasingly complex.
The present invention provides a kind of SOC chip and method with debugging interface security mechanism, referring to Fig. 1, being shown as this
The structural schematic diagram of SOC chip, including debugging port 1, microprocessor 2, the debugging interface 201 in microprocessor, storage unit 3
And security control unit 4.
Specifically, the storage unit 3 has secure access to password for prestoring debugging interface, by chip production supplier
It is responsible for maintenance.In the present embodiment, the storage unit 3 uses nonvolatile memory (Non-Volatile Memory, NVM),
After power supply is turned off, the data stored will not disappear.The debugging interface secure access password is 128 bits.
The security control unit 4 is connected between the debugging port 1 and the debugging interface 201, for the company of monitoring
It is connected to the input timing of the external equipment 5 of the debugging port 1；It, then will input password and the debugging when input timing is correct
Interface security accesses password and is compared；If comparison result is consistent, opens the debugging port 1 and arrive the debugging interface
Channel between 201；If comparison result is inconsistent, the debugging port 1 is closed to leading between the debugging interface 201
Road.
In the present embodiment, the external equipment includes but not limited to cd-rom recorder or host computer.
The present invention realizes the secure access of debugging interface using digital circuit framework, and port and internal debugging are debugged in physics
Security control unit is added between interface, by the debugging interface of SOC chip and chip interior debugging interface from physical connection
It is isolated.Only end will could be physically debugged when input includes the timing waveform signal of proper password on debugging port
Mouth and internal debugging orifice, to obtain the permission for accessing internal resource.
As an example, illustrating the circuit structure diagram of the security control unit 4 in Fig. 2 comprising first password is deposited
Device 401, the second password register 402, input timing detection unit 403 and comparator 404；Wherein：
The first password register 401 is connect with the storage unit 3, for being powered in chip and completing to reset operation
It receives afterwards and the temporary debugging interface from the storage unit 3 has secure access to password.
In the present embodiment, the debugging interface secure access password being stored in the storage unit 3 is only powered in chip
The system configuration stage could be written by hardware logic in particular register afterwards, and CPU and debugging interface can not access the storage list
Member 3 and the first password register 401.
The second password register 402 is used for the temporary input password from the external equipment 1.
The input timing monitoring unit 403 is connected with the debugging port 1 and the second password register 402, uses
It is connected to the input timing of the external equipment of the debugging port 1 in monitoring, and writes input password when input timing is correct
Enter the second password register 402.
Two input terminals of the comparator 404 respectively with 401 and second password register of the first password register
402 are connected, for the input password to be compared with debugging interface secure access password.
Specifically, the security control unit 4 is arranged to be included in the number of comparison in check password, when password compares
Number is more than preset times, then locks chip.
As an example, the preset times can be 1~10.In the present embodiment, the preset times are preferably 3, that is, are worked as
Password compares unsuccessfully more than 3 times, then chip locks automatically.
In the present embodiment, the security control unit 4 is further arranged to after chip locks, and no longer receives password ratio
To data, memory scrub instructions are only received.I.e. user can only can just re-fetch chip after executing memory scrub instructions
Control, and the user data being stored at this time in memory has been wiped free of, even if being illegally accessed what chip obtained
Only " white tiles ", to realize the purpose of user program in protection memory.
Fig. 3 is shown as the flow diagram of the method for modulation interface security mechanism of the present invention, the method includes：
Step S1：Chip is powered on and is completed after resetting operation, and it is single to be stored in advance in the storage by pure hardware logic
Debugging interface secure access password in member 3 is written in first password register, and the first password register can not be by institute
State the access of microprocessor 2；
Step S2：The monitoring of 4 moment of the security control unit is connected to the input of the external equipment 5 of the debugging port 1
Then the second password register is written when sequential is correct in input password by sequential；
Step S3：After the completion of inputting password acceptance, the security control unit 4 will input password and the debugging interface
Secure access password is compared；
Step S4：If comparison result is consistent, the debugging port 1 is opened to leading between the debugging interface 201
Road；If comparison result is inconsistent, the debugging port 1 to the channel between the debugging interface 201 is closed.
128 bit debugging interfaces secure access password is stored in specific by the method for the modulation interface security mechanism of the present invention
Nonvolatile memory in, only chip after the power is turned on the system configuration stage could by hardware logic be written specific cryptosystem register
Interior, CPU and debugging interface can not access the nonvolatile memory and password register, be more than unsuccessfully certain time when password compares
Number, then chip is locked, and after chip locking, security control unit no longer receives password comparison data, only receives non-volatile deposit
Reservoir erasing instruction, so as to effectively prevent illegally obtaining and changing chip interior resource and memory data.
In conclusion the SOC chip and method use number with memory inside data tamper-proof mechanisms of the present invention
Circuit framework realizes the secure access of debugging interface, is debugged in physics and adds security control between port and internal debugging interface
Unit is isolated from physical connection.It only could be when timing waveform signal comprising proper password in input on debugging port
Port and internal debugging orifice will be physically debugged, to obtain the permission for accessing internal resource.Security control unit is negative
It blames the verification of password and charges to the number of comparison, it is automatic to lock if it is more than 3 times to compare number.After chip locking, safety is controlled
Unit processed no longer receives password comparison data, only receives NVM memory erasing instruction.User can only wipe executing NVM memory
It is weighed except can just re-fetch chip controls after instruction, and the user data being stored at this time in NVM memory has been wiped free of, from
And realize the purpose of user data in protection NVM memory unit.So the present invention effectively overcome it is in the prior art various
Disadvantage and have high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology can all carry out modifications and changes to above-described embodiment without violating the spirit and scope of the present invention.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should by the present invention claim be covered.
Claims (10)
1. a kind of SOC chip and method with debugging interface security mechanism, which is characterized in that including：
Debug port；
Microprocessor, including debugging interface；
Storage unit has secure access to password for prestoring debugging interface；
Security control unit is connected between the debugging port and the debugging interface, and the debugging is connected to for monitoring
The input timing of the external equipment of port；When input timing is correct, then will input password and debugging interface secure access it is close
Code is compared；If comparison result is consistent, the debugging port to the channel between the debugging interface is opened；If than
It is inconsistent compared with result, then close the debugging port to the channel between the debugging interface.
2. SOC chip and method according to claim 1 with debugging interface security mechanism, it is characterised in that：It is described
Security control unit includes：
First password register is connect with the storage unit, for chip power on and complete reset operation after receive and it is temporary
Deposit the debugging interface secure access password from the storage unit；
Second password register, for the temporary input password from the external equipment；
Input timing monitoring unit is connected with the debugging port and the second password register, and institute is connected to for monitoring
The input timing of the external equipment of debugging port is stated, and second password is written into input password when input timing is correct and is posted
Storage；
Comparator, two input terminals of the comparator respectively with the first password register and the second password register phase
Even, for the input password to be compared with debugging interface secure access password.
3. SOC chip and method according to claim 2 with debugging interface security mechanism, it is characterised in that：Chip
It powers on and completes after resetting operation, the debugging interface secure access password from the storage unit is write by pure hardware logic
Enter to the first password register, the first password register can not be by the microprocessor access.
4. SOC chip and method according to claim 1 with debugging interface security mechanism, it is characterised in that：It is described
Security control unit is arranged to when password compares number be more than preset times, then locks chip.
5. SOC chip and method according to claim 4 with debugging interface security mechanism, it is characterised in that：It is described
Security control unit is arranged to after locking chip, no longer receives password comparison data, only receives memory scrub instructions.
6. SOC chip and method according to claim 4 with debugging interface security mechanism, it is characterised in that：It is described
Preset times are 1~10.
7. SOC chip and method according to claim 1 with debugging interface security mechanism, it is characterised in that：It is described
It is 128 bits that debugging interface, which has secure access to password,.
8. SOC chip and method according to claim 1 with debugging interface security mechanism, it is characterised in that：It is described
Storage unit is nonvolatile memory.
9. SOC chip and method according to claim 1 with debugging interface security mechanism, it is characterised in that：It is described
It is host computer or cd-rom recorder to deposit external equipment.
10. a kind of method of debugging interface security mechanism, which is characterized in that be applied to as described in claim 1-9 any one
The SOC chip with debugging interface security mechanism, the method includes：
Chip is powered on and is completed after resetting operation, is connect the debugging being stored in advance in the storage unit by pure hardware logic
Mouth secure access password is written in first password register, and the first password register can not be visited by the microprocessor
It asks；
Security control unit moment monitoring is connected to the input timing of the external equipment of the debugging port, when sequential just
Really, then the second password register is written into input password；
After the completion of inputting password acceptance, the security control unit will input password and have secure access to password with the debugging interface
It is compared；
If comparison result is consistent, the debugging port to the channel between the debugging interface is opened；If comparison result
It is inconsistent, then close the debugging port to the channel between the debugging interface.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611126402.1A CN108460296A (en) | 2016-12-09 | 2016-12-09 | SOC chip with debugging interface security mechanism and method |
| PCT/CN2017/085624 WO2018103275A1 (en) | 2016-12-09 | 2017-05-24 | Soc chip having debugging interface security mechanism, and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611126402.1A CN108460296A (en) | 2016-12-09 | 2016-12-09 | SOC chip with debugging interface security mechanism and method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108460296A true CN108460296A (en) | 2018-08-28 |
Family
ID=62490766
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611126402.1A Pending CN108460296A (en) | 2016-12-09 | 2016-12-09 | SOC chip with debugging interface security mechanism and method |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN108460296A (en) |
| WO (1) | WO2018103275A1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109977023A (en) * | 2019-04-03 | 2019-07-05 | 北京智芯微电子科技有限公司 | Support the cpu chip emulator of debugging permission control |
| CN112100691A (en) * | 2020-09-11 | 2020-12-18 | 浪潮(北京)电子信息产业有限公司 | Protection method and protection system of hardware debugging interface and programmable controller |
| CN112380119A (en) * | 2020-11-12 | 2021-02-19 | 上海东软载波微电子有限公司 | Chip, programming debugger, system and method for locking programming debugging entry |
| CN113918392A (en) * | 2020-07-10 | 2022-01-11 | 珠海格力电器股份有限公司 | Debugging protection system and debugging processing module |
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| CN112788382A (en) * | 2020-12-31 | 2021-05-11 | 成都长虹网络科技有限责任公司 | Set top box with safety debugging function |
| CN116756781B (en) * | 2023-08-23 | 2023-11-14 | 菁音核创科技(厦门)有限公司 | Encryption protection method, device and equipment for chip and storage medium |
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| CN109977023A (en) * | 2019-04-03 | 2019-07-05 | 北京智芯微电子科技有限公司 | Support the cpu chip emulator of debugging permission control |
| CN113918392A (en) * | 2020-07-10 | 2022-01-11 | 珠海格力电器股份有限公司 | Debugging protection system and debugging processing module |
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| CN112100691A (en) * | 2020-09-11 | 2020-12-18 | 浪潮(北京)电子信息产业有限公司 | Protection method and protection system of hardware debugging interface and programmable controller |
| CN112380119A (en) * | 2020-11-12 | 2021-02-19 | 上海东软载波微电子有限公司 | Chip, programming debugger, system and method for locking programming debugging entry |
| CN112380119B (en) * | 2020-11-12 | 2024-08-16 | 上海东软载波微电子有限公司 | Chip, programming debugger, system and method for locking programming debugging entrance |
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| WO2018103275A1 (en) | 2018-06-14 |
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