CN108399937A - Automatic repair circuit of memory - Google Patents

Abstract

The automatic repair circuit of the memory comprises a decoding circuit, a latch enabling circuit and a first latch circuit. The decoding circuit is used for comparing a first input address with a plurality of bad addresses so as to generate a control signal. The latch enable circuit is used for selectively generating a first enable signal at least according to the control signal. The first latch circuit is used for receiving the first input address and storing the first input address after receiving the first enabling signal. When the control signal indicates that the first input address is the same as one of the bad addresses, the latch enabling circuit prevents the enabling signal from being transmitted to the first latch circuit.

Description

Memory automatic repair circuit

technical field

The invention relates to a memory automatic repair circuit.

Background technique

The test of the memory element usually has two stages: bare die test (Chip Probing, CP) and final test (Final Test, FT). The former is to detect the crystal grains on the chip by needle testing, while the latter is to conduct an electrical test on the finished product after packaging. During testing, when a word line corresponding to an input address is found to be defective, a redundant word line is usually selected to replace the defective word line. When a word line corresponding to a specific address is found to be defective, there may be two redundant word lines corresponding to the specific address in two different test stages, and the problem of double selection occurs at this time. During the final testing phase, there may also be problems with repeated selections. Therefore, it is necessary to propose a circuit so that a specific address will only access a normal word line or a redundant word line.

Contents of the invention

An automatic memory repair circuit according to an embodiment of the present invention includes a decoding circuit, a latch enabling circuit and a first latch circuit. The decoding circuit is used for comparing a first input address with a plurality of bad addresses, so as to generate a control signal. The latch enable circuit is used for selectively generating a first enable signal at least according to the control signal. The first latch circuit is used for receiving the first input address, and storing the first input address after receiving the first enabling signal. When the control signal indicates that the first input address is the same as one of the defective addresses, the latch enable circuit prevents the enable signal from being transmitted to the first latch circuit.

Description of drawings

FIG. 1 shows a schematic block diagram of a memory automatic repair circuit according to a first embodiment of the present invention.

FIG. 2 shows a schematic block diagram of a memory automatic repair circuit according to a second embodiment of the present invention.

FIG. 3 shows a schematic block diagram of a memory automatic repair circuit according to a third embodiment of the present invention.

FIG. 4 shows a schematic block diagram of a memory automatic repair circuit according to a fourth embodiment of the present invention.

【Symbol Description】

100 memory automatic repair circuit

101 decoding circuit

102 Check circuit

103 Latch enabling circuit

104 Latch circuit

105 Type E fuse circuit

200 memory automatic repair circuit

201 decoding circuit

202 Check circuit

203 Latch enabling circuit

204_1, 204_2 Latch circuit

205_1, 205_2 Type E fuse circuit

206 comparison circuit

300 memory automatic repair circuit

301 decoding circuit

302 Check circuit

303 Latch enabling circuit

304_1, 304_2 Latch circuit

305_1, 305_2 Type E fuse circuit

306 comparison circuit

400 memory automatic repair circuit

401 decoding circuit

402 Check circuit

403 Latch enabling circuit

404_1, 404_2 Latch circuit

405_1, 405_2 Type E fuse circuit

406 comparison circuit

Detailed ways

Certain terms are used throughout the specification and appended claims to refer to particular elements. Those skilled in the art should understand that manufacturers may use different terms to refer to the same component. This description and the appended claims do not use the difference in name as a way to distinguish components, but use the difference in function of components as a criterion for distinguishing. "Includes" mentioned throughout the specification and appended claims is an open-ended term, so it should be interpreted as "including but not limited to". In addition, the term "coupled" herein includes any direct and indirect means of electrical connection. Therefore, if it is described that a first device is coupled to a second device, it means that the first device may be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connection means.

FIG. 1 shows a schematic block diagram of a memory automatic repair circuit according to a first embodiment of the present invention. Referring to FIG. 1 , the automatic memory repair circuit 100 includes a decoding circuit 101 , a checking circuit 102 , a latch enabling circuit 103 , a latch circuit 104 and an E-type fuse circuit 105 .

The decoding circuit 101 is used to receive an input address (such as the input address A1 in FIG. 1 ), and perform decoding according to whether the input address A1 is the same as one of a plurality of bad addresses FAm˜FAn. When the input address A1 is the same as one of the bad addresses FAm˜FAn, the decoding circuit 101 will select a redundant word line previously assigned to the bad address instead of a normal word line. The bad addresses FAm˜FAn are usually stored in a plurality of E-type fuse circuits. For the sake of brevity, only one E-type fuse circuit 105 is shown in this embodiment.

Referring to FIG. 1 , when the input address A1 is the same as one of the bad addresses FAm˜FAn, the decoding circuit 101 generates a control signal CS. The check circuit 102 receives and checks the input address A1 to determine whether the input address A1 corresponds to a defective word line. The checking circuit 102 generates a checking result IR to the latch enabling circuit 103 . In this embodiment, the checking circuit 102 is located in the memory automatic repairing circuit 100 . However, in other embodiments, the checking circuit 102 is located outside the automatic memory repair circuit 100 . The inspection circuit 102 can be in various types such as hardware, software or firmware.

The latch enable circuit 103 is used for selectively generating an enable signal EN1 according to the control signal CS and the check result IR. When the control signal CS is generated, it means that the input address A1 is the same as one of the bad addresses FAm˜FAn, and the latch enable circuit 103 prevents the enable signal EN1 from being transmitted to the latch circuit 104 . When the inspection result IR is generated, it means that the input address A1 does not correspond to a defective word line, and the latch enable circuit 103 prevents the enable signal EN1 from being transmitted to the latch circuit 104 . In other situations, the enable signal EN1 is transmitted from the latch enable circuit 103 to the latch circuit 104 . The latch circuit 104 is used for receiving the input address A1, and storing the input address A1 in the E-type fuse circuit 105 as a bad address FA1 after receiving the enable signal EN1. After the defective address FA1 is stored by the E-type fuse circuit 105, the decoding circuit 101 compares the input address A1 with the defective address FA1 after receiving the input address A1. Since they are the same, the decoding circuit 101 selects a redundancy word line RWL1 corresponding to the defect address FA1 to turn on.

To further illustrate, there are three situations when the automatic memory repair circuit 100 operates. In the first condition, when the input address A1 is different from one of the defective addresses FAm˜FAn, and the check result IR indicates that the input address A1 does not correspond to a defective word line, the latch The enable circuit 103 prevents the enable signal EN1 from being transmitted to the latch circuit 104 . Therefore, the latch circuit 104 will not store the input address A1 as a bad address. After decoding the input address A1, the decoding circuit 101 accesses a normal word line WL1 corresponding to the input address A1. In the second condition, when the input address A1 is the same as one of the bad addresses FAm˜FAn, the control signal CS will be generated to the latch enable circuit 103, so that the enable signal EN1 will not be transmitted to the latch circuit 104. Therefore, the latch circuit 104 will not store the input address A1. After the decoding circuit 101 receives the input address A1 and decodes it, it will select a redundant word line previously assigned to the bad address. In the third condition, when the input address A1 is different from one of the defective addresses FAm˜FAn, and the check result IR indicates that the input address A1 corresponds to a defective word line, the latch causes The enable circuit 103 generates the enable signal EN1 to the latch circuit 104 . Therefore, the latch circuit 104 stores the input address A1 into the E-type fuse circuit 105 as the bad address FA1. After receiving the input address A1, the decoding circuit 101 selects the redundancy word line RWL1 corresponding to the bad address FA1 to turn on.

FIG. 2 shows a schematic block diagram of a memory automatic repair circuit 200 according to a second embodiment of the present invention. Referring to FIG. 2, the memory automatic repair circuit 200 includes a decoding circuit 201, a checking circuit 202, a latch enable circuit 203, two latch circuits 204_1 and 204_2, two E-type fuse circuits 205_1 and 205_2, and a comparison circuit 206.

In this embodiment, the input address A1 has been stored in the latch circuit 204_1 according to the enable signal EN1, so the defect address FA1 is stored by the E-type fuse circuit 205_1. The decoding circuit 201 is used to receive an input address (such as the input address A2 in FIG. 2 ), and perform decoding according to whether the input address A2 is the same as one of a plurality of bad addresses FAm˜FAn. When the input address A2 is identical to one of the bad addresses FAm˜FAn, the decoding circuit 201 selects a redundant word line previously assigned to the bad address.

In addition, when the input address A2 is the same as one of the bad addresses FAm˜FAn, the decoding circuit 201 generates the control signal CS. The check circuit 202 receives and checks the input address A2 to determine whether the input address A2 corresponds to a defective word line. The checking circuit 202 generates the checking result IR to the latch enabling circuit 203 .

The comparison circuit 206 is used for comparing the input address A1 and the input address A2 to generate a comparison signal COM. The latch enable circuit 203 is used for selectively generating an enable signal EN2 according to the control signal CS, the check result IR and the comparison signal COM. When the control signal CS is generated, it means that the input address A2 is the same as one of the defective addresses FAm˜FAn, and the latch enable circuit 203 prevents the enable signal EN2 from being transmitted. When the inspection result IR is generated, it means that the input address A2 does not correspond to a defective word line, and the latch enable circuit 203 prevents the enable signal EN2 from being transmitted. When the comparison circuit 260 compares the input address A2 and finds that it is the same as the address A1 previously stored in the latch circuit 204_1 , the latch enable circuit 203 prevents the enable signal EN2 from being transmitted. In other situations, the enable signal EN2 is transmitted from the latch enable circuit 203 to the latch circuit 204_2 . After receiving the input address A2, the latch circuit 204_2 stores the input address A2 in the E-type fuse circuit 205_2 as a bad address FA2 according to the enable signal EN2. After the bad address FA2 is stored by the E-type fuse circuit 205_2, after the decoding circuit 201 receives the input address A2, if the input address A2 is the same as the bad address FA2, the decoding circuit 201 will select the bad address FA2 A corresponding redundant word line RWL2 is turned on.

To further illustrate, there are four situations when the automatic memory repair circuit 200 operates. In the first condition, when the comparison signal COM indicates that the input address A2 is different from the input address A1, the input address A2 is different from one of the bad addresses FAm˜FAn, and the check result IR indicates that the input address A2 is different from the input address A1. When the address A2 does not correspond to a defective word line, the latch enable circuit 203 prevents the enable signal EN2 from being transmitted to the latch circuit 204_2 . Therefore, the latch circuit 204_2 will not store the input address A2 as a bad address. After decoding the input address A2, the decoding circuit 201 accesses a normal word line WL2 corresponding to the input address A2. In the second condition, when the comparison signal COM indicates that the input address A2 is different from the input address A1, and the input address A2 is the same as one of the bad addresses FAm˜FAn, the control signal CS will be generated. to the latch enable circuit 203 so that the enable signal EN2 will not be transmitted to the latch circuit 204_2 . Therefore, the latch circuit 204_2 will not store the input address A2 as a bad address. After receiving the input address A2 and decoding it, the decoding circuit 201 will select a redundant word line previously assigned to the bad address. In the third condition, when the comparison signal COM indicates that the input address A2 is different from the input address A1, the input address A2 is different from one of the bad addresses FAm˜FAn, and the check result IR indicates the When the input address A2 corresponds to a defective word line, the latch enable circuit 203 generates the enable signal EN2 to the latch circuit 204_2 . Therefore, the latch circuit 204_2 stores the input address A2 into the E-type fuse circuit 205_2 as a defective address FA2. After receiving the input address A2, the decoding circuit 201 selects the redundancy word line RWL2 corresponding to the defect address FA2 to turn on. In the last condition, when the comparison signal COM indicates that the input address A2 is the same as the input address A1, the latch enable circuit 203 will not generate the enable signal EN2 to the latch circuit 204_2. Therefore, the latch circuit 204_2 will not store the input address A2. After receiving the input address A2, the decoding circuit 201 selects the redundant word line RWL1 corresponding to the defective address FA1 to turn on. According to the control signal CS and the comparison signal COM, the decoding circuit 201 will only access a normal word line or a redundant word line according to an input address.

FIG. 3 shows a schematic block diagram of a memory automatic repair circuit according to a third embodiment of the present invention. Referring to FIG. 3, the memory automatic repair circuit 300 includes a decoding circuit 301, a checking circuit 302, a latch enable circuit 303, two latch circuits 304_1 and 304_2, two E-type fuse circuits 305_1 and 305_2, and a comparison circuit 306. The operation principle of the inspection circuit 302, the latch enable circuit 303, the latch circuits 304_1 and 304_2, the E-type fuse circuits 305_1 and 305_2, and the comparison circuit 306 and the circuit of the embodiment shown in FIG. 2 The principle of operation is the same. The difference between the second embodiment and the third embodiment is that when the input address A1 is stored in the E-type fuse circuit 305_1 as the bad address FA1, the E-type fuse circuit 305_1 will generate a fuse signal B1 to the lock storage circuit 304_1. When the fuse signal B1 is received by the latch circuit 304_1 , the latch circuit 304_1 will no longer store any input address. Similarly, when the input address A2 is stored in the E-type fuse circuit 305_2 as the bad address FA2, the E-type fuse circuit 305_2 will generate a fuse signal B2 to the latch circuit 304_2. When the fuse signal B2 is received by the latch circuit 304_2 , the latch circuit 304_2 will no longer store any input address.

Then, after the power supply of the automatic memory repair circuit 300 is interrupted and then powered on again, if the E-type fuse circuits 305_1 and 305_2 have stored the defect addresses FA1 and FA2 through the fusing signals B1 and B2, the The latch circuits 304_1 and 304_2 will not store any input address, so as to avoid the problem of repeated selection.

FIG. 4 shows a schematic block diagram of a memory automatic repair circuit 400 according to a fourth embodiment of the present invention. Referring to FIG. 4, the memory automatic repair circuit 400 includes a decoding circuit 401, a checking circuit 402, a latch enable circuit 403, two latch circuits 404_1 and 404_2, two E-type fuse circuits 405_1 and 405_2, and a comparison circuit 406. The decoding circuit 401, the inspection circuit 402, the latch enabling circuit 403, the latch circuits 404_1 and 404_2, the E-type fuse circuits 405_1 and 405_2, and the comparison circuit 406 operate according to the principles of FIG. 2 and FIG. The circuit operation principle of the embodiment shown in 3 is the same. The difference between the fourth embodiment and the former is that the latch circuits 404_1 and 404_2 are used to store a specific address, such as the specific addresses SA1 and SA2 shown in FIG. 4 , but not to store the input addresses A1 and A2 . Referring to FIG. 4, after the latch enabling circuit 403 receives an active command (Active command) ACT and a test mode command RT1/RT2, the memory automatic repair circuit 400 enters a specific test mode. During a specific test mode, the latch enable circuit 403 ignores the inspection result IR and the comparison signal COM, and generates the enable signal EN1 in response to the test mode command RT1 and generates the enable signal EN1 in response to the test mode command RT2. The enable signal EN2. Then, when the enable signal EN1 is generated, the latch circuit 404_1 will store the address SA1 specified by the active command ACT, and when the enable signal EN2 is generated, the latch circuit 404_2 will store the address SA1 specified by the active command ACT. Address SA2, not the bad address.

In the above-mentioned embodiment, the address received by the decoding circuit, checking circuit, latch circuit and comparing circuit in Fig. 1 to Fig. 4 is a row address (row address), and the decoding circuit will only select a normal The word line or a redundant word line is turned on. However, the present invention should not be limited thereto. The decoding circuit, the checking circuit, the latch circuit and the comparison circuit can receive a column address, and the decoding circuit will access a normal bit line or turn on a redundant bit line according to the column address. Through the generation of the control signal CS, the comparison signal COM and the inspection result IR, the memory automatic repair circuit disclosed by the present invention can avoid the problem of repeated selection.

The technical content and technical features of the present invention have been disclosed above, but those skilled in the art may still make various substitutions and modifications based on the teaching and disclosure of the present invention without departing from the spirit of the present invention. Therefore, the protection scope of the present invention should not be limited to those disclosed in the embodiments, but should include various replacements and modifications that do not depart from the present invention, and are covered by the appended claims.

Claims (9)

1. A memory automatic repair circuit, comprising: A decoding circuit for comparing the first input address with a plurality of bad addresses, so as to generate a control signal; a latch enable circuit for selectively generating a first enable signal at least according to the control signal; and a first latch circuit, configured to receive the first input address, and store the first input address after receiving the first enabling signal; Wherein, when the control signal indicates that the first input address is the same as one of the defective addresses, the latch enabling circuit prevents the enabling signal from being transmitted to the first latch circuit. 2. The memory automatic repair circuit according to claim 1, further comprising: a comparison circuit, used to compare the first input address and the second input address, so as to generate a comparison signal to the latch enabling circuit; Wherein, when the comparison signal indicates that the first input address is different from the second input address, the latch enabling circuit generates a second enabling signal. 3. The memory automatic repair circuit according to claim 2, further comprising: The second latch circuit is used for receiving the second input address after the first input address is stored by the first latch circuit, and storing the first input address after the second enabling signal is received by the second latch circuit 2. Enter the address. 4. The memory automatic repair circuit according to claim 3, further comprising: A first E-type fuse circuit, wherein when the first enabling signal is received by the first latch circuit, the first latch circuit stores the first input address and transmits it to the first E-type fuse circuit for as the first bad address; and A second E-type fuse circuit, wherein when the second enable signal is received by the second latch circuit, the second latch circuit stores the second input address and sends it to the second E-type fuse circuit for as the second bad address. 5. The memory automatic repair circuit according to claim 4, wherein when the first E-type fuse circuit stores the first input address as the first defective address, the first E-type fuse circuit generates a first fusing signal to the first latch circuit, and when the second E-type fuse circuit stores the second input address as the second bad address, the second E-type fuse circuit generates a second fusing signal to the the second latch circuit. 6. The memory automatic repair circuit according to claim 5, wherein when the first latch circuit receives the first fusing signal, the first latch circuit will not store any input address, and when the second latch circuit After the circuit receives the second fusing signal, the second latch circuit will not store any input address. 7. The memory automatic repair circuit according to claim 2, wherein after the latch enabling circuit receives the active command and the test mode command, the latch enabling circuit ignores the comparison signal and generates the first enabling signal, And when the first enable signal is generated, the first latch circuit stores the third address specified by the active command. 8. The memory automatic repair circuit according to claim 1, wherein when the control signal indicates that the first input address is the same as one of the bad addresses, the first latch circuit will not store the first input address , and when the decoding circuit decodes the first input address, the decoding circuit accesses the one of the redundant word lines corresponding to the defective address. 9. The memory automatic repair circuit according to claim 1, further comprising: a checking circuit, configured to receive and check the first input address to determine whether the first input address corresponds to a defective word line; Wherein when the control signal indicates that one of the first input address and the defective address is different, and the checking circuit determines that the first input address does not correspond to the defective word line, the first latch circuit The first input address is not stored, and the decoding circuit decodes the first input address to access the normal word line corresponding to the first input address.