CN108321206A - LDMOS device and its manufacturing method - Google Patents

Abstract

The invention discloses an LDMOS device. The field oxygen in the drift region is an integrally formed structure composed of a main part and a bottom part, and a second epitaxial layer or a first epitaxial layer is formed on the surface of the first epitaxial layer in the formation region of the field oxygen in the drift region. Two polysilicon layers, the second epitaxial layer or the second polysilicon layer is oxidized to form the main part and the first epitaxial layer at the bottom of the main part is oxidized to form the bottom part; the bottom part will form a bird's beak to lower the gate The electric field intensity at the contact point between the dielectric layer and the field oxygen in the drift region; the main part can ensure the total thickness of the field oxygen in the drift region and reduce the thickness of the bottom part. The invention also discloses a manufacturing method of the LDMOS device. The invention can improve the breakdown voltage of the device, reduce the on-resistance and off-state leakage current of the device, and has the advantage of simple process.

Description

LDMOS device and its manufacturing method

technical field

The invention relates to the field of manufacturing semiconductor integrated circuits, in particular to an LDMOS device; the invention also relates to a method for manufacturing the LDMOS device.

Background technique

Double-diffused metal oxide semiconductor field effect transistor (Double-diffused MOS) is widely used in power management circuits due to its characteristics of withstand voltage, high current drive capability and extremely low power consumption. DMOS includes vertical double-diffused metal oxide semiconductor field effect transistor (VDMOS) and LDMOS (LDMOS). In LDMOS devices, on-resistance is an important indicator. In the BCD process, although LDMOS and CMOS are integrated in the same chip, due to the requirements of high withstand voltage, low characteristic resistance and on-resistance, the conditions of LDMOS in the base device region and drift region are shared with the existing process conditions of CMOS. Under the premise, there are contradictions and compromises between the on-resistance and the breakdown voltage (BV), which often cannot meet the requirements of the switching tube application. The on-resistance is usually represented by the characteristic resistance (Rsp). Therefore, in order to obtain the same off-state breakdown voltage (offBV), Rsp should be reduced as much as possible to improve the competitiveness of the product.

As shown in Figure 1, it is a schematic structural diagram of the first existing LDMOS device; taking an N-type device as an example, the existing first LDMOS device includes:

An N-type first epitaxial layer 2, a P-type drift region 4 and an N-type body region 5 are formed in a selected region of the first epitaxial layer 2; the drift region 4 and the body region 5 are laterally There is distance in isolation.

A P-type heavily doped first buried layer 1 is formed at the bottom of the first epitaxial layer 2; the first buried layer 1 is formed on the surface of the semiconductor substrate. Usually, the semiconductor substrate is a silicon substrate, and the first epitaxial layer 2 is a silicon epitaxial layer.

In selected regions of the drift region 4 is formed a drift region field oxygen 3 .

Formed on the surface of the body region 5 is a gate structure formed by stacking a gate dielectric layer such as a gate oxide layer 6 and a polysilicon gate 7, and the surface of the body region 5 covered by the polysilicon gate 7 is used to form a channel .

The second side of the gate dielectric layer 6 is in contact with the first side of the drift region field oxide 3 , and the second side of the polysilicon gate 7 extends to the surface of the drift region field oxide 3 .

The source region 8 a is formed on the surface of the body region 5 , and the second side of the source region 8 a is self-aligned with the first side of the polysilicon gate 7 .

A drain region 8b is formed in the drift region 4 and a first side of the drain region 8b is self-aligned with a second side of the drift region field 3 .

An N-type heavily doped body lead-out region 9 is also formed on the surface of the body region 5 , and the body lead-out region 9 is in contact with the side surface of the first side of the source region 8 a. The body lead-out region 9 and the source region 8a will be connected to the source formed by the front metal layer through the same contact hole.

The drain region 8b is connected to the drain composed of the front metal layer through the contact hole, and the polysilicon gate 7 is connected to the gate composed of the front metal layer through the contact hole.

In FIG. 1, the field oxygen 3 in the drift region is a structure recessed to a certain depth in the first epitaxial layer 2. Generally, the field oxygen 3 in the drift region adopts a shallow trench isolation process (STI) or a local oxidation process (LOCOS )form. Wherein, the step of forming the field oxygen 3 in the drift region by using the STI process includes: a) etching silicon to form a shallow trench, b) performing thermal oxidation to form an oxide layer on the surface of the shallow trench, c) oxidizing the trench layer filling, d) forming the drift region field oxygen 3 by chemical mechanical polishing. In the LOCOS process, the field oxygen 3 in the drift region is formed by oxidizing local silicon. In the STI and LOCOS processes, the thicker the field oxygen 3 in the drift region is, the more favorable it is to increase the OffBV and reduce the off-state leakage current (Ioff) of the device, but the less favorable it is to reduce the Rsp of the device. On the contrary, the thinner the field oxygen 3 in the drift region is, the more favorable it is to reduce Rsp, but it will lead to a decrease in OffBV and an increase in leakage Ioff.

Fig. 2 is a schematic structural diagram of the existing second LDMOS device; the difference from the existing first structure shown in Fig. 1 is that the existing second LDMOS device has the following characteristics:

In FIG. 2 , the field oxygen 3 a in the drift region is formed above the surface of the first epitaxial layer 2 , and the field oxygen 3 a in the drift region is formed by oxide layer deposition and photolithography. The disadvantage of the existing second type of LDMOS is that when the withstand voltage is high, a high electric field is easily formed at the junction of the gate dielectric layer 6 and the field oxygen 3a in the drift region, so breakdown often occurs at the junction. In order to avoid this phenomenon, the lateral dimension of the device has to be enlarged. However, enlarging the lateral dimension will cause the Rsp of the device to increase rapidly.

Contents of the invention

The technical problem to be solved by the present invention is to provide an LDMOS device, which can increase the breakdown voltage of the device and reduce the on-resistance and off-state leakage current of the device. Therefore, the present invention also provides a manufacturing method of the LDMOS device.

In order to solve the above technical problems, the LDMOS device provided by the present invention includes:

A first epitaxial layer of the second conductivity type, a drift region of the first conductivity type and a body region of the second conductivity type are formed in a selected region of the first epitaxial layer; the drift region and the body region laterally There is a distance between contact or isolation.

Oxygen from the drift region is formed in selected regions of the drift region.

A gate structure formed by stacking a gate dielectric layer and a polysilicon gate is formed on the surface of the body region, and the surface of the body region covered by the polysilicon gate is used to form a channel.

The second side of the gate dielectric layer is in contact with the first side of the drift region field oxygen, and the second side of the polysilicon gate extends to the surface of the drift region field oxygen.

A source region is formed on the surface of the body region and the second side of the source region is self-aligned with the first side of the polysilicon gate.

A drain region is formed in the drift region and a first side of the drain region is self-aligned with a second side of the drift region field.

The drift region field oxygen is an integrally formed structure formed by superimposing a main part and a bottom part, and a second epitaxial layer or a second polycrystalline layer is formed on the surface of the first epitaxial layer in the formation region of the drift region field oxygen A silicon layer, the main body part is formed by performing local field oxidation on the second epitaxial layer or the second polysilicon layer, and the bottom part is simultaneously formed on the bottom of the second epitaxial layer or the second polysilicon layer The first epitaxial layer is formed by local field oxidation.

The bottom portion forms a bird's beak on the first side of the drift region field oxygen so that the gate dielectric layer contacts the bird's beak on the first side of the drift region field oxygen, lowering the gate dielectric layer and the gate dielectric layer. The electric field strength at the field-oxygen contact in the drift region.

The main part is used to reduce the thickness of the bottom part under the condition that the total thickness of the drift region field oxygen remains constant, thereby reducing the distance between the bottom of the drift region field oxygen and the surface of the first epitaxial layer. The distance between them is used to reduce the on-resistance of the device.

A further improvement is that a first buried layer heavily doped with the first conductivity type is formed at the bottom of the first epitaxial layer; and the first buried layer is formed on the surface of the semiconductor substrate.

A further improvement is that the semiconductor substrate is a silicon substrate, and the first epitaxial layer is a silicon epitaxial layer.

A further improvement is that the consumption of the first epitaxial layer by the local field oxidation process corresponding to the bottom part is

A further improvement is that the thickness of the main body part is

A further improvement is that the gate dielectric layer is a gate oxide layer.

A further improvement is that a heavily doped body lead-out region of the second conductivity type is further formed on the surface of the body region, and the body lead-out region is in contact with the side surface of the first side of the source region.

A further improvement is that the LDMOS is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the LDMOS is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type .

In order to solve the problems of the technologies described above, the manufacturing method of the LDMOS device provided by the invention comprises the following steps:

Step 1, providing a first epitaxial layer of a second conductivity type.

Step 2, sequentially forming a first oxide layer and a second nitride layer on the surface of the first epitaxial layer, defining the formation area of the field oxygen in the drift region by photolithography, and forming the formation area of the field oxygen in the drift region The second nitride layer and the first oxide layer are removed to form a first opening exposing the surface of the first epitaxial layer.

Step 3, filling the first opening with the second epitaxial layer or the second polysilicon layer; performing local field oxidation to oxidize the second epitaxial layer or the second polysilicon layer to form the drift region field oxygen The local field oxidation simultaneously oxidizes the second epitaxial layer or the first epitaxial layer at the bottom of the second polysilicon layer to form the bottom part of the drift region field oxygen.

Step 4: Form a drift region in a selected region of the first epitaxial layer by using a first conductivity type ion implantation process, and the field oxygen of the drift region is located in a part of the drift region.

Step 5, forming a gate dielectric layer and a first polysilicon layer in sequence.

Step 6: Perform the first photolithography to define the side position of the first side of the polysilicon gate, and sequentially etch the first polysilicon layer and the gate dielectric layer to form the first side of the polysilicon gate and expose the surface of the first epitaxial layer outside the side surfaces of the first side of the polysilicon gate.

Step 7: Forming a body region by using a second conductivity type ion implantation process, the body region is located in the first epitaxial layer outside the side surface of the first side of the polysilicon gate, and the body region extends to The bottom of the first side of the polysilicon gate, the surface of the body covered by the polysilicon gate is used to form a channel.

Step 8: Perform a second photolithography to define the side position of the second side of the polysilicon gate, etch the first polysilicon layer to form the side surface of the second side of the polysilicon gate and form the polysilicon gate A gate structure is formed by stacking the gate dielectric layer and the polysilicon gate; the second side of the gate dielectric layer is in contact with the first side of the drift region field oxygen, and the second side of the polysilicon gate extends to the surface of the drift region field oxygen.

Step 9: Perform heavy doping ion implantation of the first conductivity type to form a source region and a drain region at the same time, the source region is formed on the surface of the body region and the second side of the source region is self-aligned with the first side of the polysilicon gate alignment; a drain region is formed in the drift region and a first side of the drain region and a second side of the drift region field oxygen are self-aligned.

The bottom portion forms a bird's beak on the first side of the drift region field oxygen so that the gate dielectric layer contacts the bird's beak on the first side of the drift region field oxygen, lowering the gate dielectric layer and the gate dielectric layer. The electric field strength at the field-oxygen contact in the drift region.

The main part is used to reduce the thickness of the bottom part under the condition that the total thickness of the drift region field oxygen remains constant, thereby reducing the distance between the bottom of the drift region field oxygen and the surface of the first epitaxial layer. The distance between them is used to reduce the on-resistance of the device.

A further improvement is that in step 1, a first buried layer heavily doped with the first conductivity type is formed at the bottom of the first epitaxial layer; the first buried layer is formed on the surface of the semiconductor substrate.

A further improvement is that the semiconductor substrate is a silicon substrate, and the first epitaxial layer is a silicon epitaxial layer.

A further improvement is that the consumption of the first epitaxial layer by the local field oxidation process corresponding to the bottom part in step 2 is

A further improvement is that when the second epitaxial layer or the second polysilicon layer in step 3 is completely an epitaxial layer, the second epitaxial layer or the second polysilicon layer is filled in the said epitaxial layer through a selective epitaxial process. In the first opening.

When the second epitaxial layer or the second polysilicon layer in step 3 includes polysilicon, after the deposition of the second epitaxial layer or the second polysilicon layer, the second epitaxial layer or the second polysilicon layer The silicon layer fills the first opening and extends to the surface of the second nitride layer outside the first opening, and uses the second nitride layer as a stop layer to perform a chemical mechanical polishing process to remove the first The second epitaxial layer or the second polysilicon layer outside the opening is ground away and the second epitaxial layer or the second polysilicon layer is ground to be level with the top surface of the first opening.

A further improvement is that the thickness of the main body part is

A further improvement is to include steps after step nine:

Step 10: Implanting heavily doped ions of the second conductivity type to form a body lead-out region on the surface of the body region, the body lead-out region is in contact with the side surface of the first side of the source region.

The present invention makes a targeted design on the structure of the field oxygen in the drift region, mainly because the field oxygen in the drift region is an integrally formed structure in the present invention and is improved on the basis of the existing local field oxide layer. The field oxygen in the drift region is not completely formed by oxidizing the first epitaxial layer corresponding to the drift region, but the present invention first forms the second epitaxial layer or the second epitaxial layer on the surface of the first epitaxial layer in the formation region of the drift region field oxygen. The polysilicon layer is then formed by local field oxidation, the main part of the field oxygen in the drift region formed in this way is located on the first epitaxial layer and is formed by oxidation of the second epitaxial layer or the second polysilicon layer; and the second epitaxial layer or the second polysilicon layer is oxidized; An epitaxial layer is located at the bottom of the second epitaxial layer or the second polysilicon layer, so the oxidation rate of the first epitaxial layer is slow and only a thinner thickness is oxidized to form the bottom part of the drift region field oxygen, through the bottom The superposition of part and main part makes the present invention have following overall effect:

The bottom portion of the present invention has a bird’s beak structure. In the case of the bottom portion, the gate dielectric layer will be in contact with the bird’s beak on the first side of the drift region field oxygen, and the gate dielectric layer and the drift region field can be reduced through the bird’s beak The electric field strength at the contact of oxygen can increase the breakdown voltage of the device, that is, compared with the existing structure shown in Figure 2, the present invention has an additional bottom part with a bird's beak, which can improve the breakdown voltage of the device.

In addition, the thickness of the field oxygen in the drift region of the present invention is mainly determined by the main body, and the thicker field oxygen in the drift region can reduce the off-state leakage current of the device.

In addition, the oxidation rate of the bottom part of the present invention is slower and has a thinner thickness, that is, the thickness of the part where the field oxygen in the drift region is recessed into the first epitaxial layer is smaller, compared with the existing structure shown in FIG. 1 , the present invention can shorten the path through which the current in the drift region passes, and can reduce the on-resistance of the device.

In addition, the main part and the bottom part of the field oxygen in the drift region of the present invention are formed simultaneously by a local field oxidation process, and it is only necessary to increase the formation of the second epitaxial layer or the second polysilicon layer in the local area of the field oxidation before the field oxidation. Only steps are required, so the process of the present invention is simple and the cost is low.

Therefore, the present invention can increase the breakdown voltage of the device, can reduce the on-resistance and the off-state leakage current of the device under the condition that the breakdown voltage is guaranteed, and has the advantage of simple process.

Description of drawings

Below in conjunction with accompanying drawing and specific embodiment the present invention will be described in further detail:

FIG. 1 is a structural schematic diagram of the first existing LDMOS device;

FIG. 2 is a schematic structural diagram of a second existing LDMOS device;

3 is a schematic structural diagram of an LDMOS device according to an embodiment of the present invention;

4A-4E are schematic diagrams of the device structure in each step of the manufacturing method of the LDMOS device according to the embodiment of the present invention.

Detailed ways

As shown in Figure 3, it is a schematic structural diagram of an LDMOS device according to an embodiment of the present invention; the LDMOS device according to an embodiment of the present invention includes:

The first epitaxial layer 102 of the second conductivity type, in the selected region of the first epitaxial layer 102, a drift region 104 of the first conductivity type and a body region 105 of the second conductivity type are formed; the drift region 104 and the body region 105 of the second conductivity type are formed; The body regions 105 are laterally separated by a distance. In other embodiments, it can also be: the drift region 104 is in lateral contact with the body region 105 .

In the embodiment of the present invention, a first buried layer 101 heavily doped with the first conductivity type is formed at the bottom of the first epitaxial layer 102; the first buried layer 101 is formed on the surface of the semiconductor substrate. Preferably, the semiconductor substrate is a silicon substrate, and the first epitaxial layer 102 is a silicon epitaxial layer.

A drift region field oxygen 103 is formed in selected regions of the drift region 104 .

On the surface of the body region 105 is formed a gate structure formed by stacking a gate dielectric layer 106 and a polysilicon gate 107 , and the surface of the body region 105 covered by the polysilicon gate 107 is used to form a channel. Preferably, the gate dielectric layer 106 is a gate oxide layer.

The second side of the gate dielectric layer 106 is in contact with the first side of the drift region field oxide 103 , and the second side of the polysilicon gate 107 extends to the surface of the drift region field oxide 103 .

The source region 108a is formed on the surface of the body region 105, and the second side of the source region 108a is self-aligned with the first side of the polysilicon gate 107.

A drain region 108b is formed in the drift region 104 and a first side of the drain region 108b is self-aligned with a second side of the drift region field 103 .

A heavily doped body lead-out region 109 of the second conductivity type is further formed on the surface of the body region 105 , and the body lead-out region 109 is in contact with the side surface of the first side of the source region 108 a. The body lead-out region 109 and the source region 108a will be connected to the source formed by the front metal layer through the same contact hole.

The drain region 108b is connected to the drain formed by the front metal layer through the contact hole, and the polysilicon gate 107 is connected to the gate formed by the front metal layer through the contact hole.

The drift region field oxygen 103 is an integrally formed structure formed by superimposing the main body part 1031 and the bottom part 1032, and a second epitaxial layer is formed on the surface of the first epitaxial layer 102 in the formation region of the drift region field oxygen 103 Or the second polysilicon layer 112, the main part 1031 is formed by performing local field oxidation on the second epitaxial layer or the second polysilicon layer 112, and the bottom part 1032 is formed by simultaneously oxidizing the second epitaxial layer or second polysilicon layer 112 at the bottom of the first epitaxial layer 102 is formed by local field oxidation. Please refer to FIG. 4B for the second epitaxial layer or the second polysilicon layer 112 .

The bottom part 1032 forms a bird's beak on the first side of the drift region field oxygen 103 so that the gate dielectric layer 106 is in contact with the bird's beak on the first side of the drift region field oxygen 103, lowering the gate dielectric The electric field strength at the contact between the layer 106 and the field oxygen 103 in the drift region.

The main part 1031 is used to reduce the thickness of the bottom part 1032 under the condition that the total thickness of the drift region oxygen 103 remains unchanged, thereby reducing the bottom of the drift region oxygen 103 and the first The distance between the surfaces of the epitaxial layer 102 is used to reduce the on-resistance of the device.

Preferably, the consumption of the first epitaxial layer 102 by the local field oxidation process corresponding to the bottom portion 1032 is That is, the thickness of the bottom portion 1032 can be obtained by consuming the first epitaxial layer 102 .

The thickness of the bottom portion 1032 in the embodiment of the present invention is greatly reduced compared with the field oxygen separating the active region in other regions, and is a miniature version of the local field oxygen (Mini-LOCOS).

The thickness of the main body portion 1031 is

In the embodiment of the present invention, the LDMOS is an N-type device, the first conductivity type is N-type, the second conductivity type is P-type, and the semiconductor substrate is P-type doped. In other embodiments, it can also be: the LDMOS is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

The LDMOS device in the embodiment of the present invention can be integrated in a BCD process. It can be seen from the above that, different from the existing technology, the field oxygen 103 in the drift region is a structure composed of upper and lower parts. The bottom part 1032 forms a very shallow Mini-LOCOS by performing partial thermal oxidation on the surface of the first epitaxial layer 102, and the Mini-LOCOS at both ends will form a small and short bird's beak, short bird's beak. The mouth does not affect the thickness of the gate dielectric layer 106 . Shallow Mini-LOCOS can shorten the current path, that is, significantly reduce the Rsp of the device, and the bird's beak of LOCOS can significantly reduce the electric field at the junction of the gate dielectric layer 106 and the field oxygen 103 in the drift region under the high withstand voltage state, thus improving the device performance. breakdown voltage. The main part 1031 is disposed on the bottom part 1032 and is also formed by local field oxygen, that is, local thermal oxidation, but the main part 1031 is not formed by oxidation of the first epitaxial layer 102, but formed on the surface of the first epitaxial layer 102 The oxidation of the second epitaxial layer or the second polysilicon layer 112 is formed, and the purpose of the main body part 1031 is to thicken the thickness of the field oxygen 103 in the entire drift region to improve the off-state breakdown voltage (OffBV) of the device, wherein The thickness of the field oxygen region formed by Mini-LOCOS should not be too thick, too thick will significantly increase Rsp, but the thickness of the field oxygen 103 in the drift region should not be too thin, as too thin will reduce OffBV, so the embodiment of the present invention adopts the setting of the main part 1031 The thicker field oxygen 103 in the drift region can be formed under the condition that the bottom portion 1032 is thinner. As mentioned above, the function of Mini-LOCOS is to form a bird's beak at the connection between the gate dielectric layer 106 and the field oxygen 103 in the drift region to reduce the electric field at the connection and improve the breakdown voltage (BV) of the device. Compared with the bird's beak Because the bird's beak formed by the existing LOCOS is small and short, the device structure of the embodiment of the present invention can reduce the Rsp of the device and improve the performance of the device; the simulation can indeed prove that the embodiment of the present invention can ensure the premise of the breakdown voltage Lower the Rsp of the device.

As shown in FIG. 4A to FIG. 4E, it is a schematic diagram of the device structure in each step of the manufacturing method of the LDMOS device according to the embodiment of the present invention. The manufacturing method of the LDMOS device according to the embodiment of the present invention includes the following steps:

Step 1, as shown in FIG. 4A , providing a first epitaxial layer 102 of the second conductivity type.

In the method of the embodiment of the present invention, a first buried layer 101 heavily doped with the first conductivity type is formed at the bottom of the first epitaxial layer 102; the first buried layer 101 is formed on the surface of the semiconductor substrate.

Preferably, the semiconductor substrate is a silicon substrate, and the first epitaxial layer 102 is a silicon epitaxial layer.

Step 2, as shown in FIG. 4A, a first oxide layer 110 and a second nitride layer 111 are sequentially formed on the surface of the first epitaxial layer 102, and the formation area of the drift region field oxygen 103 is defined by photolithography, and the The second nitride layer 111 and the first oxide layer 110 in the formation region of the drift region field oxide 103 are removed to form a first opening exposing the surface of the first epitaxial layer 102 .

Step 3, as shown in FIG. 4B , filling the first opening with the second epitaxial layer or the second polysilicon layer 112 .

In the embodiment of the present invention, the second epitaxial layer or the second polysilicon layer 112 is only composed of polysilicon, which needs to include the following sub-steps:

As shown in FIG. 4A, the second epitaxial layer or the second polysilicon layer 112 is deposited and formed, and the second epitaxial layer or the second polysilicon layer 112 fills the first opening and extends to the The surface of the second nitride layer 111 outside the first opening.

As shown in FIG. 4B, the second epitaxial layer or the second polysilicon layer 112 outside the first opening is polished away by a chemical mechanical polishing process using the second nitride layer 111 as a stop layer, and the The second epitaxial layer or the second polysilicon layer 112 is polished to be even with the top surface of the first opening.

In other embodiments, it can also be: the second epitaxial layer or the second polysilicon layer 112 in step 3 is completely composed of an epitaxial layer, as shown in FIG. layer or the second polysilicon layer 112 is filled in the first opening; since the selective epitaxial layer will not form the second epitaxial layer on the surface of the second silicon nitride layer 111 outside the first opening layer or the second polysilicon layer 112, so no CMP process is required.

As shown in FIG. 4C, the second epitaxial layer or the second polysilicon layer 112 is oxidized to form the main part 1031 of the field oxygen 103 in the drift region by performing local field oxidation, and the local field oxidation simultaneously oxidizes the first The second epitaxial layer or the first epitaxial layer 102 at the bottom of the second polysilicon layer 112 is oxidized to form the bottom portion 1032 of the drift region field oxygen 103 . The local field oxidation is to thermally oxidize a selected local area, and a step of removing the second nitride layer 111 is also included after the formation of the local field oxidation.

In the method of the embodiment of the present invention, the consumption of the first epitaxial layer 102 by the local field oxidation process corresponding to the bottom part 1032 is The thickness of the formed main body portion 1031 is

Step 4, as shown in FIG. 4D, a drift region 104 is formed in a selected region of the first epitaxial layer 102 by using a first conductivity type ion implantation process, and the field oxygen 103 of the drift region is located in a part of the drift region 104 in the area. The first oxide layer 110 remains during the ion implantation process of the drift region 104 , and the first oxide layer 110 is removed after the implantation is completed.

Step 5, as shown in FIG. 4E , forming a gate dielectric layer 106 and a first polysilicon layer 107 in sequence. Preferably, the gate dielectric layer 106 is a gate oxide layer formed by a thermal oxidation process.

Step 6, as shown in FIG. 4E , perform the first photolithography to define the side position of the first side of the polysilicon gate 107, and sequentially etch the first polysilicon layer 107 and the gate dielectric layer 106 to form The side surface of the first side of the polysilicon gate 107 exposes the surface of the first epitaxial layer 102 outside the side surface of the first side of the polysilicon gate 107 .

Step 7. As shown in FIG. 4E , a second conductivity type ion implantation process is used to form a body region 105, and the body region 105 is located in the first epitaxial layer 102 outside the side surface of the first side of the polysilicon gate 107 The body region 105 extends to the bottom of the first side of the polysilicon gate 107 after annealing, and the surface of the body region 105 covered by the polysilicon gate 107 is used to form a channel.

Preferably, the ion implantation of the body region 105 needs to be implanted with a photoresist, and the photoresist is the photoresist that defines the side position of the first side of the polysilicon gate 107 in step six.

Step 8. As shown in FIG. 3 , perform a second photolithography to define the side position of the second side of the polysilicon gate 107, and etch the first polysilicon layer 107 to form the second side of the polysilicon gate 107. side and form the polysilicon gate 107, the gate structure is formed by overlapping the gate dielectric layer 106 and the polysilicon gate 107; the second side of the gate dielectric layer 106 and the first side of the drift region field oxygen 103 The second side of the polysilicon gate 107 extends to the surface of the field oxide 103 in the drift region.

Step 9, as shown in FIG. 3 , perform heavy doping ion implantation of the first conductivity type to form a source region 108a and a drain region 108b at the same time, the source region 108a is formed on the surface of the body region 105 and the second side of the source region 108a Self-aligned with the first side of the polysilicon gate 107; the drain region 108b is formed in the drift region 104 and the first side of the drain region 108b is self-aligned with the second side of the drift region field oxygen 103 .

Preferably, the body regions 105 of adjacent LDMOS devices are shared, and two adjacent source regions of the same body region 105 are used when performing ion implantation to form the source region 108a and the drain region 108b The areas between 108a are blocked with photoresist. The drain regions 108b of adjacent LDMOS devices are shared, and both sides of the drain region 108b are the drift region field oxygen 103, and the position of the drain region 108b is directly determined by the drift region field oxygen 103 on both sides. Self-alignment definition.

The bottom part 1032 forms a bird's beak on the first side of the drift region field oxygen 103 so that the gate dielectric layer 106 is in contact with the bird's beak on the first side of the drift region field oxygen 103, lowering the gate dielectric The electric field strength at the contact between the layer 106 and the field oxygen 103 in the drift region.

The main part 1031 is used to reduce the thickness of the bottom part 1032 under the condition that the total thickness of the drift region oxygen 103 remains unchanged, thereby reducing the bottom of the drift region oxygen 103 and the first The distance between the surfaces of the epitaxial layer 102 is used to reduce the on-resistance of the device.

Step 10: Implanting heavily doped ions of the second conductivity type to form a body lead-out region 109 on the surface of the body region 105, the body lead-out region 109 is in contact with the side surface of the first side of the source region 108a. When performing the body lead-out region 109 , the formation region of the body lead-out region 109 needs to be opened first, and other regions are blocked by photoresist, and then implanted to form the body lead-out region 109 .

In the method of the embodiment of the present invention, the LDMOS is an N-type device, the first conductivity type is N-type, the second conductivity type is P-type, and the semiconductor substrate is P-type doped. In other embodiments, it can also be: the LDMOS is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

The present invention has been described in detail through specific examples above, but these do not constitute a limitation to the present invention. Without departing from the principle of the present invention, those skilled in the art can also make many modifications and improvements, which should also be regarded as the protection scope of the present invention.

Claims (15)

1. A LDMOS device, characterized in that, comprising: A first epitaxial layer of the second conductivity type, a drift region of the first conductivity type and a body region of the second conductivity type are formed in a selected region of the first epitaxial layer; the drift region and the body region laterally Contact or isolation distance; forming drift region field oxygen in selected regions of said drift region; A gate structure formed by stacking a gate dielectric layer and a polysilicon gate is formed on the surface of the body region, and the surface of the body region covered by the polysilicon gate is used to form a channel; The second side of the gate dielectric layer is in contact with the first side of the drift region field oxygen, and the second side of the polysilicon gate extends to the surface of the drift region field oxygen; a source region is formed on the surface of the body region and the second side of the source region is self-aligned with the first side of the polysilicon gate; a drain region is formed in the drift region and a first side of the drain region is self-aligned with a second side of the drift region field; The drift region field oxygen is an integrally formed structure formed by superimposing a main part and a bottom part, and a second epitaxial layer or a second polycrystalline layer is formed on the surface of the first epitaxial layer in the formation region of the drift region field oxygen A silicon layer, the main body part is formed by performing local field oxidation on the second epitaxial layer or the second polysilicon layer, and the bottom part is simultaneously formed on the bottom of the second epitaxial layer or the second polysilicon layer The first epitaxial layer is formed by local field oxidation; The bottom portion forms a bird's beak on the first side of the drift region field oxygen so that the gate dielectric layer contacts the bird's beak on the first side of the drift region field oxygen, lowering the gate dielectric layer and the gate dielectric layer. The electric field strength at the field-oxygen contact in the drift region; The main part is used to reduce the thickness of the bottom part under the condition that the total thickness of the drift region field oxygen remains constant, thereby reducing the distance between the bottom of the drift region field oxygen and the surface of the first epitaxial layer. The distance between them is used to reduce the on-resistance of the device. 2. The LDMOS device according to claim 1, characterized in that: a first buried layer heavily doped with the first conductivity type is formed at the bottom of the first epitaxial layer; the first buried layer is formed on the semiconductor substrate bottom surface. 3. The LDMOS device according to claim 2, wherein the semiconductor substrate is a silicon substrate, and the first epitaxial layer is a silicon epitaxial layer. 4. The LDMOS device according to claim 1, wherein the consumption of the first epitaxial layer by the local field oxidation process corresponding to the bottom portion is 5. The LDMOS device according to claim 1, wherein the thickness of the main body is 6. The LDMOS device according to claim 1, wherein the gate dielectric layer is a gate oxide layer. 7. The LDMOS device according to claim 1, characterized in that: a heavily doped body lead-out region of the second conductivity type is further formed on the surface of the body region, and the second conductive region of the body lead-out region and the source region The sides on one side are in contact. 8. The LDMOS device according to any one of claims 1 to 7, wherein the LDMOS is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the LDMOS is P-type type device, the first conductivity type is P-type, and the second conductivity type is N-type. 9. A method for manufacturing an LDMOS device, comprising the steps of: Step 1, providing a first epitaxial layer of a second conductivity type; Step 2, sequentially forming a first oxide layer and a second nitride layer on the surface of the first epitaxial layer, defining the formation area of the field oxygen in the drift region by photolithography, and forming the formation area of the field oxygen in the drift region removing the second nitride layer and the first oxide layer to form a first opening exposing the surface of the first epitaxial layer; Step 3, filling the first opening with the second epitaxial layer or the second polysilicon layer; performing local field oxidation to oxidize the second epitaxial layer or the second polysilicon layer to form the drift region field oxygen The main part of the local field oxidation simultaneously oxidizes the second epitaxial layer or the first epitaxial layer at the bottom of the second polysilicon layer to form the bottom part of the drift region field oxygen; Step 4, using a first conductivity type ion implantation process to form a drift region in a selected region of the first epitaxial layer, and the field oxygen of the drift region is located in a part of the drift region; Step 5, sequentially forming a gate dielectric layer and a first polysilicon layer; Step 6: Perform the first photolithography to define the side position of the first side of the polysilicon gate, and sequentially etch the first polysilicon layer and the gate dielectric layer to form the first side of the polysilicon gate and exposing the surface of the first epitaxial layer outside the side surfaces of the first side of the polysilicon gate; Step 7: Forming a body region by using a second conductivity type ion implantation process, the body region is located in the first epitaxial layer outside the side surface of the first side of the polysilicon gate, and the body region extends to the bottom of the first side of the polysilicon gate, the surface of the body covered by the polysilicon gate is used to form a channel; Step 8: Perform a second photolithography to define the side position of the second side of the polysilicon gate, etch the first polysilicon layer to form the side surface of the second side of the polysilicon gate and form the polysilicon gate A gate structure is formed by stacking the gate dielectric layer and the polysilicon gate; the second side of the gate dielectric layer is in contact with the first side of the drift region field oxygen, and the second side of the polysilicon gate extends onto the surface of the drift region field oxygen; Step 9: Perform heavy doping ion implantation of the first conductivity type to form a source region and a drain region at the same time, the source region is formed on the surface of the body region and the second side of the source region is self-aligned with the first side of the polysilicon gate alignment; a drain region is formed in the drift region and a first side of the drain region and a second side of the drift region field oxygen are self-aligned; The bottom portion forms a bird's beak on the first side of the drift region field oxygen so that the gate dielectric layer contacts the bird's beak on the first side of the drift region field oxygen, lowering the gate dielectric layer and the gate dielectric layer. The electric field strength at the field-oxygen contact in the drift region; The main part is used to reduce the thickness of the bottom part under the condition that the total thickness of the drift region field oxygen remains constant, thereby reducing the distance between the bottom of the drift region field oxygen and the surface of the first epitaxial layer. The distance between them is used to reduce the on-resistance of the device. 10. The method for manufacturing an LDMOS device according to claim 9, characterized in that: in step 1, a first buried layer heavily doped with the first conductivity type is formed at the bottom of the first epitaxial layer; The buried layer is formed on the surface of the semiconductor substrate. 11. The method for manufacturing an LDMOS device according to claim 10, wherein the semiconductor substrate is a silicon substrate, and the first epitaxial layer is a silicon epitaxial layer. 12. The method for manufacturing an LDMOS device according to claim 9, wherein the consumption of the first epitaxial layer by the local field oxidation process corresponding to the bottom portion in step 2 is 13. The method for manufacturing an LDMOS device according to claim 9, wherein when the second epitaxial layer or the second polysilicon layer is completely an epitaxial layer in step 3, the first epitaxial layer is formed by a selective epitaxial process. Two epitaxial layers or a second polysilicon layer are filled in the first opening; When the second epitaxial layer or the second polysilicon layer in step 3 includes polysilicon, after the deposition of the second epitaxial layer or the second polysilicon layer, the second epitaxial layer or the second polysilicon layer The silicon layer fills the first opening and extends to the surface of the second nitride layer outside the first opening, and uses the second nitride layer as a stop layer to perform a chemical mechanical polishing process to remove the first The second epitaxial layer or the second polysilicon layer outside the opening is ground away and the second epitaxial layer or the second polysilicon layer is ground to be level with the top surface of the first opening. 14. The method for manufacturing an LDMOS device as claimed in claim 9, wherein the thickness of the main body part is 15. The manufacturing method of LDMOS device as claimed in claim 9, is characterized in that: after step 9, also comprises the step: Step 10: Implanting heavily doped ions of the second conductivity type to form a body lead-out region on the surface of the body region, the body lead-out region is in contact with the side surface of the first side of the source region.