CN111785617A - Manufacturing method of LDMOS - Google Patents

Abstract

The invention discloses a method for manufacturing an LDMOS, comprising: step 1, providing a semiconductor substrate with a second conductivity type, and using a first mask to perform the first photolithography to open the formation area of the USTI; step 2, performing Ion implantation of the first conductivity type to form a first implantation region; Step 3, etch the semiconductor substrate to form an ultra-shallow trench; Step 4, use a second mask to perform a second photolithography to open the STI formation region ; Step 5, etch the semiconductor substrate to form a shallow trench, the depth of the shallow trench is greater than the formation depth of the ultra-shallow trench; Step 6, fill the field oxide layer in the ultra-shallow trench and the shallow trench; Step 7 . Performing heat treatment on the first implanted region to diffuse the first implanted region to form a drift region, and the drift region covers the USTI. The invention can make the USTI and the ion implantation in the drift region share the same mask, so the cost can be reduced and the performance of the device can be maintained at the same time.

Description

Manufacturing method of LDMOS

technical field

The present invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a method for manufacturing an LDMOS.

Background technique

DMOS is widely used in power management chips due to its high voltage resistance, high current drive capability and extremely low power consumption. In LDMOS devices, on-resistance is an important indicator. The process of bipolar junction transistor (BJT), CMOS device and DMOS device on the same chip is BCD process. In BCD process, although LDMOS and CMOS are integrated in the same chip, due to high breakdown voltage There are contradictions and compromises between (Vbv) and low characteristic on-resistance (Specific on-Resistance, Rsp), which often cannot meet the requirements of switching tube applications. In order to obtain high breakdown voltage and low Rsp, it is usually necessary to add additional masks, but this increases the manufacturing cost of the process platform, so how to reduce the number of masks will help reduce costs and improve product competitiveness.

In the existing LDMOS device structure, in order to increase the on-current of the device, that is, reduce the on-resistance of the device, an additional ultra-shallow trench isolation (Ultra Shallow Trench Isolation, USTI) field oxide with a shallower depth is introduced on part of the drift region. Layer (Field Plate oxide) structure, but also can improve the electric field distribution at the gate edge. However, in this structure, in order to introduce the USTI, an additional mask is required, which will increase the manufacturing cost of the process platform; in addition, the implantation of the drift region of the existing device is formed after the completion of the USTI structure, and an additional mask is also required to carry out injection. FIG. 1 is a schematic structural diagram of an existing LDMOS; taking an N-type LDMOS device as an example, an N-type buried layer 2 is formed on a P-type semiconductor substrate such as a silicon substrate 1, and a P-type buried layer 2 is formed on the N-type buried layer 2. Epitaxial layer 3. Shallow Trench Isolation (STI) 105 is formed on the semiconductor substrate 1 , the STI5 isolates the active region, and the LDMOS is formed in the active region.

A P-type doped body region 8 is formed on the P-type epitaxial layer 3 , and the body region 8 is usually composed of a P-type well.

An N-type doped drift region 6 and an N-type doped buffer zone 7 are also formed on the P-type epitaxial layer 3 .

The gate structure is formed by stacking a gate dielectric layer such as a gate oxide layer 9 and a polysilicon gate 10 , and spacers 11 are formed on both sides of the gate structure.

A USTI4 is also formed in the drift region 6, and the polysilicon gate 10 extends onto the USTI4.

An N+ doped source region 12a is formed in the body region 8 and is self-aligned with the first side of the polysilicon gate 10, and an N+ doped drain region 12b is formed in the drift region 6 outside the second side of the USTI 4. The buffer 7 and the drift region 6 overlap and the overlapping region of the two surrounds the second side of the USTI 4 and the drain region 12b.

A P+ doped body extraction region 13 is also formed in the body region 8 .

In the structure shown in FIG. 1, since it is necessary to introduce USTI4 with a depth lower than STI5 in the drift region 6, it is necessary to use a different mask from STI5 to define the formation region of USTI4, and the drift region 6 and STI5 also need to use different reticle to define. Although the increased USTI4 can reduce the on-resistance of the device and improve the electric field distribution at the edge of the gate structure, it needs to add a mask and the corresponding lithography process, so the process cost will increase, which will reduce product competition. force.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present invention is to provide a manufacturing method of LDMOS, which can reduce the cost and keep the performance of the device at the same time.

In order to solve the above technical problems, in the LDMOS manufacturing method provided by the present invention, the LDMOS is formed in the active region isolated by the STI, and the field oxide layer in the drift region of the LDMOS adopts the USTI, and the depth of the USTI is smaller than that of the STI. The formation steps of the LDMOS include:

Step 1, providing a semiconductor substrate with a second conductivity type, and using a first mask to perform a first photolithography to open the formation region of the USTI.

Step 2: Perform ion implantation of a first conductivity type in the formation region of the USTI opened by the first lithography to form a first implantation region.

Step 3: Etching the semiconductor substrate in the formation region of the USTI opened by the first lithography to form an ultra-shallow trench, and the depth of the first implantation region is greater than the depth of the ultra-shallow trench. depth.

Step 4, using a second mask to perform a second photolithography to open the formation area of the STI.

Step 5: Etching the semiconductor substrate in the STI formation region opened by the second lithography to form a shallow trench, the depth of the shallow trench is greater than the formation depth of the ultra-shallow trench .

Step 6: Fill the ultra-shallow trench and the shallow trench with a field oxide layer, the USTI is composed of the field oxide layer filled in the ultra-shallow trench, and the USTI is formed by the field oxide layer filled in the shallow trench. The field oxide layer constitutes the STI.

In step 7, heat treatment is performed on the first implanted region to diffuse the first implanted region to form the drift region, and the drift region covers the USTI.

A further improvement is that the semiconductor substrate includes a silicon substrate.

A further improvement is that, in step 1, a hard mask layer is used in the first lithography, including the following sub-steps:

A hard mask layer is formed on the surface of the semiconductor substrate.

A first layer of photoresist is coated on the surface of the hard mask layer.

Exposure and development are performed to form a first layer of photoresist pattern, and the first layer of photoresist pattern opens the formation area of the USTI and covers the formation area of the USTI.

A further improvement is that in step 2, the first conductivity type ion implantation in the first implantation region is performed using the first layer of photoresist pattern as a mask, and the first conductivity type ion implantation in the first implantation region is performed. through the hard mask layer.

A further improvement is that step 3 includes the following sub-steps:

The hard mask layer is etched using the first photoresist pattern as a mask to form a first hard mask layer pattern.

The first layer of photoresist pattern is removed.

The ultra-shallow trench is formed by etching the semiconductor substrate using the first hard mask layer pattern as a mask.

A further improvement is that, after the formation of the ultra-shallow trench in step 3 and before the second photolithography process in step 4, further comprising forming a first liner oxide layer on the inner surface of the ultra-shallow trench. step.

A further improvement is that in step 4, the second lithography includes the following sub-steps:

A second layer of photoresist is coated, and the second layer of photoresist covers the surface of the hard mask layer and the first pad oxide layer.

Exposure and development are performed to form a second layer of photoresist pattern, and the second layer of photoresist pattern opens the formation area of the STI and covers the formation area of the STI.

A further improvement is that step 5 includes the following sub-steps:

The hard mask layer is etched using the second layer of photoresist pattern as a mask, and the second hard mask layer is composed of the first pad oxide layer and the etched hard mask layer. Quality mask layer pattern.

The second layer of photoresist pattern is removed.

The shallow trench is formed by etching the semiconductor substrate using the second hard mask layer pattern as a mask.

A further improvement is that the hard mask layer is formed by stacking the first oxide layer and the second silicon nitride layer.

In step 6, the field oxide layer further extends to the ultra-shallow trench and the surface of the hard mask layer outside the shallow trench.

After the growth of the field oxide layer is completed, the method further includes:

Chemical mechanical polishing using the second silicon nitride layer as a stop layer is performed.

After that, the hard mask layer is removed.

A further improvement is that, after forming the shallow trench in step 5 and before forming the field oxide layer in step 6, a step of forming a second pad oxide layer on the inner surface of the shallow trench is further included.

A further improvement is that the heat treatment in Step 7 is implemented by using the thermal process used in the manufacturing steps of the LDMOS after Step 2.

A further improvement is to also include steps:

Step 8, performing ion implantation of the second conductivity type to form a body region, and the body region and the drift region are in lateral contact and have a space.

Step 9, forming a gate structure, the gate structure is formed by stacking a gate dielectric layer and a polysilicon gate; the first side of the gate structure is located on the body region, and the second side of the gate structure extends onto the USTI.

Step 10. Perform source-drain implantation of the first conductivity type to form a source region and a drain region, the source region is located on the surface of the body region and is self-aligned with the first side of the gate structure, and the drain region is located on the side of the USTI the surface of the drift region outside the second side.

A further improvement is that, in step 9, the gate dielectric layer is formed by a thermal oxidation process;

The polysilicon gate is formed by polysilicon deposition and etching processes.

After the polysilicon gate is etched, the method further includes the step of forming spacers on the side surfaces of the polysilicon gate.

A further improvement is that, in step 8, before or after forming the body region, it further includes a step of performing ion implantation of the first conductivity type to form a second implantation region, and the second implantation region and the drift region overlap, and the second implantation region covers the second side of the USTI, the drain region is formed on the surface of the overlapping region of the second implantation region and the drift region, and the second implantation region serves as a buffer Area.

A further improvement is that, in step ten, the method further includes performing source-drain implantation of the second conductivity type to form a body lead-out region, and the body lead-out region is located on the surface of the body region.

The invention enables the ultra-shallow trench of the USTI in the drift region and the ion implantation of the drift region to share the same mask definition, thereby saving a mask and the corresponding photolithography process, thereby reducing the cost; at the same time, the device can be The properties such as breakdown voltage and on-resistance are maintained, which ultimately improves the competitiveness of the product.

Description of drawings

The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments:

FIG. 1 is a schematic structural diagram of an existing LDMOS;

2 is a flowchart of a method for manufacturing an LDMOS according to a first embodiment of the present invention;

3A-3G are device structure diagrams in each step in the manufacturing method of the LDMOS according to the first embodiment of the present invention;

FIG. 4 is a structural diagram of a device formed by a method for manufacturing an LDMOS according to a second embodiment of the present invention.

Detailed ways

The manufacturing method of the LDMOS of the first embodiment of the present invention:

As shown in FIG. 2, it is a flow chart of the manufacturing method of the LDMOS according to the first embodiment of the present invention; as shown in FIG. 3A to FIG. 3G, it is the device structure diagram in each step of the manufacturing method of the LDMOS according to the first embodiment of the present invention; In the manufacturing method of the LDMOS according to the first embodiment of the present invention, the LDMOS is formed in the active region isolated by the STI105, the field oxide layer 156 in the drift region 106 of the LDMOS adopts the USTI104, and the depth of the USTI104 is smaller than that of the STI105. The forming steps include:

Step 1. As shown in FIG. 3A , a semiconductor substrate 101 having a second conductivity type is provided, and a first reticle is used to perform a first photolithography to open the formation region of the USTI 104 .

In the first embodiment of the present invention, the semiconductor substrate 101 includes a silicon substrate.

Preferably, a buried layer 102 doped with a first conductivity type is further formed in the semiconductor substrate 101 , and an epitaxial layer 103 doped with a second conductivity type is also formed on the surface of the buried layer 103 .

The hard mask layer is used in the first lithography, including the following sub-steps:

A hard mask layer is formed on the surface of the semiconductor substrate 101 . Preferably, the hard mask layer is formed by stacking the first oxide layer 151 and the second silicon nitride layer 152 .

A first layer of photoresist 153 is coated on the surface of the hard mask layer.

Exposure and development are performed to form a pattern of a first layer of photoresist 153, and the pattern of the first layer of photoresist 153 opens the formation area of the USTI 104 and covers the formation area of the USTI 104.

Step 2: As shown in FIG. 3A , ion implantation of the first conductivity type is performed in the formation region of the USTI 104 opened by the first lithography to form the first implantation region 106 .

In the first embodiment of the present invention, ion implantation of the first conductivity type of the first implantation region 106 is performed using the pattern of the first layer of photoresist 153 as a mask, and the first conductivity type of the first implantation region 106 is Ions are implanted through the hard mask layer.

It can be seen that the first implanted region 106 has not been thermally diffused, so the size of the lateral area of the first implanted region 106 is the same as the size of the open region of the pattern of the first layer of photoresist 153 .

Step 3: As shown in FIG. 3B , etch the semiconductor substrate 101 in the formation region of the USTI 104 opened by the first lithography to form an ultra-shallow trench, the depth of the first implantation region 106 greater than the depth of the ultra-shallow trench.

In the first embodiment of the present invention, step 3 includes the following sub-steps:

The hard mask layer is etched using the first layer of photoresist 153 pattern as a mask to form a first hard mask layer pattern.

The pattern of the first layer of photoresist 153 is removed.

The ultra-shallow trench is formed by etching the semiconductor substrate 101 using the first hard mask layer pattern as a mask.

Step 4, using a second mask to perform a second photolithography to open the formation area of the STI105.

As shown in FIG. 3C , in the first embodiment of the present invention, after the ultra-shallow trench is formed in step 3 and before the second photolithography process in step 4, the inner side of the ultra-shallow trench is further included. The step of forming the first pad oxide layer 154 on the surface.

In step 4, the second lithography includes the following steps:

As shown in FIG. 3C , a second layer of photoresist 153 a is coated, and the second layer of photoresist 153 a covers the surface of the hard mask layer and the first pad oxide layer 154 .

Exposure and development are performed to form a pattern of a second layer of photoresist 153a, and the pattern of the second layer of photoresist 153a opens the formation area of the STI 105 and covers the formation area of the STI 105.

Step 5: Etching the semiconductor substrate 101 of the STI 105 formation area opened by the second lithography to form a shallow trench, the depth of the shallow trench is greater than the formation of the ultra-shallow trench depth.

In the first embodiment of the present invention, step 5 includes the following sub-steps:

As shown in FIG. 3D, the hard mask layer is etched using the pattern of the second layer of photoresist 153a as a mask, and the first pad oxide layer 154 and the etched hard mask layer are etched. The quality mask layer forms a second hard mask layer pattern.

The pattern of the second layer of photoresist 153a is removed.

The shallow trenches are formed by etching the semiconductor substrate 101 using the second hard mask layer pattern as a mask.

Step 6. As shown in FIG. 3E, fill the ultra-shallow trench and the shallow trench with a field oxide layer 156, and the USTI 104 is composed of the field oxide layer 156 filled in the ultra-shallow trench, and is composed of The field oxide layer 156 filled in the shallow trench constitutes the STI 105 .

As shown in FIG. 3D , in the first embodiment of the present invention, after forming the shallow trench in step 5 and before forming the field oxide layer 156 in step 6, it further includes forming a second surface on the inner surface of the shallow trench. Pad oxide layer 155 step.

In step 6, as shown in FIG. 3E, the field oxide layer 156 also extends to the ultra-shallow trench and the surface of the hard mask layer outside the shallow trench.

After the growth of the field oxide layer 156 is completed, it further includes:

As shown in FIG. 3F , chemical mechanical polishing is performed using the second silicon nitride layer 152 as a stop layer.

After that, the hard mask layer is removed.

In step 7, heat treatment is performed on the first implanted region 106 to diffuse the first implanted region 106 to form the drift region 106 , and the drift region 106 covers the USTI 104 . In FIG. 3F , both the drift region and the first implant region are indicated by reference numeral 106 .

In the first embodiment of the present invention, the heat treatment in step 7 is implemented by the thermal process used in the manufacturing steps of the LDMOS after step 2. For example, the thermal process for realizing the heat treatment includes: a thermal process in the process of forming the first pad oxide layer 154 and the second pad oxide layer 155 , and a thermal process in the process of forming the field oxide layer 156 . As well as the subsequent processes such as the formation of the gate dielectric layer 109 and the thermal process in the annealing and activation of each doped region, the area of the first implanted region 6 will be correspondingly enlarged after each thermal process. That is, in the first embodiment of the present invention, a separate thermal process is not required to process the first implantation region 6, but the thermal treatment of the first implantation region 6 is automatically realized in the thermal process of the subsequent process. In other embodiments, the first implanted region 6 can also be treated by a separate thermal process.

Also includes steps:

Step 8. As shown in FIG. 3F , ion implantation of the second conductivity type is performed to form a body region 108 , and the body region 108 and the drift region 106 are in lateral contact and spaced apart.

In the first embodiment of the present invention, before or after the formation of the body region 108 , the step of performing ion implantation of the first conductivity type to form the second implantation region 107 , the second implantation region 107 and the drift region 106 is further included. The second implanted region 107 covers the second side of the USTI 104, and the subsequent drain region 112b is formed on the surface of the overlapping region of the second implanted region 107 and the drift region 106, so The second injection region 107 is used as a buffer.

Step 9. As shown in FIG. 3G , a gate structure is formed, and the gate structure is formed by stacking the gate dielectric layer 109 and the polysilicon gate 110 ; the first side of the gate structure is located on the body region 108 , so The second side of the gate structure extends onto the USTI 104 .

In the first embodiment of the present invention, in step 9, the gate dielectric layer 109 is formed by a thermal oxidation process;

The polysilicon gate 110 is formed by polysilicon deposition and etching processes.

After the polysilicon gate 110 is etched, the step of forming sidewall spacers 111 on the side surface of the polysilicon gate 110 is further included.

The area of the drift region 106 covered by the polysilicon gate 110 is an accumulation region.

Step 10. Perform source-drain implantation of the first conductivity type to form a source region 112a and a drain region 112b. The source region 112a is located on the surface of the body region 108 and is self-aligned with the first side of the gate structure. Region 112b is located on the surface of the drift region 106 outside the second side of the USTI 104 .

In the first embodiment of the present invention, source-drain implantation of the second conductivity type is further included to form a body lead-out region 113 , and the body lead-out region 113 is located on the surface of the body region 108 .

The first embodiment of the present invention enables the ultra-shallow trench of the USTI 104 in the drift region 106 and the ion implantation in the drift region 106 to share the same reticle definition, thereby saving a reticle and the corresponding photolithography process, thus reducing the cost ; while maintaining device performance such as breakdown voltage and on-resistance.

In the method according to the first embodiment of the present invention, the LDMOS is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the LDMOS can also be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

The manufacturing method of the LDMOS of the second embodiment of the present invention:

As shown in FIG. 4, it is a device structure diagram formed by the manufacturing method of the LDMOS according to the second embodiment of the present invention. The difference between the manufacturing method of the LDMOS according to the second embodiment of the present invention and the manufacturing method of the LDMOS according to the first embodiment of the present invention is:

In step 8 corresponding to FIG. 3F , the formation process of the second implantation region 107 is not performed.

The present invention has been described in detail above through specific embodiments, but these are not intended to limit the present invention. Without departing from the principles of the present invention, those skilled in the art can also make many modifications and improvements, which should also be regarded as the protection scope of the present invention.

Claims (15)

1. a manufacturing method of LDMOS, it is characterized in that, LDMOS is formed in the active region isolated by STI, and the field oxide layer in the drift region of described LDMOS adopts USTI, and the depth of USTI is less than STI, and the depth of described LDMOS is less than STI. The forming steps include: Step 1, providing a semiconductor substrate with the second conductivity type, and using a first mask to perform the first photolithography to open the formation area of the USTI; Step 2, performing ion implantation of a first conductivity type in the formation region of the USTI opened by the first lithography to form a first implantation region; Step 3: Etching the semiconductor substrate in the formation region of the USTI opened by the first lithography to form an ultra-shallow trench, and the depth of the first implantation region is greater than the depth of the ultra-shallow trench. depth; Step 4, using a second reticle to perform a second photolithography to open the formation area of the STI; Step 5: Etching the semiconductor substrate in the STI formation region opened by the second lithography to form a shallow trench, the depth of the shallow trench is greater than the formation depth of the ultra-shallow trench ; Step 6: Fill the ultra-shallow trench and the shallow trench with a field oxide layer, the USTI is composed of the field oxide layer filled in the ultra-shallow trench, and the USTI is formed by the field oxide layer filled in the shallow trench. The field oxide layer constitutes the STI; In step 7, heat treatment is performed on the first implanted region to diffuse the first implanted region to form the drift region, and the drift region covers the USTI. 2. The method for manufacturing an LDMOS according to claim 1, wherein the semiconductor substrate comprises a silicon substrate. 3. The manufacturing method of LDMOS according to claim 1, characterized in that: in step 1, a hard mask layer is used in the first lithography, comprising the following steps: forming a hard mask layer on the surface of the semiconductor substrate; coating a first layer of photoresist on the surface of the hard mask layer; Exposure and development are performed to form a first layer of photoresist pattern, and the first layer of photoresist pattern opens the formation area of the USTI and covers the formation area of the USTI. 4. The manufacturing method of LDMOS according to claim 3, wherein in step 2, the first conductivity type ion implantation of the first implantation region is performed by using the first layer of photoresist pattern as a mask, so that the The first conductivity type ions of the first implant region are implanted through the hard mask layer. 5. the manufacture method of LDMOS according to claim 4, is characterized in that: step 3 comprises following substep: etching the hard mask layer by using the first layer of photoresist pattern as a mask to form a first hard mask layer pattern; removing the first layer of photoresist pattern; The ultra-shallow trench is formed by etching the semiconductor substrate using the first hard mask layer pattern as a mask. 6 . The method for manufacturing LDMOS according to claim 5 , wherein: after the formation of the ultra-shallow trench in step 3 and before the second photolithography process in step 4, further comprising: The step of forming a first pad oxide layer on the inner surface of the groove. 7. the manufacturing method of LDMOS according to claim 6, is characterized in that: in step 4, described second photolithography comprises the following steps: coating a second layer of photoresist, the second layer of photoresist covers the surface of the hard mask layer and the first pad oxide layer; Exposure and development are performed to form a second layer of photoresist pattern, and the second layer of photoresist pattern opens the formation area of the STI and covers the formation area of the STI. 8. the manufacture method of LDMOS according to claim 7, is characterized in that: step 5 comprises following steps: The hard mask layer is etched using the second layer of photoresist pattern as a mask, and the second hard mask layer is composed of the first pad oxide layer and the etched hard mask layer. Quality mask layer pattern; removing the photoresist pattern of the second layer; The shallow trench is formed by etching the semiconductor substrate using the second hard mask layer pattern as a mask. 9. The manufacturing method of LDMOS according to claim 8, wherein the hard mask layer is formed by stacking a first oxide layer and a second silicon nitride layer; In step 6, the field oxide layer also extends to the ultra-shallow trench and the surface of the hard mask layer outside the shallow trench; After the growth of the field oxide layer is completed, the method further includes: performing chemical mechanical polishing with the second silicon nitride layer as a stop layer; After that, the hard mask layer is removed. 10 . The method for manufacturing LDMOS according to claim 8 , wherein after forming the shallow trench in step 5 and before forming the field oxide layer in step 6, further comprising forming on the inner surface of the shallow trench. 11 . the step of a second pad oxide layer. 11 . The method for manufacturing an LDMOS according to claim 1 , wherein the heat treatment in step 7 is implemented by using the thermal process used in the manufacturing step of the LDMOS after step 2 . 12 . 12. the manufacture method of LDMOS according to claim 1, is characterized in that, also comprises the step: Step 8, performing ion implantation of the second conductivity type to form a body region, and the body region and the drift region are in lateral contact or have a space; Step 9, forming a gate structure, the gate structure is formed by stacking a gate dielectric layer and a polysilicon gate; the first side of the gate structure is located on the body region, and the second side of the gate structure extends onto said USTI; Step 10. Perform source-drain implantation of the first conductivity type to form a source region and a drain region, the source region is located on the surface of the body region and is self-aligned with the first side of the gate structure, and the drain region is located on the side of the USTI the surface of the drift region outside the second side. 13. The method for manufacturing an LDMOS according to claim 12, wherein in step 9, the gate dielectric layer is formed by a thermal oxidation process; The polysilicon gate is formed by polysilicon deposition and etching processes; After the polysilicon gate is etched, the method further includes the step of forming spacers on the side surfaces of the polysilicon gate. 14. The method for manufacturing an LDMOS according to claim 12, wherein in step 8, before or after forming the body region, it further comprises the step of performing ion implantation of the first conductivity type to form a second implantation region, the A second implanted region overlaps the drift region, and the second implanted region wraps the second side of the USTI, and the drain region is formed at the overlap of the second implanted region and the drift region the surface of the region, the second implanted region acts as a buffer. 15 . The method for manufacturing an LDMOS according to claim 12 , wherein in step ten, it further comprises performing source-drain implantation of the second conductivity type to form a body lead-out region, and the body lead-out region is located on the surface of the body region. 16 .

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