CN108321086B

CN108321086B - High frequency device and method of making the same

Info

Publication number: CN108321086B
Application number: CN201710749904.8A
Authority: CN
Inventors: 翁銘彦; 高克毅; 何家齐; 筱崎勉; 王程麒; 李宜音
Original assignee: Innolux Display Corp
Current assignee: Innolux Corp
Priority date: 2017-01-16
Filing date: 2017-08-28
Publication date: 2021-09-07
Anticipated expiration: 2037-08-28
Also published as: CN108321503B; CN108321513B; CN108321086A; CN108321513A; CN108321503A; CN108321148A

Abstract

The present disclosure provides a method for manufacturing a high-frequency device, including: providing a substrate; forming a conductive material on the substrate; leaving a first time interval; , wherein the thickness of the conductive layer ranges from 0.9 μm to 10 μm; and the patterned conductive layer. The present disclosure also provides a high frequency device.

Description

High frequency device and method for manufacturing the same

Technical Field

The present disclosure relates to a high frequency device and a method for manufacturing the same, and more particularly, to a conductive layer of a high frequency device and a method for manufacturing the same.

Background

In the fabrication of conventional displays, the deposition of a conductive layer on a substrate by Physical Vapor Deposition (PVD), for example, requires only a few thousand angstroms

That is, the requirement of the product is met, but for high frequency devices (e.g., antennas), it is necessary to provide a conductive layer with a relatively large thickness on the substrate. However, for a substrate with a general thickness, a conductive layer (e.g., greater than 1 micrometer (μm)) with a relatively large thickness is plated thereon, which requires a long-time continuous deposition, and during the process, a large amount of heat energy is released by atomic impact and accumulated on the conductive layer and the substrate, so that the conductive layer or the substrate is warped (warped) due to an increase in structural stress, and the substrate plated with a conductive material (e.g., metal) cannot smoothly enter an equipment machine for subsequent process operations, for example,photolithography, cleaning processes, etc., make the fabrication of thick conductive layer devices difficult.

Therefore, a conductive coating structure capable of effectively maintaining a flat state is developed, which can reduce the warpage problem generated when a thick conductive layer is fabricated on a substrate.

Disclosure of Invention

In some embodiments, the present disclosure provides a method of manufacturing a high frequency device, including: providing a substrate; forming a conductive material on the substrate; standing for a first time interval; sequentially repeating the step of forming the conductive material and the step of standing at least once to form a conductive layer, wherein the thickness of the conductive layer ranges from 0.9 μm to 10 μm; and patterning the conductive layer.

In other embodiments, the present disclosure provides a method of manufacturing a high frequency device, including: providing a substrate; forming a conductive layer on the substrate, wherein the temperature of the substrate ranges from 10 ℃ to 130 ℃; and patterning the conductive layer.

In still other embodiments, a high frequency device structure includes: a substrate; the patterned conducting layer is positioned on the substrate and has a thickness; wherein the patterned conductive layer has a first location adjacent to the substrate, the patterned conductive layer has a second location remote from the substrate, the first location is located at the thickness from the substrate 1/5, the second location is located at the thickness from the substrate 4/5, and the grain size at the first location is larger than the grain size at the second location.

Drawings

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:

FIG. 1 is a flow chart of steps in a method of fabricating a high frequency device according to some embodiments of the present disclosure;

FIGS. 2A-2E are cross-sectional views of a high frequency device at various stages in the fabrication process, according to some embodiments of the present disclosure;

FIG. 3 is a flow chart of steps in a method of fabricating a high frequency device according to some embodiments of the present disclosure;

FIGS. 4A-4C are cross-sectional views of a high frequency device at various stages in the fabrication process, according to some embodiments of the present disclosure;

FIGS. 5A-5D are schematic diagrams of images of a patterned conductive layer of a high frequency device structure viewed using a Scanning Electron Microscope (SEM), according to some embodiments of the present disclosure;

figures 6A-6E are X-ray diffraction analysis diagrams of conductive layers according to some embodiments of the present disclosure.

Element numbering in the figures:

10 a method for manufacturing a high-frequency device;

12 to 26 steps of a method for manufacturing a high frequency device;

30 a method for manufacturing a high frequency device;

a step of manufacturing a 32-38 high frequency device;

100 a substrate;

102 a buffer layer;

102' patterning the buffer layer;

104a conductive layer;

104' patterning the conductive layer;

104a first conductive material;

104b a second conductive material;

104N an nth conductive material;

200 high frequency device architecture;

g1 crystal grains;

g2 crystal grains;

p1 first position;

p2 second position;

t thickness.

T' thickness.

Detailed Description

The structure of the high-frequency device of the present disclosure and the method for manufacturing the same will be described in detail below. It is to be understood that the following description provides many different embodiments, or examples, for implementing different aspects of some embodiments of the disclosure. The specific components and arrangements described below are merely illustrative of some embodiments of the disclosure for simplicity and clarity. These are, of course, merely examples and are not intended to be limiting of the disclosure. Moreover, repeated reference numerals or designations may be used in various embodiments. These iterations are merely provided for a simplified and clear description of some embodiments of the disclosure, and do not represent any correlation between the various embodiments and/or structures discussed. Furthermore, when a first material layer is located on or above a second material layer, the first material layer and the second material layer are in direct contact. Alternatively, one or more layers of other materials may be present, in which case there may not be direct contact between the first and second layers of material.

It should be understood that the components or devices of the drawings may exist in a variety of forms well known to those of ordinary skill in the art. Furthermore, relative terms, such as "lower" or "bottom" and "upper" or "top," may be used in embodiments to describe one component's relative relationship to another component of the drawings. It will be understood that if the device of the drawings is turned upside down, elements described as being on the "lower" side will be elements on the "upper" side. The embodiments of the present disclosure can be understood together with the drawings, which are also considered part of the disclosure. It is to be understood that the drawings of the present disclosure are not to scale and that in fact any elements may be exaggerated or minimized in size to clearly illustrate the features of the present invention while the same or similar elements are indicated by similar symbols in the specification and drawings.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various components or sections, these components, sections, or sections should not be limited by these terms, and these terms are merely used to distinguish different components, sections, or sections. Thus, a first element, component, or section discussed below could be termed a second element, component, or section without departing from the teachings of the present disclosure.

As used herein, the term "about", "about" or "substantially" generally means within 20%, preferably within 10%, more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. The amounts given herein are approximate, that is, the meanings of "about", "about" and "substantially" may be implied without specifically stating "about", "about" or "substantially".

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Furthermore, in some embodiments of the present disclosure, terms such as "connected," "interconnected," and the like, with respect to bonding, connecting, and the like, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, unless otherwise specified, with other structures being interposed between the two structures. And the terms coupled and connected should also be construed to include both structures being movable or both structures being fixed.

The manufacturing method of the high-frequency device can form the conductive layer with larger thickness (for example, more than 1 μm), and can reduce the warpage caused by overhigh temperature of the conductive layer or the substrate by controlling the process temperature when the conductive layer is formed, thereby reducing the difficulty of subsequent process. According to some embodiments of the present disclosure, a method for manufacturing a high frequency device intermittently forms a conductive layer with a large thickness on a substrate, and the conductive layer can be formed at a relatively low temperature, thereby reducing the problem of warpage caused by stress increase of the conductive layer or the substrate. The high frequency device of the present disclosure may be, for example, a liquid crystal antenna, but is not limited thereto, and the frequency range of the high frequency device may be, for example, greater than or equal to 1 gigahertz (GHz) and less than or equal to 50 gigahertz (GHz). The conductive layer in the high-frequency device of the present disclosure may have, for example, a function of a waveguide or transmitting a microwave signal, but is not limited thereto.

Fig. 1 shows a flow chart of steps of a method 10 of manufacturing a high frequency device, according to some embodiments. It should be understood that additional operations may be provided before, during, and/or after the fabrication method 10 for high frequency devices is performed. In various embodiments, some of the stages described may be replaced or deleted. Additional features may be added to the high frequency device and in different embodiments some of the features described below may be replaced or deleted. Fig. 2A-2E illustrate cross-sectional views of a high frequency device formed using the fabrication method 10 of fig. 1 at various stages, according to some embodiments.

Referring first to fig. 1 and 2A, a method 10 for manufacturing a high frequency device begins at step 12 by providing a substrate 100. The material of the substrate 100 may include glass, quartz, sapphire (sapphire), Polycarbonate (PC), Polyimide (PI), polyethylene terephthalate (PET), other materials suitable as a substrate, or a combination of the foregoing, but is not limited thereto. In some embodiments, the material of the substrate 100 may be glass. In some embodiments, the thickness of the substrate 100 ranges from about 0.3mm to about 1.1 mm.

In some embodiments, the method 10 for fabricating a high frequency device may optionally include step 14 of forming a buffer layer 102 on the substrate 100. The buffer layer 102 may be used to increase adhesion between the substrate 100 and a subsequently formed conductive layer. The material of the buffer layer 102 may include molybdenum, titanium, aluminum, copper alloy, molybdenum alloy, Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), other suitable buffer materials, or a combination of the foregoing, but is not limited thereto. In some embodiments, the material of the buffer layer 102 may include molybdenum. In some embodiments, the buffer layer 102 has a thickness in the range of about

To

For example, it can be

Further, the buffer layer 102 may be formed by a Chemical Vapor Deposition (CVD) process, a Physical Vapor Deposition (PVD) process, an electroplating process, an electroless plating process, other suitable processes, or a combination thereof, but is not limited thereto. In some embodiments, the buffer layer 102 may be formed by a physical vapor deposition process. The physical vapor deposition process may include, but is not limited to, sputtering, evaporation, Pulsed Laser Deposition (PLD), and the like. In some embodiments, the buffer layer 102 may be formed by a sputtering process.

Next, referring to fig. 1 and fig. 2B, in step 16, a first conductive material 104a is formed on the buffer layer 102. The first conductive material 104a may include copper, aluminum, tungsten, titanium, gold, platinum, nickel, copper alloy, aluminum alloy, tungsten alloy, titanium alloy, gold alloy, platinum alloy, nickel alloy, other suitable conductive materials, or a combination of the foregoing, but is not limited thereto. In some embodiments, the first conductive material 104a comprises copper. In some embodiments, the thickness of the first conductive material 104a ranges approximately from

To

Or

To

For example, it can be

Further, the first conductive material 104a may be formed by a chemical vapor deposition process, a physical vapor deposition process, an electroplating process, an electroless plating process, other suitable processes, or a combination thereof, but is not limited thereto. In some embodiments, the first conductive material 104a may be formed using a physical vapor deposition process. The physical vapor deposition process may include, but is not limited to, a sputtering process, an evaporation process, a pulsed laser deposition, and the like. In some embodiments, the first conductive material 104a may be formed by a sputtering process.

After forming the first conductive material 104a, the substrate 100 and the first conductive material 104a formed thereon are left for a first time interval t₁As shown in step 18. In detail, the substrate 100 is placed in a process chamber (process chamber) before the buffer layer 102 is formed, for example, in a physical vapor deposition process chamber, and the subsequent conductive layer forming step is performed in the same process chamber. That is, after the first conductive material 104a is formed, the substrate 100 and the conductive material 104a formed thereon are left standing in the same process chamber without moving the substrate 100. In some embodiments, the first time interval t₁May range from about 0.5 minutes to about 30 minutes or from about 1 minute to about 10 minutes, for example about 2 minutes. I.e. the first time interval t₁Can be greater than or equal to about 0.5 minutes and less than or equal to about 30 minutes (0.5 minutes ≦ first time interval t ₁30 minutes), or about 1 minute or more and 10 minutes or less (1 minute or less first time interval t)₁10 min ≦).

Next, referring to fig. 1 and fig. 2C, in step 20, a second conductive material 104b is formed on the first conductive material 104 a. The structure and formation method of the second conductive material 104b are substantially the same as those of the first conductive material 104 a. Specifically, the second conductive material 104b may include copper, aluminum, tungsten, titanium, gold, platinum, nickel, copper alloy, aluminum alloy, tungsten alloy, titanium alloy, gold alloy, platinum alloy, nickel alloy, other suitable conductive materials, or a combination of the foregoing, but is not limited thereto. In some embodiments, the second conductive material 104b comprises copper. In some embodiments, the second conductive material 104b has a thickness in the range of about

To

Or

To

For example, it can be

In one embodiment, steps 12, 16 and 18 may be repeated at least once in sequence to form a conductive layer 104, but is not limited thereto. The thickness T of the conductive layer 104 may be formed in a range of about 0.9 μm to 10 μm or 1 μm to 5 μm. That is, the thickness T of the conductive layer 104 may be greater than or equal to about 0.9 μm and less than or equal to about 10 μm (0.9 μm. ltoreq. thickness T. ltoreq.10 μm), or greater than or equal to about 1 μm and less than or equal to about 5 μm (1 μm. ltoreq. thickness T. ltoreq.5 μm).

Further, the second conductive material 104b may be formed by a chemical vapor deposition process, a physical vapor deposition process, an electroplating process, an electroless plating process, other suitable processes, or a combination thereof, but is not limited thereto. In some embodiments, the second conductive material 104b may be formed using a physical vapor deposition process. The physical vapor deposition process may include, but is not limited to, a sputtering process, an evaporation process, a pulsed laser deposition, and the like. In some embodiments, the second conductive material 104b may be formed by a sputtering process.

Then, after forming the second conductive material 104b, the substrate 100 and the first conductive material 104a and the second conductive material 104b formed thereon are left standing in the process chamber for a second time interval t₂As shown in step 22. In some embodiments, the second time interval t₂May range from about 0.5 minutes to about 30 minutes, or from about 1 minute to about 10 minutes, e.g., about 2 minutes. I.e. the second time interval t₂Can be greater than or equal to about 0.5 minutes and less than or equal to about 30 minutes (0.5 minutes ≦ second time interval t ₂30 minutes), or about 1 minute or more and 10 minutes or less (1 minute or less, second time interval t)₂10 min ≦).

Then, referring to fig. 1 and fig. 2D, the steps 16 to 22 are repeated at least once, that is, the steps of forming the conductive material and the step of standing are sequentially repeated at least once to form the conductive layer 104 (step 24). In some embodiments, the conductive layer 104 may include a first conductive material 104a, a second conductive material 104b …, and an nth conductive material 104N. It is understood that the subsequently formed conductive material (e.g., the nth conductive material 104N) also has a similar structure and formation method as the first conductive material 104a and the second conductive material 104b, and thus, the description thereof is omitted. In some embodiments, the thickness T of the conductive layer 104 may be formed in a range of about 0.9 μm to about 10 μm, or about 1 μm to about 5 μm. That is, the conductive layer 104 may be formed to have a thickness T of about 0.9 μm or more and 10 μm or less, or about 1 μm or more and 5 μm or less.

In addition, although the conductive materials of the first conductive material 104a, the second conductive material 104b, etc. may have similar thicknesses or structures under the same process conditions in the illustrated embodiments, it is understood that the thicknesses, structures, or materials of the conductive material layers may be substantially the same or different without departing from the teachings of the present disclosure. On the other hand, the time of rest (e.g., first time interval t)₁And a second time interval t₂Etc.) may be maintained at a relatively low temperature, e.g., the substrate 100 may be maintained at a temperature of less than 130 c or less than 120 c during the formation of the conductive layer 104. In some embodiments, the time for standing can be such that the substrate 100 is maintained at a temperature range greater than or equal to 10 ℃ and less than or equal to 130 ℃ (10 ℃ ≦ 130 ℃ for the substrate 100), i.e., in a range from 10 ℃ to 130 ℃, during the formation of the conductive layer 104.

In detail, during the process of forming the conductive layer 104 on the substrate 100, when the deposition of the conductive layer 104 is performed by, for example, a sputtering process, the particles continuously impact the substrate 100, thereby generating the release of heat energy. Thus, when thicker conductive layers 104 are continuously deposited, the thermal energy will accumulate in large amounts, and excessive temperatures (e.g., greater than 250 ℃) cause increased stress to the conductive layers 104 or the substrate 100 and severe warpage. However, intermittently (intermittently) forming the conductive layer 104 on the substrate 100, that is, sequentially repeating the steps of forming the conductive material and the step of standing at least once, or forming the conductive layer 104 with a time interval, the temperature of the substrate 100 can be controlled to a lower temperature (for example, less than 130 ℃), which reduces the occurrence of the foregoing.

Next, referring to fig. 1 and fig. 2E, in step 26, the substrate 100 and the conductive layer 104 formed thereon are removed from the process chamber, and a patterning process is performed to form a patterned conductive layer 104'. In some embodiments, as shown in fig. 2E, during the patterning of the conductive layer 104, the buffer layer 102 is also partially removed, forming a patterned buffer layer 102'.

The patterning process may include a photolithography process and an etching process. The photolithography process may include, but is not limited to, photoresist coating (e.g., spin coating), soft baking, hard baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, and drying. The etching process may include a dry etching process or a wet etching process. In particular, the process of patterning the conductive layer 104 includes a high temperature process, such as a photolithography process or an etching process at a temperature range of 130 ℃ to 360 ℃. In some embodiments, the temperature of the substrate 100 during the step of patterning the conductive layer 104 (step 26) is greater than the temperature of the substrate 100 during the step of forming the conductive layer (steps 16-20). As mentioned above, since the conductive layer 104 is formed in a lower temperature process, the grain size of the conductive layer 104 is smaller than that in a higher temperature process. However, after the high temperature process for patterning the conductive layer 104, the grain size of the conductive layer 104 becomes larger. In other words, the high temperature process of patterning the conductive layer 104 has an effect similar to annealing (annealing).

On the other hand, according to other embodiments of the present disclosure, the method for manufacturing a high frequency device can continuously form a conductive layer with a larger thickness on the substrate, and control the temperature of the substrate by the cooling system, so as to reduce the problem of warpage caused by the stress increase of the conductive layer or the substrate due to high temperature. Fig. 3 shows a flow chart of steps of a method 30 of manufacturing a high frequency device, according to some embodiments. Fig. 4A-4C illustrate cross-sectional views of a high frequency device formed using the method 30 of fig. 3 at various stages according to some embodiments.

Referring first to fig. 3 and 4A, a method 30 of fabricating a high frequency device begins at step 32 by providing a substrate 100. The material of the substrate 100 may include glass, quartz, sapphire, polycarbonate, polyimide, polyethylene terephthalate, other materials suitable as a substrate, or a combination of the foregoing, but is not limited thereto. In some embodiments, the material of the substrate 100 may be glass. In some embodiments, the thickness of the substrate 100 ranges from about 0.3mm to about 1.1 mm.

In some embodiments, the method 30 for fabricating a high frequency device may optionally include step 34 of forming a buffer layer 102 on the substrate 100. The buffer layer 102 may be used to increase adhesion between the substrate 100 and a subsequently formed conductive layer. The material of the buffer layer 102 may include molybdenum, titanium, aluminum, copper alloy, molybdenum alloy, Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), other suitable buffer materials, or a combination of the foregoing, but is not limited thereto. In some embodiments, the material of the buffer layer 102 may include molybdenum. In some embodiments, the buffer layer 102 has a thickness in the range of about

To

For example, it can be

Further, the buffer layer 102 may be formed by a chemical vapor deposition process, a physical vapor deposition process, an electroplating process, an electroless plating process, other suitable processes, or a combination thereof, but is not limited thereto. In some embodiments, the buffer layer 102 may be formed by a physical vapor deposition process. The physical vapor deposition process may include, but is not limited to, a sputtering process, an evaporation process, a pulsed laser deposition, and the like. In some embodiments, the buffer layer 102 may be formed by a sputtering process.

Next, referring to fig. 3 and fig. 4B, in step 36, a conductive layer 104 is formed on the buffer layer 102. It is noted that the temperature of the substrate 100 may range from greater than or equal to about 10 ℃ to less than or equal to about 130 ℃ during the formation of the conductive layer 104. In this embodiment, the conductive layer 104 is continuously formed on the buffer layer 102. In some embodiments, the thickness T of the conductive layer 104 can be greater than or equal to about 0.9 μm and less than or equal to about 10 μm, or can be greater than or equal to about 1 μm and less than or equal to about 5 μm. The material of the conductive layer 104 may include copper, aluminum, tungsten, titanium, gold, platinum, nickel, copper alloy, aluminum alloy, tungsten alloy, titanium alloy, gold alloy, platinum alloy, nickel alloy, other suitable conductive materials, or a combination of the foregoing, but is not limited thereto. In some embodiments, the material of the conductive layer 104 comprises copper.

Further, the conductive layer 104 may be formed by a chemical vapor deposition process, a physical vapor deposition process, an electroplating process, an electroless plating process, other suitable processes, or a combination thereof, but is not limited thereto. In some embodiments, the conductive layer 104 may be formed using a physical vapor deposition process. The physical vapor deposition process may include, but is not limited to, a sputtering process, an evaporation process, a pulsed laser deposition, and the like. In some embodiments, the conductive layer 104 may be formed by a sputtering process.

As described above, since the conductive layer 104 is continuously formed on the buffer layer 102, the temperature of the substrate 100 is significantly increased, and therefore, in this embodiment, the temperature of the substrate 100 is maintained at a relatively low temperature by the cooling system additionally provided during the process of forming the conductive layer 104. In some embodiments, the substrate 100 may be maintained at a temperature of less than 130 ℃ or less than 120 ℃ during the formation of the conductive layer 104. In some embodiments, the substrate 100 may be controlled by the cooling system to be maintained at a temperature of about 10 ℃ or higher and 130 ℃ or lower during the formation of the conductive layer 104. Therefore, the situation of warping caused by the stress increase of the conductive layer 104 or the substrate 100 can be reduced. Further, in some embodiments, the temperature of the cooling system itself ranges from about-70 ℃ to-190 ℃ or from-80 ℃ to-150 ℃.

Next, referring to fig. 3 and 4C, in step 38, the substrate 100 and the conductive layer 104 formed thereon are removed from the process chamber, and a patterning process is performed to form a patterned conductive layer 104'. In some embodiments, as shown in fig. 4C, during the patterning of the conductive layer 104, the buffer layer 102 is also partially removed, forming a patterned buffer layer 102'.

The patterning process may include a photolithography process and an etching process. The photolithography process may include, but is not limited to, photoresist coating (e.g., spin coating), soft baking, hard baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, and drying. The etching process may include a dry etching process or a wet etching process. In particular, the process of patterning the conductive layer 104 includes a high temperature process, such as a photolithography process or an etching process at a temperature range of 130 ℃ to 360 ℃. In some embodiments, the temperature of the substrate 100 in the step of patterning the conductive layer 104 (step 38) is greater than the temperature of the substrate 100 in the step of forming the conductive layer (step 36). As mentioned above, since the conductive layer 104 is formed in a lower temperature process, the grain size of the conductive layer 104 is smaller than that in a higher temperature process. However, after the high temperature process for patterning the conductive layer 104, the grain size of the conductive layer 104 becomes larger. In other words, the high temperature process of patterning the conductive layer 104 has an annealing-like effect.

As shown in fig. 2E and 4C, the high frequency device structure completed by the high frequency device manufacturing method 10 and the high frequency device manufacturing method 30 is schematically shown. The high frequency device 200 may have a substrate 100, and a patterned conductive layer 104' formed on the substrate 100. In some embodiments, the buffer layer 102 is further included between the substrate 100 and the patterned conductive layer 104 ', that is, the patterned buffer layer 102 ' may be disposed between the substrate 100 and the patterned conductive layer 104 '. The structure of the patterned conductive layer 104' is further described in detail below. In some embodiments, the patterned conductive layer 104' comprises copper.

Fig. 5A-5D are schematic diagrams of images of the patterned conductive layer 104' of the high frequency device structure observed by a Scanning Electron Microscope (SEM), according to some embodiments. As shown in fig. 5A to 5D, the patterned conductive layer 104' has a first position P1 and a second position P2, the first position P1 is adjacent to the substrate 100, and the second position P2 is away from the substrate 100. Furthermore, the patterned conductive layer 104 'has a thickness T'. The distance between the first position P1 and the substrate 100 is approximately 1/5 a thickness T ', and the distance between the second position P2 and the substrate 100 is approximately 4/5 a thickness T'. In other words, the first position P1 is located at a thickness T 'of about 1/5 from the substrate 100, and the second position P2 is located at a thickness T' of about 4/5 from the substrate 100. In some embodiments, the grain size of grain G1 (shown in dashed lines) at first position P1 is larger than the grain size of grain G2 (shown in dashed lines) at second position P2. However, it is understood that the position having the thickness T 'of about 1/5 from the substrate 100 may have a plurality of first positions P1, and the position having the thickness T' of about 4/5 from the substrate 100 may have a plurality of second positions P2, not limited to the positions illustrated in the drawings. Furthermore, the grain size of the patterned conductive layer 104' is not uniform. In some embodiments, the grain boundary (grain boundary) of the first position P1 is less than the grain boundary of the second position P2.

In summary, the grain size of the grains closer to the at least one first position P1 of the substrate 100 is larger than the grain size of the grains farther from the at least one second position P2 of the substrate 100, and the grain boundaries of the grains closer to the at least one first position P1 of the substrate 100 are smaller than the grain boundaries of the grains farther from the at least one second position P2 of the substrate 100, which is presumably because the high temperature process of the patterned conductive layer 104 has a greater influence on the temperature of the substrate 100, so that the influence of the temperature on the first position P1 closer to the substrate 100 is more significant than that on the second position P2, which increases the situation that the grain size becomes larger or the grain boundaries become smaller.

In addition, as shown in fig. 5A to 5D, the patterned conductive layer 104' further includes a plurality of stacked structures (as indicated by arrows) adjacent to the second position P2. In some embodiments, the dies are stacked on top of each other, forming a stacked structure that is substantially stacked along the Y-direction (parallel to the normal direction of the substrate). In some embodiments, the dies are stacked in a direction that is about 0.5 to 45 degrees from the Y-direction to form a stacked structure, but not limited thereto. In some embodiments, the thickness of each die in the stacked structure may be different. In other embodiments, the thickness of each die in the stacked structure may be partially the same and partially different, but is not limited thereto. Furthermore, in some embodiments, the width of each die may be different in the same stacked structure. In some embodiments, the grain width is also different between different stacked structures, but is not limited thereto.

As mentioned above, the grains adjacent to the second position P2 are not completely aligned, and the stacked structure may be mixed with other grains, such as, but not limited to, columnar grains or spherical grains. In fact, there are various kinds of grains different in size or pattern in the vicinity of the first position P1 and the second position P2.

Examples 1 to 3 batch Process

Copper is plated on a glass substrate by a PVD sputtering process in an intermittent deposition process (as shown in the high frequency device manufacturing method 10) until the copper layer thickness reaches 3 μm, and the copper layer is subjected to a patterning process after the deposition is completed. The substrate temperature of the sputtering process is in the range of 10-150 ℃, the sputtering time is 4-13 seconds, then the sputtering is stopped for 0.5-30 minutes, and the cycle is 10-100 times. Thereafter, annealing is performed at a temperature greater than 230 ℃ for more than 30 minutes.

Comparative example-high temperature continuous Process

Copper was plated on the glass substrate using a PVD sputtering process using a continuous deposition method until the copper layer thickness reached 3 μm. The substrate temperature of the sputtering process is in the range of 200-300 ℃, and the sputtering time is 150-500 seconds.

Morphology observation of conductive layer

Images of the conductive layer formed according to the method of the embodiment were observed using a Scanning Electron Microscope (SEM), and the results are shown in fig. 5A to 5D. As mentioned above, the conductive layer has a larger grain size and fewer grain boundaries at the position adjacent to the substrate, whereas the conductive layer has a smaller grain size and more grain boundaries at the position farther from the substrate, and has a plurality of grains stacked on top of each other to form a stacked structure, which may extend in the direction Y parallel to the normal line of the substrate, or may extend in other directions, but is not limited thereto. Generally, grains of different sizes or patterns are mixedly present in the conductive layer, and this is more pronounced in regions farther from the substrate.

Influence of patterning process on conductive layer

According to one embodiment, the effect of the patterning process on the resistivity of the conductive layer is measured. In detail, the resistivity of the conductive layer before the patterning process is performed and after the patterning process is performed by the method of the comparative example. For example, the measurement can be performed by using NAPSON HA-6100/RG-1000F four-point probe resistance measurement apparatus, and the measurement result is: the resistivity of the conductive layer without patterning process was 2.37 μ Ω cm, and the resistivity of the conductive layer after patterning process was reduced to 2.07 μ Ω cm.

Structure observation of conductive layer

For example, Shimadzu XRD-6000 can be used to perform X-ray diffraction analysis on the conductive layer, and FIGS. 6A to 6E show X-ray diffraction patterns of copper layers formed according to the methods shown in comparative examples and examples 1 to 3, respectively. In particular, the method of comparative example 1 corresponds to a conventional high temperature (e.g., greater than 250 ℃) continuous deposition process.

FIGS. 6A to 6E show X-ray diffraction patterns of the formed copper layers at the crystal orientations (111), (200), (220), (311) and (222), respectively. In which, examples 1 to 3 represent the results of measuring three different positions of the same sample. As shown in fig. 6A to 6E, the copper layers formed in the comparative examples and examples have small differences in strength between the crystal orientation (111) (fig. 6A) and the crystal orientation (220) (fig. 6C); the strength of the comparative example was higher than that of the example in the crystal orientation (200) (FIG. 6B), the crystal orientation (311) (FIG. 6D) and the crystal orientation (222) (FIG. 6E). In addition, the copper layers formed in the comparative examples and the examples have a relatively significant peak shift phenomenon in the crystal orientation (200). From the above results, it is understood that the copper layers formed in the comparative examples and examples have different crystal states, and for example, the copper layers formed in the comparative examples and examples have different ratios of crystal orientations (2 θ).

In summary, the method for manufacturing a high frequency device according to the present disclosure can form a conductive layer with a larger thickness (e.g., greater than 1 μm) under a relatively low temperature process condition, and compared to the conventional high temperature continuous plating process, the method for manufacturing a high frequency device according to the present disclosure can effectively alleviate the stress in the substrate structure, so as to reduce the warpage of the conductive layer or the substrate due to an excessive temperature. In addition, the manufacturing method of the high-frequency device can further change the resistivity or the grain state of the conductive layer by the patterning process, so as to change the performance of the conductive layer.

Although embodiments of the present disclosure and their advantages have been disclosed above, it should be understood that various changes, substitutions and alterations can be made herein by those skilled in the art without departing from the spirit and scope of the disclosure. Moreover, the scope of the present disclosure is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification, but rather, the present disclosure will suggest themselves to those skilled in the art having the benefit of this disclosure, and is intended to cover such modifications as would normally occur to one skilled in the art to which this disclosure pertains, if not expressly written herein, to the extent that such modifications are possible in the practice of the embodiments described herein, or the results of such modifications are achieved. Accordingly, the scope of the present disclosure includes the processes, machines, manufacture, compositions of matter, means, methods, and steps described above. In addition, each claim constitutes a separate embodiment, and the scope of protection of the present disclosure also includes combinations of the respective claims and embodiments. The scope of the present invention is defined by the appended claims.

Claims

1. A method of manufacturing a liquid crystal antenna, comprising:

providing a substrate, wherein the material of the substrate comprises glass;

forming a buffer layer on the substrate, wherein the buffer layer is made of molybdenum;

forming a conductive material on the buffer layer;

resting for a first time interval, wherein the first time interval ranges from 0.5 minutes to 30 minutes;

sequentially repeating the step of forming the conductive material and the step of standing at least once to form a conductive layer, wherein the thickness of the conductive layer ranges from 0.9 μm to 10 μm; and

patterning the conductive layer, wherein the patterned conductive layer has a first location adjacent to the substrate, the patterned conductive layer has a second location remote from the substrate, the first location is located at the thickness from the substrate 1/5, the second location is located at the thickness from the substrate 4/5, and the grain size at the first location is greater than the grain size at the second location.

2. The method of claim 1, wherein the conductive layer comprises copper.

3. A method of manufacturing a liquid crystal antenna, comprising:

providing a substrate, wherein the material of the substrate comprises glass;

forming a conductive material on the buffer layer;

sequentially repeating the step of forming the conductive material and the step of standing at least once to form a conductive layer on the substrate, wherein the temperature of the substrate ranges from 10 ℃ to 130 ℃; and

4. The method of claim 3, wherein the conductive layer has a thickness in a range of 0.9 μm to 10 μm.

5. A method of manufacturing a liquid crystal antenna according to claim 3, wherein the conductive layer comprises copper.

6. A liquid crystal antenna structure, comprising:

a substrate, the material of the substrate comprises glass;

the buffer layer is positioned on the substrate, and the material of the buffer layer comprises molybdenum; and

a patterned conductive layer on the buffer layer, the patterned conductive layer having a thickness;

wherein the patterned conductive layer has a first location adjacent to the substrate, the patterned conductive layer has a second location remote from the substrate, the first location is located at the thickness from the substrate 1/5, the second location is located at the thickness from the substrate 4/5, and the grain size at the first location is larger than the grain size at the second location.

7. The liquid crystal antenna structure of claim 6, wherein the patterned conductive layer has a laminated structure adjacent to the second location.

8. The liquid crystal antenna structure of claim 6, wherein the patterned conductive layer comprises copper.