CN108321086A - High frequency device and method for manufacturing the same - Google Patents

Abstract

The present disclosure provides a method of manufacturing a high frequency device, including: providing a substrate; forming a conductive material on a substrate; standing for a first time interval; sequentially repeating the steps of forming the conductive material and the step of standing at least once to form a conductive layer, wherein the thickness of the conductive layer ranges from 0.9 μm to 10 μm; and patterning the conductive layer. The present disclosure also provides a high frequency device.

Description

High frequency device and its manufacturing method

technical field

The present disclosure relates to a high-frequency device and its manufacturing method, in particular to a conductive layer of the high-frequency device and its manufacturing method.

Background technique

In the manufacture of traditional displays, when the conductive layer is deposited on the substrate by, for example, physical vapor deposition (PVD), only a few thousand angstroms need to be deposited. That is, it meets the requirements of the product, but for high-frequency devices (eg, antennas), it is necessary to arrange a thick conductive layer on the substrate. However, for a substrate with a general thickness, plating a thicker conductive layer (for example, greater than 1 micron (μm)) requires a long period of continuous deposition, and the atomic impact during the process releases a large amount of heat energy accumulated on the substrate. The conductive layer and the substrate cause the conductive layer or the substrate to warp due to the increase in the stress of the structure, which prevents the substrate plated with conductive materials (such as metal) from smoothly entering the equipment machine for subsequent processing operations, such as , photolithography, cleaning processes, etc., resulting in difficulties in the production of thick conductive layer components.

Therefore, developing a conductive coating structure that can effectively maintain a flat state can reduce the above-mentioned warpage problem that occurs when forming a thick conductive layer on a substrate.

Contents of the invention

In some embodiments, the present disclosure provides a method for manufacturing a high-frequency device, including: providing a substrate; forming a conductive material on the substrate; standing for a first time interval; and repeating the step of forming the conductive material in sequence. and the step of standing still at least once to form a conductive layer, wherein the thickness of the conductive layer is in the range of 0.9 μm to 10 μm; and patterning the conductive layer.

In some other embodiments, the present disclosure provides a method for manufacturing a high-frequency device, including: providing a substrate; forming a conductive layer on the substrate, the temperature of the substrate is in the range of 10°C to 130°C; and patterning the conductive layer.

In some other embodiments, a high-frequency device structure includes: a substrate; and a patterned conductive layer located on the substrate, and the patterned conductive layer has a thickness; wherein, the patterned conductive layer is adjacent to The substrate has a first position, the patterned conductive layer has a second position away from the substrate, the first position is located at the thickness of 1/5 from the substrate, and the second position is located at 4/5 from the substrate at the thickness, and the grain size at the first location is larger than the grain size at the second location.

Description of drawings

In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and understandable, the specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

FIG. 1 is a flowchart of steps of a method for manufacturing a high-frequency device according to some embodiments of the present disclosure;

2A to 2E are cross-sectional views of high-frequency devices at different stages in the manufacturing process according to some embodiments of the present disclosure;

FIG. 3 is a flowchart of steps of a method for manufacturing a high-frequency device according to some embodiments of the present disclosure;

4A to 4C are cross-sectional views of high-frequency devices at different stages in the manufacturing process according to some embodiments of the present disclosure;

5A to 5D are schematic diagrams of images obtained by using a scanning electron microscope (SEM) to observe a patterned conductive layer of a high-frequency device structure according to some embodiments of the present disclosure;

6A to 6E are X-ray diffraction analysis diagrams of the conductive layer according to some embodiments of the present disclosure.

Explanation of component numbers in the figure:

10. Manufacturing method of high-frequency device;

12-26 Steps of the manufacturing method of the high-frequency device;

30. Manufacturing methods of high-frequency devices;

32-38 The steps of the manufacturing method of the high-frequency device;

100 substrates;

102 buffer layer;

102' patterned buffer layer;

104 conductive layer;

104' patterned conductive layer;

104a a first conductive material;

104b a second conductive material;

104n Nth conductive material;

200 High-frequency device structure;

G1 grain;

G2 die;

P1 first position;

P2 second position;

T Thickness.

T' thickness.

Detailed ways

The structure and manufacturing method of the high-frequency device of the present disclosure will be described in detail below. It should be appreciated that the following description provides many different embodiments or examples for implementing different aspects of some embodiments of the present disclosure. The specific components and arrangements described below are only for simple and clear description of some embodiments of the present disclosure. Of course, these are only examples rather than limitations of the present disclosure. Furthermore, repeated reference numerals or designations may be used in different embodiments. These repetitions are only for simply and clearly describing some embodiments of the present disclosure, and do not mean that there is any relationship between the different embodiments and/or structures discussed. Furthermore, when it is mentioned that a first material layer is located on or above a second material layer, it includes the situation that the first material layer is in direct contact with the second material layer. Alternatively, one or more layers of other material may be interspersed, in which case there may be no direct contact between the first material layer and the second material layer.

It should be understood that the components or devices in the drawings can exist in various forms well known to those skilled in the art. In addition, relative terms such as "lower" or "bottom" and "higher" or "top" may be used in the embodiments to describe the relative relationship of one component to another component in the drawings. It will be appreciated that if the illustrated device is turned over so that it is upside down, components described as being on the "lower" side would then become components on the "higher" side. The embodiments of the present disclosure can be understood together with the drawings, and the drawings of the present disclosure are also regarded as a part of the disclosure. It should be understood that the drawings of the present disclosure are not drawn to scale. In fact, the dimensions of components may be arbitrarily enlarged or reduced in order to clearly show the features of the present invention. In the specification and drawings, the same or similar components will be indicated by a similar symbol.

It can be understood that although the terms "first", "second", "third" and the like may be used herein to describe various components or parts, these components, components or parts should not be limited by these terms, and these terms It is only used to distinguish different components, components or parts. Accordingly, a first component, component or section discussed below could be termed a second component, component or section without departing from the teachings of the present disclosure.

Here, the terms "about", "approximately" and "substantially" usually mean within 20%, preferably within 10%, more preferably within 5%, or within 3% of a given value or range. Within %, or within 2%, or within 1%, or within 0.5%. The quantities given here are approximate quantities, that is, "about", "approximately" and "substantially" can still be implied without specifying "about", "approximately" and "substantially". meaning.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It can be understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having meanings consistent with the background or context of the related art and the present disclosure, and should not be interpreted in an idealized or overly formal manner. Interpretation, unless otherwise defined in the embodiments of the present disclosure.

In addition, in some embodiments of the present disclosure, terms related to bonding and connection, such as "connection" and "interconnection", unless otherwise specified, may mean that two structures are in direct contact, or may also mean that two structures are not in direct contact. Contact, where other structures are placed between the two structures. And the terms about joining and connecting may also include the situation that both structures are movable, or both structures are fixed.

The manufacturing method of the high-frequency device provided by the present disclosure can form a conductive layer with a relatively large thickness (for example, greater than 1 μm), and by controlling the process temperature during the formation of the conductive layer, it can reduce warpage caused by the excessive temperature of the conductive layer or the substrate. curve, thereby reducing the difficulty of subsequent manufacturing processes. According to some embodiments of the present disclosure, the manufacturing method of the high-frequency device is to intermittently form a conductive layer with a relatively large thickness on the substrate, which can form the conductive layer at a relatively low temperature to reduce warpage caused by the increased stress of the conductive layer or the substrate. song problem. The high-frequency device of the present disclosure may be, for example, a liquid crystal antenna, but not limited thereto, and the frequency range of the high-frequency device may be, for example, greater than or equal to 1 GHz and less than or equal to 50 GHz. The conductive layer in the high-frequency device of the present disclosure may, for example, function as a waveguide or transmit microwave signals, but is not limited thereto.

FIG. 1 shows a flowchart of the steps of a method 10 for manufacturing a high frequency device according to some embodiments. It should be understood that additional operations may be provided before, during and/or after the method 10 for manufacturing a high frequency device. In various embodiments, some of the stages described may be replaced or deleted. Additional features may be added to the high frequency device, and some of the features described below may be replaced or deleted in different embodiments. 2A to 2E show cross-sectional views at different stages of a high-frequency device formed using the manufacturing method 10 shown in FIG. 1 according to some embodiments.

First, please refer to FIG. 1 and FIG. 2A , the manufacturing method 10 of a high-frequency device starts at step 12 , and a substrate 100 is provided. The material of the substrate 100 may include glass, quartz, sapphire (sapphire), polycarbonate (polycarbonate, PC), polyimide (polyimide, PI), polyethylene terephthalate (polyethylene terephthalate, PET), other Materials or combinations of the foregoing are suitable as substrates, but are not limited thereto. In some embodiments, the material of the substrate 100 may be glass. In some embodiments, the thickness of the substrate 100 ranges from about 0.3 mm to about 1.1 mm.

In some embodiments, the method 10 for manufacturing a high frequency device may optionally include a step 14 of forming a buffer layer 102 on the substrate 100 . The buffer layer 102 can be used to increase the adhesion between the substrate 100 and the subsequently formed conductive layer. The material of the buffer layer 102 may include molybdenum, titanium, aluminum, copper alloy, molybdenum alloy, indium tin oxide (ITO), indium zinc oxide (IZO), other suitable buffer materials or combinations thereof, but is not limited thereto. In some embodiments, the material of the buffer layer 102 may include molybdenum. In some embodiments, the buffer layer 102 has a thickness ranging from about to For example about

Furthermore, the buffer layer 102 can be formed by chemical vapor deposition (chemical vapor deposition, CVD), physical vapor deposition (physical vapor deposition, PVD), electroplating, electroless plating, other suitable processes, or a combination of the foregoing. , but not limited to this. In some embodiments, the buffer layer 102 may be formed by a physical vapor deposition process. The physical vapor deposition process may include sputtering, evaporation, pulsed laser deposition (PLD), etc., but is not limited thereto. In some embodiments, the buffer layer 102 may be formed by a sputtering process.

Next, please refer to FIG. 1 and FIG. 2B , in step 16 , a first conductive material 104 a is formed on the buffer layer 102 . The first conductive material 104a may include copper, aluminum, tungsten, titanium, gold, platinum, nickel, copper alloy, aluminum alloy, tungsten alloy, titanium alloy, gold alloy, platinum alloy, nickel alloy, other suitable conductive materials or the aforementioned combination, but not limited to this. In some embodiments, the first conductive material 104a includes copper. In some embodiments, the thickness of the first conductive material 104a ranges from about to or to For example about

Furthermore, the first conductive material 104a can be formed by chemical vapor deposition process, physical vapor deposition process, electroplating process, electroless plating process, other suitable processes or combinations thereof, but is not limited thereto. In some embodiments, the first conductive material 104a may be formed by a physical vapor deposition process. The physical vapor deposition process may include sputtering process, evaporation process, pulsed laser deposition, etc., but is not limited thereto. In some embodiments, the first conductive material 104a may be formed by a sputtering process.

After the first conductive material 104a is formed, the substrate 100 and the first conductive material 104a formed thereon are left to rest for a first time interval t ₁ , as shown in step 18 . Specifically, before forming the buffer layer 102, the substrate 100 is placed in a process chamber, for example, placed in a physical vapor deposition process chamber, and the subsequent conductive layer forming steps are also in the same process. carried out in the chamber. That is, after the first conductive material 104a is formed, the substrate 100 does not need to be moved but the substrate 100 and the conductive material 104a formed thereon are placed in the same process chamber. In some embodiments, the first time interval t ₁ ranges from about 0.5 minutes to 30 minutes or from about 1 minute to 10 minutes, for example, about 2 minutes. That is, the range of the first time interval _t1 may be approximately greater than or equal to 0.5 minutes and less than or equal to 30 minutes (0.5 minutes≦the first time interval _t1 ≦30 minutes), or approximately may be greater than or equal to 1 minute and less than or equal to It is equal to 10 minutes (1 minute≦first time interval t ₁ ≦10 minutes).

Next, please refer to FIG. 1 and FIG. 2C, in step 20, a second conductive material 104b is formed on the first conductive material 104a. The structure and forming method of the second conductive material 104b are substantially the same as those of the first conductive material 104a. Specifically, the second conductive material 104b may include copper, aluminum, tungsten, titanium, gold, platinum, nickel, copper alloy, aluminum alloy, tungsten alloy, titanium alloy, gold alloy, platinum alloy, nickel alloy, and other suitable conductive materials. materials or combinations of the foregoing, but not limited thereto. In some embodiments, the second conductive material 104b includes copper. In some embodiments, the thickness of the second conductive material 104b ranges from about to or to For example about In one embodiment, steps 12 , 16 and 18 may be repeated at least once to form a conductive layer 104 , but not limited thereto. The thickness T of the formed conductive layer 104 may range approximately from 0.9 μm to 10 μm or from 1 μm to 5 μm. That is, the thickness T of the formed conductive layer 104 may be greater than or equal to 0.9 μm and less than or equal to 10 μm (0.9 μm≦thickness T≦10 μm), or approximately greater than or equal to 1 μm and less than or equal to 5 μm (1 μm≦thickness T ≦5μm).

Furthermore, the second conductive material 104b can be formed by chemical vapor deposition process, physical vapor deposition process, electroplating process, electroless plating process, other suitable processes or combinations thereof, but is not limited thereto. In some embodiments, the second conductive material 104b may be formed by a physical vapor deposition process. The physical vapor deposition process may include sputtering process, evaporation process, pulsed laser deposition, etc., but is not limited thereto. In some embodiments, the second conductive material 104b may be formed by a sputtering process.

Next, after the second conductive material 104b is formed, the substrate 100 and the first conductive material 104a and the second conductive material 104b formed thereon are left in the processing chamber for a second time interval _t2 , as shown in step 22 . In some embodiments, the second time interval t ₂ may range from about 0.5 minutes to 30 minutes, or from 1 minute to 10 minutes, such as about 2 minutes. That is, the second time interval _t2 may be approximately greater than or equal to 0.5 minutes and less than or equal to 30 minutes (0.5 minutes≦second time interval _t2 ≦30 minutes), or approximately greater than or equal to 1 minute and less than or equal to 10 minutes. minutes (1 minute≦second time interval t ₂ ≦10 minutes).

After that, referring to FIG. 1 and FIG. 2D , repeat the aforementioned step 16 to step 22 at least once, that is, repeat the step of forming the conductive material and the step of standing for at least one time to form the conductive layer 104 (step 24 ). In some embodiments, the conductive layer 104 may include a first conductive material 104a, a second conductive material 104b . . . and an Nth conductive material 104n. It can be understood that the subsequently formed conductive material (for example, the Nth conductive material 104n) also has a structure and a formation method similar to those of the first conductive material 104a and the second conductive material 104b mentioned above, and details will not be repeated here. In some embodiments, the thickness T of the formed conductive layer 104 may range from about 0.9 μm to 10 μm, or 1 μm to 5 μm. That is, the thickness T of the formed conductive layer 104 may be greater than or equal to 0.9 μm and less than or equal to 10 μm, or may be greater than or equal to 1 μm and less than or equal to 5 μm.

In addition, although in the illustrated embodiment, the first conductive material 104a, the second conductive material 104b and other conductive materials may have similar thicknesses or structures under the same process conditions, it should be understood that in The thicknesses, structures or materials of the various conductive material layers may be substantially the same or different without departing from the teachings of the present disclosure. On the other hand, the standing time (for example, the first time interval _t1 and the second time interval _t2, etc.) can moderately lower the temperature of the substrate 100 and the conductive material, and keep it at a relatively low temperature, for example, the substrate 100 can be kept at a relatively low temperature. 100 is maintained at a temperature of less than 130° C. or less than 120° C. during the formation of conductive layer 104 . In some embodiments, the standing time can keep the substrate 100 at a temperature range greater than or equal to 10°C and less than or equal to 130°C during the formation of the conductive layer 104 (10°C≦temperature of the substrate 100≦130°C ), that is, in the range of 10°C to 130°C.

In detail, during the process of forming the conductive layer 104 on the substrate 100 , when the conductive layer 104 is deposited by, for example, a sputtering process, heat energy is released due to the continuous impact of the particles on the substrate 100 . Therefore, when continuously depositing thicker conductive layers 104 , a large amount of thermal energy will be accumulated, and excessively high temperature (eg, greater than 250° C.) will increase the stress of the conductive layer 104 or the substrate 100 and cause serious warpage. However, intermittently (intermittently) forming the conductive layer 104 on the substrate 100, that is, repeating the step of forming the conductive material and the step of resting at least once in sequence, or having a time interval during the process of forming the conductive layer 104, the substrate can be 100 The temperature is controlled at a lower temperature (for example, less than 130° C.) to reduce the occurrence of the aforementioned situation.

Next, please refer to FIG. 1 and FIG. 2E , in step 26, the substrate 100 and the conductive layer 104 formed thereon are removed from the processing chamber, and a patterning process is performed to form a patterned conductive layer 104'. In some embodiments, as shown in FIG. 2E , during the process of patterning the conductive layer 104, the buffer layer 102 is partially removed to form a patterned buffer layer 102'.

The patterning process may include a photolithography process and an etching process. The photolithography process may include photoresist coating (eg, spin coating), soft bake, hard bake, mask alignment, exposure, post-exposure bake, photoresist development, cleaning and drying, etc., but is not limited thereto. The etching process may include a dry etching process or a wet etching process. In particular, the process of patterning the conductive layer 104 includes a high temperature process, for example, a photolithography process or an etching process at a temperature range of 130° C. to 360° C. In some embodiments, the temperature of the substrate 100 in the step of patterning the conductive layer 104 (step 26 ) is greater than the temperature of the substrate 100 in the step of forming the conductive layer (steps 16 - 20 ). As mentioned above, since the conductive layer 104 is formed in a lower temperature process, the grain size of the conductive layer 104 is smaller than that in a high temperature process. However, after the aforementioned high-temperature process for patterning the conductive layer 104 , the size of some grains of the conductive layer 104 will become larger. In other words, the high temperature process of patterning the conductive layer 104 has an effect similar to annealing.

On the other hand, according to some other embodiments of the present disclosure, the manufacturing method of the high-frequency device can continuously form a thicker conductive layer on the substrate, and control the temperature of the substrate by means of a cooling system, so as to reduce the occurrence of high temperature on the conductive layer or the substrate. Increased stress creates warpage problems. FIG. 3 shows a flowchart of steps of a method 30 for manufacturing a high frequency device according to some embodiments. 4A-4C show cross-sectional views of a high-frequency device formed using the method 30 shown in FIG. 3 at different stages, according to some embodiments.

First, please refer to FIG. 3 and FIG. 4A , the manufacturing method 30 of the high-frequency device starts at step 32 , and the substrate 100 is provided. The material of the substrate 100 may include glass, quartz, sapphire, polycarbonate, polyimide, polyethylene terephthalate, other materials suitable for the substrate, or combinations thereof, but is not limited thereto. In some embodiments, the material of the substrate 100 may be glass. In some embodiments, the thickness of the substrate 100 ranges from about 0.3 mm to about 1.1 mm.

In some embodiments, the method 30 for manufacturing a high frequency device may optionally include a step 34 of forming a buffer layer 102 on the substrate 100 . The buffer layer 102 can be used to increase the adhesion between the substrate 100 and the subsequently formed conductive layer. The material of the buffer layer 102 may include molybdenum, titanium, aluminum, copper alloy, molybdenum alloy, indium tin oxide (ITO), indium zinc oxide (IZO), other suitable buffer materials or combinations thereof, but is not limited thereto. In some embodiments, the material of the buffer layer 102 may include molybdenum. In some embodiments, the buffer layer 102 has a thickness ranging from about to For example about

Moreover, the buffer layer 102 can be formed by chemical vapor deposition process, physical vapor deposition process, electroplating process, electroless plating process, other suitable processes or a combination of the foregoing, but not limited thereto. In some embodiments, the buffer layer 102 may be formed by a physical vapor deposition process. The physical vapor deposition process may include sputtering process, evaporation process, pulsed laser deposition, etc., but is not limited thereto. In some embodiments, the buffer layer 102 may be formed by a sputtering process.

Next, please refer to FIG. 3 and FIG. 4B , in step 36 , a conductive layer 104 is formed on the buffer layer 102 . It should be noted that during the formation of the conductive layer 104 , the temperature of the substrate 100 is in a range of greater than or equal to 10° C. and less than or equal to 130° C. In this embodiment, the conductive layer 104 is continuously formed on the buffer layer 102 . In some embodiments, the thickness T of the conductive layer 104 may be greater than or equal to 0.9 μm and less than or equal to 10 μm, or may be greater than or equal to 1 μm and less than or equal to 5 μm. The material of the conductive layer 104 may include copper, aluminum, tungsten, titanium, gold, platinum, nickel, copper alloy, aluminum alloy, tungsten alloy, titanium alloy, gold alloy, platinum alloy, nickel alloy, other suitable conductive materials or the aforementioned combination, but not limited to this. In some embodiments, the material of the conductive layer 104 includes copper.

Moreover, the conductive layer 104 can be formed by chemical vapor deposition process, physical vapor deposition process, electroplating process, electroless plating process, other suitable processes or combinations thereof, but not limited thereto. In some embodiments, the conductive layer 104 may be formed using a physical vapor deposition process. The physical vapor deposition process may include sputtering process, evaporation process, pulsed laser deposition, etc., but is not limited thereto. In some embodiments, the conductive layer 104 may be formed by a sputtering process.

As mentioned above, since the conductive layer 104 is continuously formed on the buffer layer 102, the temperature of the substrate 100 will increase significantly. Therefore, in this embodiment, during the process of forming the conductive layer 104, an additional cooling system is used to control The temperature of the substrate 100 is maintained at a relatively low temperature. In some embodiments, the substrate 100 may be maintained at a temperature of less than 130° C. or less than 120° C. during the formation of the conductive layer 104 . In some embodiments, the cooling system can be used to control the temperature of the substrate 100 during the formation of the conductive layer 104 in a range of greater than or equal to 10°C and less than or equal to 130°C. In this way, the warpage caused by the increased stress of the conductive layer 104 or the substrate 100 can be reduced. Additionally, in some embodiments, the temperature of the cooling system itself ranges from about -70°C to -190°C or -80°C to -150°C.

Next, please refer to FIG. 3 and FIG. 4C , in step 38, the substrate 100 and the conductive layer 104 formed thereon are removed from the processing chamber, and a patterning process is performed to form a patterned conductive layer 104'. In some embodiments, as shown in FIG. 4C , during the process of patterning the conductive layer 104, the buffer layer 102 is partially removed to form a patterned buffer layer 102'.

The patterning process may include a photolithography process and an etching process. The photolithography process may include photoresist coating (eg, spin coating), soft bake, hard bake, mask alignment, exposure, post-exposure bake, photoresist development, cleaning and drying, etc., but is not limited thereto. The etching process may include a dry etching process or a wet etching process. In particular, the process of patterning the conductive layer 104 includes a high temperature process, for example, a photolithography process or an etching process at a temperature range of 130° C. to 360° C. In some embodiments, the temperature of the substrate 100 in the step of patterning the conductive layer 104 (step 38 ) is greater than the temperature of the substrate 100 in the step of forming the conductive layer (step 36 ). As mentioned above, since the conductive layer 104 is formed in a lower temperature process, the grain size of the conductive layer 104 is smaller than that in a high temperature process. However, after the aforementioned high-temperature process for patterning the conductive layer 104 , the size of some grains of the conductive layer 104 will become larger. In other words, the high temperature process of patterning the conductive layer 104 has an effect similar to annealing.

As shown in FIG. 2E and FIG. 4C , schematic diagrams of the structure of the high-frequency device completed according to the manufacturing method 10 of the high-frequency device and the manufacturing method 30 of the high-frequency device are respectively shown. The high frequency device 200 may have a substrate 100 and a patterned conductive layer 104' formed on the substrate 100. Referring to FIG. In some embodiments, the buffer layer 102 is further included between the substrate 100 and the patterned conductive layer 104', that is, there may be a patterned buffer layer 102' between the substrate 100 and the patterned conductive layer 104'. The structure of the patterned conductive layer 104' is further described in detail as follows. In some embodiments, the patterned conductive layer 104' includes copper.

5A to 5D show schematic diagrams of images obtained by using a scanning electron microscope (SEM) to observe the patterned conductive layer 104' of the high-frequency device structure according to some embodiments. As shown in FIG. 5A to FIG. 5D , the patterned conductive layer 104' has a first position P1 and a second position P2, the first position P1 is located adjacent to the substrate 100, and the second position P2 is located away from the substrate 100. Furthermore, the patterned conductive layer 104' has a thickness T'. The distance between the first position P1 and the substrate 100 is about 1/5 of the thickness T', and the distance between the second position P2 and the substrate 100 is about 4/5 of the thickness T'. In other words, the first position P1 is located at about 1/5 of the thickness T' away from the substrate 100, and the second position P2 is located at about 4/5 of the thickness T' away from the substrate 100. In some embodiments, the grain size of the grain G1 (shown by the dotted line) at the first position P1 is larger than the grain size of the grain G2 (shown by the dotted line) at the second position P2 . However, it should be understood that a position about 1/5 of the thickness T' from the substrate 100 may have a plurality of first positions P1, and a position of about 4/5 of the thickness T' from the substrate 100 may have a plurality of second positions P2. , not limited to the position shown in the figure. Furthermore, the grain size of the patterned conductive layer 104' is not uniform. In some embodiments, the grain boundaries of the first position P1 are less than the grain boundaries of the second position P2.

In view of the above, the grain size of the grains at least one first position P1 closer to the substrate 100 is larger than the grain size of the grains at least one second position P2 farther away from the substrate 100, and the grain size of at least one second position P2 closer to the substrate 100 is larger. The grain boundaries of the grains at a position P1 are less than the grain boundaries of at least one second position P2 away from the substrate 100. It is speculated that this may be due to the influence of the aforementioned high-temperature process of the patterned conductive layer 104 on the temperature of the substrate 100. Larger, so that the first position P1 closer to the substrate 100 is more affected by the temperature than the second position P2, resulting in increased grain size or fewer grain boundaries.

In addition, as shown in FIG. 5A to FIG. 5D , the patterned conductive layer 104' further includes a plurality of stacked structures (as indicated by arrows) adjacent to the second position P2. In some embodiments, the dies are stacked on each other to form a stacked structure substantially along the Y direction (parallel to the normal direction of the substrate). In some embodiments, the crystal grains are stacked along a direction with an angle of about 0.5° to 45° with respect to the Y direction to form a stacked structure, but not limited thereto. In some embodiments, the thickness of each grain in the stacked structure may be different. In some other embodiments, the thicknesses of the crystal grains in the stacked structure may be partly the same and partly different, but not limited thereto. In addition, in some embodiments, in the same stacked structure, the widths of the grains may be different. In some embodiments, the grain widths are also different between different stacked structures, but not limited thereto.

Based on the foregoing, the grains adjacent to the second position P2 are not completely aligned, and the stacked structure is also mixed with other types of grains, such as columnar grains or spherical grains, but not limited thereto. In fact, various crystal grains with different sizes or shapes are mixed in the vicinity of the first position P1 and the second position P2 .

Embodiment 1 to embodiment 3-batch process

Copper is plated on the glass substrate by a PVD sputtering process by a batch deposition method (as shown in the manufacturing method 10 of a high-frequency device) until the thickness of the copper layer reaches 3 μm, and the copper layer is patterned after the deposition is completed Process. The substrate temperature of the above-mentioned sputtering process is in the range of 10-150° C., the sputtering time is 4-13 seconds, and then the sputtering is stopped for 0.5-30 minutes, and the cycle is 10-100 times. Thereafter, annealing is performed at a temperature greater than 230° C. for more than 30 minutes.

Comparative example - high temperature continuous process

Using a continuous deposition method, copper is plated on the glass substrate using a PVD sputtering process until the thickness of the copper layer reaches 3 μm. The substrate temperature of the above sputtering process is in the range of 200-300° C., and the sputtering time is 150-500 seconds.

Morphological observation of the conductive layer

A scanning electron microscope (SEM) is used to observe the schematic images of the conductive layer formed according to the method shown in the embodiment, and the results are shown in FIG. 5A to FIG. 5D . As mentioned above, the grain size of the conductive layer near the substrate is larger and there are fewer grain boundaries. On the contrary, the grain size farther away from the substrate is smaller and the grain boundaries are more. The crystal grains form a stacked structure, and the stacked structure may extend along a direction Y parallel to the normal of the substrate, or the stacked structure may extend along other directions, but is not limited thereto. Generally speaking, crystal grains with different sizes or shapes exist mixedly in the conductive layer, and this situation is more obvious in a region farther from the substrate.

Effect of Patterning Process on Conductive Layer

According to the method shown in the embodiment, the effect of the patterning process on the resistivity of the conductive layer was measured. Specifically, the resistivity of the conductive layer before and after the implementation of the patterning process in the method shown in the embodiment is compared. For example, NAPSON HA-6100/RG-1000F four-point probe resistance measuring instrument can be used for measurement. The measurement result is: the resistivity of the conductive layer without patterning process is 2.37μΩcm, and after patterning process The resistivity of the conductive layer dropped to 2.07 μΩcm.

Structural Observation of Conductive Layer

For example, Shimadzu XRD-6000 can be used to conduct X-ray diffraction analysis on the conductive layer. Figure 6A to Figure 6E show the X-ray diffraction of the copper layer formed according to the methods shown in Comparative Example and Examples 1-3 respectively. shooting map. In particular, the method shown in Comparative Example 1 is equivalent to the traditional high temperature (eg greater than 250° C.) continuous deposition process.

6A to FIG. 6E respectively show the X-ray diffraction patterns of the formed copper layer at crystallographic orientations (111), (200), (220), (311), and (222). Among them, Examples 1 to 3 represent the results of measuring three different positions of the same sample. As shown in Figures 6A to 6E, the copper layers formed in Comparative Examples and Examples have little difference in the strength of the crystal orientation (111) (Figure 6A) and the crystal orientation (220) (Figure 6C); in the crystal orientation (200) (FIG. 6B), crystal orientation (311) (FIG. 6D) and crystal orientation (222) (FIG. 6E), the strength of the comparative example is higher than that of the embodiment. In addition, the copper layer formed in the comparative example and the embodiment has a more obvious peak shift phenomenon in the crystal orientation (200). From the above results, it can be seen that the crystallization conditions of the copper layers formed in the comparative examples and the examples are different, for example, the proportions of the copper layers formed in the comparative examples and the examples are different in different crystal orientations (2θ).

In summary, the method for manufacturing a high-frequency device provided by the present disclosure can form a conductive layer with a relatively large thickness (for example, greater than 1 μm) under relatively low-temperature process conditions. Compared with the traditional high-temperature continuous coating process, the present disclosure The manufacturing method of the high-frequency device can effectively relieve the stress in the substrate structure, thereby reducing the warpage of the conductive layer or the substrate due to excessive temperature. In addition, the manufacturing method of the high-frequency device of the present disclosure can further change the resistivity or grain shape of the conductive layer through a patterning process, thereby changing the performance of the conductive layer.

Although the embodiments of the present disclosure and their advantages have been disclosed above, it should be understood that those skilled in the art can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. In addition, the protection scope of the present disclosure is not limited to the process, machine, manufacture, material composition, device, method and steps in the specific embodiments described in the specification, any person of ordinary skill in the art can understand from the disclosure content of the present disclosure Any existing or future developed processes, machines, manufactures, compositions of matter, devices, methods and steps can be used in accordance with the present disclosure as long as they can perform substantially the same functions or obtain substantially the same results in the embodiments described herein. Therefore, the protection scope of the present disclosure includes the above-mentioned process, machine, manufacture, composition of matter, device, method and steps. In addition, each claim constitutes an individual embodiment, and the protection scope of the present disclosure also includes combinations of the individual claims and the embodiments. The scope of protection of the present invention should be defined by the appended claims.

Claims (14)

1. A method for manufacturing a high-frequency device, comprising: providing a substrate; forming a conductive material on the substrate; standing for a first time interval; sequentially repeating the step of forming the conductive material and the step of standing at least once to form a conductive layer, wherein the thickness of the conductive layer ranges from 0.9 μm to 10 μm; and The conductive layer is patterned. 2. The method for manufacturing a high frequency device as claimed in claim 1, wherein the first time interval ranges from 0.5 minutes to 30 minutes. 3. The method for manufacturing a high-frequency device as claimed in claim 1, wherein the temperature of the substrate in the patterning step is higher than the temperature of the substrate in the step of forming the conductive layer. 4. The method for manufacturing a high frequency device as claimed in claim 1, further comprising forming a buffer layer on the substrate before the step of forming the conductive material. 5. The method of manufacturing a high frequency device as claimed in claim 1, wherein the conductive layer comprises copper. 6. A method for manufacturing a high-frequency device, comprising: providing a substrate; forming a conductive layer on the substrate, the temperature of the substrate is in the range of 10°C to 130°C; and The conductive layer is patterned. 7 . The method for manufacturing a high frequency device as claimed in claim 6 , wherein the conductive layer has a thickness ranging from 0.9 μm to 10 μm. 8. The method of manufacturing a high frequency device as claimed in claim 6, wherein the temperature of the substrate in the patterning step is higher than the temperature of the substrate in the step of forming the conductive layer. 9. The method for manufacturing a high frequency device as claimed in claim 6, further comprising forming a buffer layer on the substrate before the step of forming the conductive layer. 10. The method of manufacturing a high frequency device as claimed in claim 6, wherein the conductive layer comprises copper. 11. A high-frequency device structure, characterized in that it comprises: a substrate; and A patterned conductive layer is located on the substrate, and the patterned conductive layer has a thickness; Wherein, the patterned conductive layer has a first position adjacent to the substrate, and the patterned conductive layer has a second position away from the substrate, the first position is located at a distance of 1/5 of the thickness from the substrate, and the first position is Two positions are located 4/5 of the thickness away from the substrate, and the grain size of the first position is larger than the grain size of the second position. 12. The high-frequency device structure as claimed in claim 11, wherein the patterned conductive layer has a stacked structure adjacent to the second position. 13. The high frequency device structure as claimed in claim 11, wherein the patterned conductive layer comprises copper. 14. The high frequency device structure as claimed in claim 11, further comprising a buffer layer located between the substrate and the patterned conductive layer.