CN108306702B - Synchronous code detection system - Google Patents
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- CN108306702B CN108306702B CN201711336390.XA CN201711336390A CN108306702B CN 108306702 B CN108306702 B CN 108306702B CN 201711336390 A CN201711336390 A CN 201711336390A CN 108306702 B CN108306702 B CN 108306702B
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Abstract
The embodiment of the invention discloses a synchronous code detection system, which comprises: a demultiplexer, a comparator, and a detection circuit; the demultiplexer is used for converting the first group of serial data and the second group of serial data output by the clock data recovery circuit into first parallel data and second parallel data respectively; the comparator is connected with the demultiplexer and is used for judging whether the synchronous code carried by the first parallel data is the same as the first group of calibration synchronous codes and whether the synchronous code carried by the second parallel data is the same as the second group of calibration synchronous codes; and the detection circuit is connected with the comparator and is used for detecting the transmission type of the first group of serial data and the second group of serial data according to the judging result of the comparator. The embodiment of the invention solves the problem that the first group of serial data and the second group of serial data which are output by the clock data recovery circuit cannot be identified, and realizes the effect of correctly identifying the two groups of serial data transmission types so as to correctly recover the original data.
Description
Technical Field
The embodiment of the invention relates to the technical field of communication, in particular to a synchronous code detection system.
Background
An 8b/10b coding mode is often adopted in the current high-speed serial communication system, so that the purpose is to balance the number of 0 and 1 in a data bit stream and achieve the effect of balancing direct current. In an 8b/10b communication system, a plurality of K control words are defined as synchronous identification marks, 8bit data are expanded into 10bit data after 8b/10b coding, and a transmitting end physical layer outputs the 10bit data from low order to high order bit by bit to form a high-speed serial data stream. The receiving end physical layer restores the high-speed serial data stream into half transmission rate clock CLK and Bit0 and Bit1 serial data through a clock data restoring circuit CDR, the CLK and Bit0 and Bit1 serial data are restored into 10-Bit wide parallel signals, finally the 10-Bit wide parallel signals are restored into 8-Bit data and K control words after 8b/10b decoding, and the K control bits represent that the type of input data is data or control words.
Although in the prior art, data recovery is performed on high-speed serial data, and data segmentation is performed by using a K control word as an identifier, when CDR recovers clock and data, two random transmission cases may exist for Bit0 and Bit1 serial data: one case is that Bit0 and Bit1 sets of serial data are simultaneously output, and the other case is that Bit1 serial data leads Bit0 serial data by one clock output. Because the serial data of Bit0 and Bit1 are output randomly, the transmission condition of the two groups of serial data of Bit0 and Bit1 cannot be determined, and a series of signals cannot be divided correctly at a high-speed serial receiving end, so that the original data cannot be restored.
Disclosure of Invention
The embodiment of the invention provides a synchronous code detection system, which is used for correctly dividing a series of signals at a high-speed serial receiving end so as to correctly recover original data.
The embodiment of the invention provides a synchronous code detection system, which comprises: a demultiplexer, a comparator, and a detection circuit; wherein,
The demultiplexer is used for converting the first group of serial data and the second group of serial data output by the clock data recovery circuit into first parallel data and second parallel data respectively;
The comparator is connected with the demultiplexer and is used for judging whether the synchronous code carried by the first parallel data is the same as the first group of calibration synchronous codes and whether the synchronous code carried by the second parallel data is the same as the second group of calibration synchronous codes;
The detection circuit is connected with the comparator and is used for detecting the transmission types of the first group of serial data and the second group of serial data according to the judgment result of the comparator; wherein the transmission types of the first group of serial data and the second group of serial data include: the first set of serial data and the second set of serial data are output simultaneously or the first set of serial data and the second set of serial data are output non-simultaneously.
Further, the system further comprises:
and the clock frequency dividing circuit is used for carrying out five-frequency division processing on the clock output by the clock data recovery circuit and generating a corresponding five-frequency division clock.
Further, the demultiplexer further includes:
The third D trigger is used for sampling the first standby parallel data by a five-frequency division clock to generate third parallel data, wherein the third parallel data is six-bit wide parallel data;
and the fourth D trigger is used for sampling the second standby parallel data by a five-frequency division clock to generate fourth parallel data, wherein the fourth parallel data is six-bit wide parallel data.
Further, the system further comprises:
And the synchronous reset circuit is used for sending a synchronous reset signal to position synchronous codes in the first group of serial data and the second group of serial data when the detection circuit detects that the transmission types of the first group of serial data and the second group of serial data are the simultaneous output of the first group of serial data and the second group of serial data or the non-simultaneous output of the first group of serial data and the second group of serial data.
Further, the system further comprises:
and the multiplexer is used for performing bit-spaced splicing on the third parallel data and the fourth parallel data according to the synchronous code position and the transmission types of the first group of serial data and the second group of serial data.
The embodiment of the invention provides a synchronous code detection system, which is used for comparing and verifying synchronous codes carried in first parallel data and second parallel data converted by a demultiplexer through a comparator, and detecting the transmission types of the first group of serial data and the second group of serial data through a detection circuit under the condition that the synchronous codes are verified to be correct. The embodiment of the invention solves the problem that the first group of serial data and the second group of serial data which are output by the clock data recovery circuit cannot be identified, realizes the correct identification of the two groups of serial data transmission types, and further realizes the effect of correctly dividing a series of signals at a high-speed serial receiving end so as to correctly recover the original data.
Drawings
Fig. 1 is a system block diagram of a synchronization code detection system according to a first embodiment of the present invention;
FIG. 2A is a system block diagram of a high-speed serial communication system according to a first embodiment of the present invention;
FIG. 2B is a schematic diagram of a high-speed serial data stream according to an embodiment of the present invention;
Fig. 2C is a functional block diagram of a receiving end of a high-speed serial communication system according to an embodiment of the present invention;
FIG. 3A is a schematic diagram showing a first group of serial data Bit1 and a second group of serial data Bit0 simultaneously output according to a first embodiment of the present invention;
FIG. 3B is a schematic diagram showing non-simultaneous output of a first group of serial data Bit1 and a second group of serial data Bit0 according to an embodiment of the present invention;
Fig. 4 is a circuit block diagram of a synchronization code detection system according to a second embodiment of the present invention;
Fig. 5 is a schematic structural diagram of a first comparator in a synchronization code detection system according to a second embodiment of the present invention;
Fig. 6 is a circuit diagram of a detection circuit in a synchronous code detection system according to a third embodiment of the present invention;
FIG. 7 is a block diagram of a data recovery system for detecting a synchronization code according to a fourth embodiment of the present invention;
Fig. 8A is a schematic diagram illustrating a simulation of positive synchronization code detection according to a fourth embodiment of the present invention;
fig. 8B is a schematic diagram of negative synchronization code detection according to a fourth embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
Example 1
Fig. 1 is a system block diagram of a synchronization code detection system according to an embodiment of the present invention, where the embodiment of the present invention may be applied to a high-speed serial bus receiving end, and the system block diagram of the synchronization code detection system according to the embodiment of the present invention, as shown in fig. 1, includes: a demultiplexer 110, a comparator 120 and a detection circuit 130.
In this embodiment, the synchronous code detection system may be composed of an output terminal of the demultiplexer 110 connected to an input terminal of the comparator 120, and an output terminal of the comparator 120 connected to an input terminal of the detection circuit 130.
The demultiplexer 110 is configured to convert the first set of serial data and the second set of serial data output by the clock data recovery circuit into first parallel data and second parallel data, respectively.
Generally, referring to fig. 2A, fig. 2A is a system block diagram of a high-speed serial communication system according to a first embodiment of the present invention, and a physical layer at a transmitting end of the high-speed serial communication system may output 10-bit wide parallel data output by 8b/10 codes from low-order to high-order bit by bit to form a high-speed serial data stream. Referring to fig. 2B, fig. 2B is a schematic diagram of a high-speed serial data stream structure according to a first embodiment of the present invention. Referring to fig. 2C, fig. 2C is a functional block diagram of a receiving end of a high-speed serial communication system according to an embodiment of the present invention, where a clock data recovery circuit can recover clock and data from a high-speed serial data stream according to fig. 2C, and the clock data recovery circuit outputs a first set of serial data Bit1 and a second set of serial data Bit0 randomly after recovering the data. Fig. 3A is a schematic diagram of simultaneous output of a first set of serial data Bit1 and a second set of serial data Bit0 according to the first embodiment of the present invention, and fig. 3B is a schematic diagram of non-simultaneous output of the first set of serial data Bit1 and the second set of serial data Bit0 according to the first embodiment of the present invention, wherein Bit1 leads Bit0 by one clock output in fig. 3B.
In the present embodiment, the first set of serial data Bit1 and the second set of serial data Bit0 output from the clock data recovery circuit are converted into the first parallel data corresponding to Bit1 and the second parallel data corresponding to Bit0, respectively, by the demultiplexer 110.
The comparator 120 is connected to the demultiplexer 110, and is configured to determine whether the synchronization code carried by the first parallel data is the same as the first set of calibration synchronization codes and whether the synchronization code carried by the second parallel data is the same as the second set of calibration synchronization codes.
In an 8b/10 high-speed serial communication system, K control words are generally defined in the transmitted data as marks for synchronous identification, and K28.5 words are generally used as marks, namely synchronous codes, and once K28.5 words are identified, the subsequent serial data are segmented by using the K28.5 words as coordinates. The K28.5 synchronous code carried in the 8bit data can be two 10 bit corresponding synchronous codes after 8b/10b coding, which are positive synchronous code RD+ or negative synchronous code RD-, respectively, and are complementary. Wherein, the positive synchronization code RD+ is 0x305, and the negative synchronization code RD-is 0x0FA.
In this embodiment, the 10-bit parallel data output through the 8b/10b encoding may carry a 10-bit positive synchronization code or a 10-bit negative synchronization code. Correspondingly, the subsequent high-speed serial data stream also carries 10-Bit positive synchronous codes or 10-Bit negative synchronous codes, and the first group of serial data Bit1 and the second group of serial data Bit0 which are further recovered by the clock data recovery circuit also respectively carry half of the positive synchronous codes or half of the negative synchronous codes added before. It should be noted that, since the high-speed serial data stream is recovered by the clock data recovery circuit into the first set of serial data Bit1 and the second set of serial data Bit0 that are transmitted in parallel, the 10-Bit positive synchronization code or the 10-Bit negative synchronization code carried in the high-speed serial data stream is mapped in the first set of serial data Bit1 and the second set of serial data Bit0 in a scattered manner. That is, the first set of serial data Bit1 carries a 5-Bit positive synchronization code and the second set of serial data Bit0 carries the remaining 5-Bit positive synchronization code; or the first group of serial data Bit1 carries 5-Bit negative synchronous codes and the second group of serial data Bit0 carries the rest 5-Bit negative synchronous codes. It can be seen that the 10-Bit synchronization code is split into two parts by Bit separation and mapped into the first group of serial data Bit1 and the second group of serial data Bit0 respectively, and the corresponding 5-Bit synchronization codes in the first group of serial data Bit1 and the second group of serial data Bit0 are carried in the first parallel data and the second parallel data obtained by the subsequent corresponding conversion.
Illustratively, it is assumed that the high-speed serial data stream includes a K28.5 positive synchronization code (0 x 305) control word, and the first set of serial data Bit1 and the second set of serial data Bit0 output through the clock data recovery circuit are output simultaneously. In this process, referring to fig. 2b, the 10-bit positive synchronization code (0 x 305) is in binary form in the data N, specifically: 1100000101; referring to fig. 3A, after being recovered by the clock data recovery circuit, the carrying modes of positive synchronous codes of 10 bits mapped to the first group of serial data Bit1 and the second group of serial data Bit0 at Bit1 and Bit0 are respectively: 10000 and 10011.
In this embodiment, the comparator 120 may compare and determine the 5-bit synchronization code carried by the first parallel data with the first set of calibration synchronization codes, and if the two are the same, it indicates that the 5-bit synchronization code carried by the first parallel data is verified to be correct; meanwhile, the comparator 120 may compare and determine the remaining 5-bit synchronization code carried by the second parallel data with the second set of calibration synchronization codes, and if the remaining 5-bit synchronization code carried by the second parallel data is the same, it indicates that the remaining 5-bit synchronization code carried by the second parallel data is verified to be correct. It should be noted that, the synchronization codes carried in the first parallel data and the second parallel data are both positive synchronization codes or both negative synchronization codes. The positive synchronization code (0 x 305) is converted to a binary representation: 1100000101, the negative synchronization code (0 x0 FA) is replaced by a binary representation: 0011111010. the positive synchronization code (0 x 305) can be separated into 10000 and 10011 by bit separation, and the 10000 and 10011 are respectively used as a first group of calibration synchronization codes and a second group of calibration synchronization codes; and/or the negative synchronization code (0 x0 FA) may also be separated into 01111 and 01100 as the first and second sets of calibration synchronization codes, respectively.
A detection circuit 130, connected to the comparator 120, for detecting the transmission type of the first group of serial data and the second group of serial data according to the judgment result of the comparator 120; wherein the transmission types of the first group of serial data and the second group of serial data comprise: the first and second sets of serial data are output simultaneously or the first and second sets of serial data are output non-simultaneously.
In this embodiment, when the 5-bit synchronization code carried by the first parallel data and the remaining 5-bit synchronization code carried by the second parallel data are verified to be correct at the same time, the synchronization codes of the first parallel data and the second parallel data are determined to be correct, that is, the existence of the synchronization codes is detected in the first parallel data and the second parallel data. Wherein the first parallel data may carry 5-bit synchronization code 10000 in positive synchronization code (0 x 305) and the second parallel data may carry the remaining 5-bit synchronization code 10011 in positive synchronization code (0 x 305); or the first parallel data may carry the 5-bit synchronization code 01111 in the negative synchronization code (0 x0 FA) and the second parallel data may carry the remaining 5-bit synchronization code 01100 in the negative synchronization code (0 x0 FA). It should be noted that only one of the positive synchronization code (0 x 305) and the negative synchronization code (0 x0 FA) can be carried in the same 10-bit data.
In this embodiment, when the comparator determines that the positive synchronization code or the negative synchronization code of the first parallel data and the second parallel data are correct, that is, the presence of the positive synchronization code or the negative synchronization code of the first parallel data and the second parallel data is detected, a detection signal is sent to the detection circuit 130, and the detection circuit 130 detects the transmission types of the first group of serial data and the second group of serial data according to the detection signal. And determining whether the first group of serial data and the second group of serial data are output simultaneously or are not output simultaneously according to the detection result.
The synchronous code detection system provided by the embodiment of the invention adopts the demultiplexer, the comparator and the detection circuit to determine the transmission types of the first group of serial data and the second group of serial data output by the clock data recovery circuit, so that the correct identification of the two groups of serial data transmission types is realized, a series of signals are further correctly segmented at a high-speed serial receiving end, and the effect of correctly recovering the original data is achieved.
Example two
Fig. 4 is a circuit block diagram of a synchronization code detection system according to a second embodiment of the present invention, where the synchronization code detection system according to the second embodiment of the present invention is optimized based on the foregoing embodiment, as shown in fig. 4, and includes: a demultiplexer 110, a comparator 120 and a detection circuit 130. Wherein:
The demultiplexer 110 may include: a first shift register 1101 and a second shift register 1102. The first shift register 1101 is specifically configured to convert a first set of serial data into first spare parallel data, and take the upper five bits in the first spare parallel data as the first parallel data; the second shift register 1102 is specifically configured to convert the second set of serial data into second spare parallel data, and take the upper five bits of the first spare parallel data as the second parallel data.
In the present embodiment, the first shift register 1101 and the second shift register 1102 receive serial data of 6 bits from the first group serial data Bit1 and the second group serial data Bit0, respectively, when receiving the first group serial data Bit1 and the second group serial data Bit0 output from the clock data recovery circuit CDR. For example, the first shift register 1101 and the second shift register 1102 may each employ a 6-bit shift register. Specifically, referring to fig. 3A and 3B, since the CDR output between the first and second sets of serial data Bit1 and Bit0 may be simultaneously output or Bit1 leads Bit0 by one clock output. When the first and second sets of serial data Bit1 and Bit0 are simultaneously output, the first and second shift registers 1101 and 1102 only need to receive 5 bits of data to acquire all data of the first and second sets of serial data Bit1 and Bit0, respectively. When the first set of serial data Bit1 leads the second set of serial data Bit0 by one clock output, since the first set of serial data Bit1 and the second set of serial data Bit0 are output in an interleaved manner, if the first shift register 1101 and the second shift register 1102 receive only 5 bits of data, 1 Bit of data may be absent from the first set of serial data Bit1 received by the first shift register 1101 or 1 Bit of data may be absent from the second set of serial data Bit0 received by the second shift register 1102. For the above reasons, regardless of the type of transmission of the first set of serial data and the second set of serial data output by the clock data recovery circuit CDR, if the first shift register 1101 and the second shift register 1102 receive 6-Bit serial data using a shift register, then the first shift register 1101 and the second shift register 1102 can receive the complete first set of serial data Bit1 and the complete second set of serial data Bit0.
In this embodiment, after the first shift register 1101 and the second shift register 1102 respectively receive the 6-Bit serial data corresponding to the first set of serial data Bit1 and the 6-Bit serial data corresponding to the second set of serial data Bit0, the first shift register 1101 converts the received 6-Bit serial data corresponding to the first set of serial data Bit1 into corresponding parallel data as first standby parallel data by using the function of serial input and parallel output of the shift registers; the second shift register 1102 converts the received 6-Bit serial data corresponding to the second set of serial data Bit0 into corresponding parallel data as second spare parallel data. The first shift register 1101 and the second shift register 1102 may directly output the upper 5-bit data of the first spare parallel data and the upper 5-bit data of the second spare parallel data as the first parallel data and the second parallel data, respectively. The input ports of the first shift register 1101 may include a CDR clock input port and a first set of serial data Bit1 input ports. The second shift register 1102 may receive the second set of serial data Bit0 output by the clock data recovery circuit CDR, and convert the second set of serial data Bit0 into corresponding parallel data as second spare parallel data. The input ports of the second shift register 1102 may include a CDR clock input port and a second set of serial data Bit0 input ports.
The comparator 120 may include: a first comparator 1201, a second comparator 1202, a third comparator 1203, and a fourth comparator 1204; wherein,
A first comparator 1201, configured to determine whether the synchronization code carried by the first parallel data is the same as the first set of calibration synchronization codes; the third comparator 1203 is configured to determine whether the synchronization code carried by the second parallel data is the same as the second set of calibration synchronization codes.
In this embodiment, the first comparator 1201 may compare the 5-bit synchronization code carried by the first parallel data with a preset first set of calibration synchronization codes one by one, and determine whether the 5-bit synchronization code carried by the first parallel data is the same as the first set of calibration synchronization codes. If the 5-bit synchronous code carried by the first parallel data is the same as the first group of calibration synchronous codes, the verification of the 5-bit synchronous code carried by the first parallel data is considered to be correct; if it is different, the verification is considered incorrect. Meanwhile, the third comparator 1203 may compare the remaining 5-bit synchronization code carried by the second parallel data with the preset second set of calibration synchronization codes one by one, to determine whether the remaining 5-bit synchronization code carried by the second parallel data is the same as the second set of calibration synchronization codes. If the remaining 5-bit synchronous codes carried by the second parallel data are the same as the second group of calibration synchronous codes, the remaining 5-bit synchronous codes carried by the second parallel data are considered to be verified to be correct; if it is different, the verification is considered incorrect.
Or a second comparator 1202 for determining whether the synchronization code carried by the first parallel data is the same as the first set of calibration synchronization codes; and a fourth comparator 1204 for determining whether the synchronization code carried by the second parallel data is the same as the second set of calibration synchronization codes.
In this embodiment, the second comparator 1202 may compare the 5-bit synchronization code carried by the first parallel data with the preset first set of calibration synchronization codes one by one, and determine whether the 5-bit synchronization code carried by the first parallel data is the same as the first set of calibration synchronization codes. If the 5-bit synchronous code carried by the first parallel data is the same as the first group of calibration synchronous codes, the verification of the 5-bit synchronous code carried by the first parallel data is considered to be correct; if it is different, the verification is considered incorrect. Meanwhile, the fourth comparator 1204 may compare the remaining 5-bit synchronization code carried by the second parallel data with a second set of calibration synchronization codes set in advance one by one, and determine whether the remaining 5-bit synchronization code carried by the second parallel data is the same as the second set of calibration synchronization codes. If the remaining 5-bit synchronous codes carried by the second parallel data are the same as the second group of calibration synchronous codes, the remaining 5-bit synchronous codes carried by the second parallel data are considered to be verified to be correct; if it is different, the verification is considered incorrect.
In the above-mentioned comparator 120, the first comparator 1201 and the third comparator 1203 may be used as one group, and the second comparator 1202 and the fourth comparator 1204 may be used as another group. Only one group of comparators can obtain the result of correct judgment and comparison or two groups of results of incorrect judgment and comparison at the same time, and the two groups of results of correct judgment and comparison cannot occur. In addition, the 5-bit synchronous code carried by the first parallel data and the rest 5-bit synchronous code carried by the second parallel data are obtained by separating and splitting the 10-bit K28.5 synchronous code, and the specific splitting process is the same as that in the embodiment. The preset first set of calibration synchronization codes and the preset second set of calibration synchronization codes can also be obtained by separating and splitting 10-bit K28.5 positive synchronization codes or negative synchronization codes.
On the basis of the above embodiment, any of the first comparator 1201, the second comparator 1202, the third comparator 1203, and the fourth comparator 1204 includes one positive synchronization code comparing unit and one negative synchronization code comparing unit inside.
Fig. 5 is a schematic structural diagram of a first comparator in a synchronization code detection system according to a second embodiment of the present invention. In the present embodiment, referring to fig. 5, the first comparator 1201 includes two synchronization code comparing units inside, one for comparing positive synchronization codes and the other for comparing negative synchronization codes. In addition, the second comparator 1202, the third comparator 1203, and the fourth comparator 1204 also employ the same structure as the first comparator 1201, and are not explained in detail here.
In this embodiment, the port of the data to be determined in the first comparator 1201 may be connected to the first parallel data output port of the first register 1101 and used for receiving the first parallel data output by the first register 1101, and the port of the data to be determined in the second comparator 1202 may also be connected to the first parallel data output port of the first register 1101 and used for receiving the first parallel data output by the first register 1101. The port of the data to be judged in the third comparator 1203 may be connected to the second parallel data output port of the second register 1102, for receiving the second parallel data output by the second register 1102, and the port of the data to be judged in the fourth comparator 1204 may also be connected to the second parallel data output port of the second register 1102, for receiving the second parallel data output by the second register 1102.
In this embodiment, the calibration synchronization code interfaces in the first and second comparators 1201 and 1202 may be connected to the first set of calibration synchronization codes, and the calibration synchronization code interfaces in the third and fourth comparators 1203 and 1204 may be connected to the second set of calibration synchronization codes. In the first comparator 1201, the first parallel data and the first set of calibration synchronization codes are judged by the positive synchronization code comparing unit and the negative synchronization code comparing unit. If the positive synchronization code comparison unit judges that the 5-bit synchronization code carried by the first parallel data is the same as the first group of 5-bit calibration synchronization codes, outputting a signal representing that the positive synchronization is the same; if the negative synchronization code comparison unit judges that the 5-bit synchronization code carried by the first parallel data is the same as the first group of 5-bit calibration synchronization codes, a signal representing that the negative synchronization is the same is output. Similarly, the second comparator 1202, the third comparator 1203 and the fourth comparator 1204 can obtain the same positive synchronization code or the same negative synchronization code signals by using a comparison process similar to that of the first comparator 1201. For example, positive synchronization code identity may be represented by equal+, and negative synchronization code identity may be represented by equal-.
Illustratively, a 10-bit K28.5 calibration synchronization code is represented by s [ n ], e.g., a positive synchronization code (0 x 305) is converted to a binary representation as: 1100000101, s [9] is "1100000101" 1 st number from left to right, "1", s [8] is "1100000101" 2 nd number from left to right, "1", … …, s [1] is "1100000101" 9 th number from left to right "0", s [0] is "1100000101" 10 th number from left to right "1". When the first comparator and the third comparator output equal+ or equal-, the control word of the comparator connected with the first serial data is { s9, s 7, s 5, s3, s1 } and the control word of the comparator connected with the second serial data is { s 8, s6, s4, s2, s 0 }. When the second comparator and the fourth comparator output equal+ or equal-, which indicates that the first group of serial data and the second group of serial data are not simultaneously output, the control words of the comparators connected with the first serial data are { s < 8 >, s < 6 >, s < 4 >, s < 2 >, s <0>, and the control words of the comparators connected with the second serial data are { s < 9 >, s < 7 >, s < 5 >, s <3>, s < 1 > }.
A detection circuit 130, connected to the comparator 120, for detecting the transmission type of the first group of serial data and the second group of serial data according to the judgment result of the comparator 120; wherein the transmission types of the first group of serial data and the second group of serial data comprise: the first and second sets of serial data are output simultaneously or the first and second sets of serial data are output non-simultaneously.
The synchronous code detection system provided by the embodiment of the invention specifically adopts the first shift register and the second shift register to respectively convert the first group of serial data and the second group of serial data output by the clock data recovery circuit into the first parallel data and the second parallel data, then adopts the first comparator and the third comparator or adopts the second comparator and the fourth comparator to determine the transmission types of the first group of serial data and the second group of serial data, thereby realizing the correct identification of the two groups of serial data transmission types, further realizing the correct segmentation of a series of signals at the high-speed serial receiving end and achieving the effect of correctly recovering the original data.
Example III
Fig. 6 is a circuit diagram of a detection circuit in a synchronization code detection system according to a third embodiment of the present invention. The present embodiment shows a specific circuit diagram of the detection circuit on the basis of the above-described embodiments.
As shown in fig. 6, a detection circuit 130 in the synchronous code detection system is connected to the comparator 120 and is used for detecting the transmission types of the first group of serial data and the second group of serial data according to the judgment result of the comparator 120; wherein the transmission types of the first group of serial data and the second group of serial data comprise: the first and second sets of serial data are output simultaneously or the first and second sets of serial data are output non-simultaneously.
In the present embodiment, the detection circuit 130 is configured to detect transmission types of the first group serial data and the second group serial data according to the determination results of the first comparator 1201 and the third comparator 1203;
Or further for detecting the transmission type of the first group serial data and the second group serial data according to the judgment result of the second comparator 1202 and the fourth comparator 1204.
Specifically, referring to fig. 6, the first comparator and the third comparator may determine the 5-bit synchronization code carried by the first parallel data and the remaining 5-bit synchronization code carried by the second parallel data by using the first set of calibration synchronization codes and the second set of calibration synchronization codes, respectively. If the 5-bit synchronization code carried by the first parallel data and the remaining 5-bit synchronization code carried by the second parallel data in the first comparator and the third comparator are judged to be the same at the same time, a first detection signal is sent to the detection circuit 130. Or the second comparator and the fourth comparator can also judge the 5-bit synchronous code carried by the first parallel data and the rest 5-bit synchronous code carried by the second parallel data by adopting the first group of calibration synchronous codes and the second group of calibration synchronous codes respectively. If the 5-bit synchronization code carried by the first parallel data and the remaining 5-bit synchronization code carried by the second parallel data in the second comparator and the fourth comparator are judged to be the same at the same time, a second detection signal is sent to the detection circuit 130.
Referring to fig. 3A, if the detection circuit 130 detects that the first detection signal is received, it determines that the first group serial data and the second group serial data are simultaneously output, and outputs a first judgment signal indicating that the first group serial data and the second group serial data are simultaneously output. Or referring to fig. 3B, if the detection circuit 130 detects that the second detection signal is received, it determines that the first set of serial data and the second set of serial data are not simultaneously output, i.e., the second serial data precede the second serial data by one clock output, and outputs a first judgment signal indicating that the first set of serial data and the second set of serial data are not simultaneously output. And meanwhile, a locking signal can be output, and a synchronous reset signal of the clock frequency dividing circuit is sent to position synchronous codes in the first parallel data and the second parallel data.
It should be noted that the first comparator and the third comparator may be set to a first group, and the second comparator and the fourth comparator may be set to a second group. Only one group of comparators can obtain the same result of judgment and comparison or two groups of comparators can not generate the same result of judgment in the same time, namely only one condition of simultaneously outputting the first group of serial data and the second group of serial data or outputting the first group of serial data and the second group of serial data in a non-simultaneous manner can be obtained in the judgment and comparison process.
In the present embodiment, referring to fig. 6, the detection circuit 130 includes: the first D trigger, the second D trigger and the RS trigger; the fourth comparator is connected with the first D trigger and the second D trigger, and the first D trigger and the second D trigger are connected with the RS trigger through an AND gate and/or an OR gate; the second comparator is connected with the RS trigger through an AND gate and/or an OR gate; the first comparator is connected with the RS trigger through an AND gate and/or an OR gate; the third comparator is connected with the RS trigger through an AND gate and/or an OR gate.
The detection circuit in the synchronous code detection system provided by the embodiment of the invention can detect the judgment comparison result of the comparator through the detection circuit, determine the transmission types of the first group of serial data and the second group of serial data, and output the judgment signals representing the transmission types of the first group of serial data and the second group of serial data.
Example IV
Fig. 7 is a block diagram of a data recovery system for detecting a synchronization code according to a fourth embodiment of the present invention, where the embodiment of the present invention may be applied to recovering data in a high-speed serial bus receiving end, and the embodiment of the present invention employs the synchronization code detection system provided by the foregoing embodiment. As shown in fig. 7, the data recovery system for synchronization code detection includes: the demultiplexer 110, the comparator 120 and the detection circuit 130, and the further data recovery system for synchronous code detection further comprises:
the clock frequency dividing circuit 140 is configured to perform a divide-by-five process on the clock output by the clock data recovery circuit, and generate a corresponding divide-by-five clock.
On the basis of the above embodiment, the demultiplexer 110 in the data recovery system for synchronization code detection further includes:
a third D flip-flop 1103, configured to sample the first standby parallel data by a divide-by-five clock to generate third parallel data, where the third parallel data is six-bit wide parallel data;
and a fourth D flip-flop 1104 for performing divide-by-five clock sampling on the second spare parallel data to generate fourth parallel data, wherein the fourth parallel data is six-bit wide parallel data.
On the basis of the above embodiment, the data recovery system for detecting a synchronization code further includes:
The synchronous reset circuit 150 is configured to send a synchronous reset signal to locate a synchronous code position in the first set of serial data and the second set of serial data when the detection circuit 130 detects that the transmission type of the first set of serial data and the second set of serial data is that the first set of serial data and the second set of serial data are output simultaneously or that the first set of serial data and the second set of serial data are output non-simultaneously.
In this embodiment, referring to fig. 8A, fig. 8A is a schematic diagram illustrating a positive synchronization code detection according to a fourth embodiment of the present invention. The input serial data contains a K28.5positive synchronous code RD+ (0 x 305) control word, and the data is recovered to the state of FIG. 3A after the clock data recovery circuit. The positive sync code 0x305 breaks apart two 5-bit control words, 0x10 and 0x13, respectively, corresponding to bit1 and bit0 inputs of the demultiplexer. Referring to fig. 8B, fig. 8B is a schematic diagram illustrating negative synchronization code detection according to a fourth embodiment of the present invention. The input serial data contains a K28.5 negative synchronous code RD- (0 x0 FA) control word, and the data is recovered to the state of FIG. 3B after the clock data recovery circuit. The negative synchronization code control word 0x0FA separates two 5-bit control words, 0x0F and 0x0C, respectively, corresponding to bit0 and bit1 inputs of the demultiplexer. Then, after detecting the transmission types of the first group of serial data bit1 and the second group of serial data bit0 through the comparator and the detection circuit, the synchronous reset circuit 150 sends out a synchronous reset signal to position the synchronous code in the first group of serial data and the second group of serial data. The positions of the synchronization codes in the first and second sets of serial data are shown in fig. 8A and 8B.
On the basis of the above embodiment, the data recovery system for detecting a synchronization code further includes:
and a multiplexer 160, configured to perform bit-spaced splicing on the third parallel data and the fourth parallel data according to the synchronization code position and the transmission types of the first set of serial data and the second set of serial data.
In this embodiment, the output data 1 of the demultiplexer and the data 0 are spliced at intervals, and restored to correct original data. Illustratively, referring to FIG. 3A, it is assumed that when the first and second sets of serial data are simultaneously output, bit1 is "Bit1[5], bit1[4], bit1[3], bit1[2], bit1[1]", bit0 is "Bit0[5], bit0[4], bit0[3], bit0[2], bit0[1]", and are spliced in the order of "Bit1[5], bit0[5], bit1[4], bit0[4], bit1[3], bit0[3], bit1[2], bit0[2], bit1[1], bit0[1]", while being Bit-spaced by multiplexers. Referring to FIG. 3B, assume that Bit1 is "Bit1[4], bit1[3], bit1[2], bit1[1], bit1[0]", bit0 is "Bit0[5], bit0[4], bit0[3], bit0[2], bit0[1]", and is spliced in the order of "Bit0[5], bit1[4], bit0[4], bit1[3], bit0[3], bit1[2], bit0[2], bit1[1], bit0[1] when the first group of serial data is output at a clock non-same time.
The embodiment of the invention provides a synchronous code detection system, which is used for comparing and verifying synchronous codes carried in first parallel data and second parallel data converted by a demultiplexer through a comparator, and detecting the transmission types of the first group of serial data and the second group of serial data through a detection circuit under the condition that the synchronous codes are verified to be correct. The embodiment of the invention solves the problem that the first group of serial data and the second group of serial data which are output by the clock data recovery circuit cannot be identified, realizes the correct identification of the two groups of serial data transmission types, and further realizes the effect of correctly dividing a series of signals at a high-speed serial receiving end so as to correctly recover the original data.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (10)
1. A synchronization code detection system, the system comprising: a demultiplexer, a comparator, and a detection circuit; wherein,
The demultiplexer is used for converting the first group of serial data output by the clock data recovery circuit into first parallel data and converting the second group of serial data output by the clock data recovery circuit into second parallel data;
The comparator is connected with the demultiplexer and is used for judging whether the synchronous code carried by the first parallel data is the same as the first group of calibration synchronous codes and whether the synchronous code carried by the second parallel data is the same as the second group of calibration synchronous codes;
The detection circuit is connected with the comparator and is used for detecting the transmission types of the first group of serial data and the second group of serial data according to the judgment result of the comparator; wherein the transmission types of the first group of serial data and the second group of serial data include: the first set of serial data and the second set of serial data are output simultaneously or the first set of serial data and the second set of serial data are output non-simultaneously;
The clock data recovery circuit recovers clock and data from the high-speed serial data stream, the clock data recovery circuit randomly outputs the first group of serial data and the second group of serial data after recovering the data, and the first group of serial data and the second group of serial data recovered by the clock data recovery circuit respectively carry half of positive synchronous codes or half of negative synchronous codes.
2. The system of claim 1, wherein the demultiplexer comprises:
the first shift register is used for converting the first group of serial data into first standby parallel data and taking the upper five bits in the first standby parallel data as the first parallel data;
and the second shift register is used for converting the second group of serial data into second standby parallel data and taking the upper five bits in the first standby parallel data as the second parallel data.
3. The system of claim 1, wherein the comparator comprises: a first comparator, a second comparator, a third comparator, and a fourth comparator; wherein,
The first comparator is used for judging whether the synchronous code carried by the first parallel data is the same as the first group of calibration synchronous codes;
The third comparator is used for judging whether the synchronous code carried by the second parallel data is the same as the second group of calibration synchronous codes or not;
or the second comparator is used for judging whether the synchronous code carried by the first parallel data is the same as the first group of calibration synchronous codes;
The fourth comparator is configured to determine whether the synchronization code carried by the second parallel data is the same as the second set of calibration synchronization codes.
4. The system of claim 3, wherein the system further comprises a controller configured to control the controller,
The detection circuit is used for detecting the transmission types of the first group of serial data and the second group of serial data according to the judging results of the first comparator and the third comparator;
Or detecting the transmission types of the first group of serial data and the second group of serial data according to the judging results of the second comparator and the fourth comparator.
5. The system of claim 4, wherein the detection circuit comprises: the first D trigger, the second D trigger and the RS trigger; the fourth comparator is connected with the first D trigger and the second D trigger, and the first D trigger and the second D trigger are connected with the RS trigger through an AND gate and/or an OR gate; the second comparator is connected with the RS trigger through an AND gate and/or an OR gate; the first comparator is connected with the RS trigger through an AND gate and/or an OR gate; the third comparator is connected with the RS trigger through an AND gate and/or an OR gate.
6. A system according to claim 3, wherein any of the first comparator, the second comparator, the third comparator and the fourth comparator comprises a positive synchronization code comparison unit and a negative synchronization code comparison unit.
7. The system of any one of claims 2-6, wherein the system further comprises:
and the clock frequency dividing circuit is used for carrying out five-frequency division processing on the clock output by the clock data recovery circuit and generating a corresponding five-frequency division clock.
8. The system of claim 2, wherein the demultiplexer further comprises:
The third D trigger is used for sampling the first standby parallel data by a five-frequency division clock to generate third parallel data, wherein the third parallel data is six-bit wide parallel data;
and the fourth D trigger is used for sampling the second standby parallel data by a five-frequency division clock to generate fourth parallel data, wherein the fourth parallel data is six-bit wide parallel data.
9. The system of claim 8, wherein the system further comprises:
And the synchronous reset circuit is used for sending a synchronous reset signal to position synchronous codes in the first group of serial data and the second group of serial data when the detection circuit detects that the transmission types of the first group of serial data and the second group of serial data are the simultaneous output of the first group of serial data and the second group of serial data or the non-simultaneous output of the first group of serial data and the second group of serial data.
10. The system of claim 9, wherein the system further comprises:
and the multiplexer is used for performing bit-spaced splicing on the third parallel data and the fourth parallel data according to the synchronous code position and the transmission types of the first group of serial data and the second group of serial data.
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