CN102065208B

CN102065208B - Realization method of digital audio and video signal SerDes

Info

Publication number: CN102065208B
Application number: CN 201010578465
Authority: CN
Inventors: 耿卫东; 商广辉; 刘艳艳; 孙钟林
Original assignee: Nankai University
Current assignee: Nankai University
Priority date: 2010-12-08
Filing date: 2010-12-08
Publication date: 2013-03-13
Anticipated expiration: 2030-12-08
Also published as: CN102065208A

Abstract

A digital audio and video signal serial deserializer and a realization method thereof belong to the technical field of flat panel display. It can be used in the serial interface circuit of LCD, LCoS, AMOLED and other micro-displays. In the serial deserializer of the present invention, its serial encoding circuit includes an image preprocessing circuit, an adjacent pixel comparator, a similarity encoding circuit, a dissimilarity encoding circuit, a scrambling encoding circuit, a multiplexer 1, and a control clock circuit It is composed of 8 unit circuits such as a synchronous generator; the invention proposes an improved scrambling mechanism based on the similarity of adjacent pixels of the video image, especially for the serial transmission technology of digital video signals, which has simple structure, additional The system overhead is small, and the present invention has the function of simultaneously transmitting audio signals.

Description

A kind of implementation method of digital audio-video signal SerDes

[technical field]:

The invention belongs to technical field of flat panel display, relate to a kind of digital video signal serial deserializer.

[background technology]:

Development along with flat panel display, various high-resolution digital image display devices and mobile media display device become the main flow in market, as the display screen of one of display system key element and the interfacing between the audio video processor, has in recent years very large development, traditional analog video interface such as CVBS, VGA interface etc., can not adapt to the requirement of various high definition display systems and movable display system, just progressively replaced by various Digital Video Interface Technology.The new digital video interface technology such as the HD-SDI that develops rapidly, DVI, HDMI, DiiVA, DisplayPort are just playing an important role at the Contemporary Information display industries, have wide market prospects, in order to satisfy the displaying contents of large information capacity, improve the transmission rate of display interface device circuit, these novel digital interface technology have all adopted high speed data interface (Serial Data Interface, SDI).Because audio video processor and display device all are the data-interfaces that walks abreast, therefore the serial deserializer of two-forty, high efficiency digital audio-video signal is the key technology that realizes the high-speed serial data transmission, switch in order to realize dc balance and to satisfy the needed state of clock recovery, in the middle of prior art, the technology that the high speed serialization deserializer adopts has two kinds, i.e. 8B/10B coding techniques and scrambler coding techniques.Wherein the 8B/10B coding techniques is the American I BM company patent of nineteen eighty-three, it also is most widely used coding techniques, the major defect of this technology is exactly the extra overhead that increases up to 25%, people have proposed the method for concentrated reduction 8B/10B overhead such as 64B66B etc. in recent years, but all to improve hardware design complexity as cost, exchange lower overhead for; Scrambler is that a kind of method that pseudo random sequence is mixed with source code flow realizes the purposes such as conversion, dc balance, and scrambler does not need extra bandwidth.DVI, HDMI adopted the 8b/10b coding techniques, and HD-SDI have adopted the scrambler technology based on transition minimized differential signaling (TMDS) channel.

[summary of the invention]: the purpose of this invention is to provide a kind of serial deserializer and its implementation for the digital audio/video High Speed Serial Transmission Interface, in order to simplify circuit structure, realize the serial transmission of the wired and wireless audio and video signal of high efficiency, two-forty.

Digital audio-video signal SerDes provided by the invention comprises serial code reconciliation circuit string decoding circuit; The serial code circuit application is in data sending terminal, and the decoding circuit that unstrings is applied to data receiver; Link to each other by optical fiber, radio wave external transmission medium between the serial code reconciliation circuit string decoding circuit;

Described serial code circuit comprises as shown in Figure 8:

Image is anticipated circuit: the input that image is anticipated circuit 1 has the digital video signal bus of each N position of RGB, links to each other with the external video treatment circuit; Control signal input CON, CK and OE link to each other with control clock circuit 7; Its output links to each other with neighbor comparator 2;

The neighbor comparator: the input of neighbor comparator 2 has two, and the output that digital video signal bus and the image of the one, 2N position anticipated circuit 1 links to each other, and the 2nd, control signal input S0 links to each other with control clock circuit 7; Its output signal has three groups, links to each other with similitude coding circuit 3, scrambler coding circuit 5 and diversity coding circuit 6 respectively;

The similitude coding circuit; The input of similitude coding circuit 3 links to each other with the output of neighbor comparator 2, and its output links to each other with MUX 1;

The scrambler coding circuit: the input of scrambler coding circuit 5 links to each other with the output of neighbor comparator 2, and its output links to each other with MUX 1;

The diversity coding circuit; The input of diversity coding circuit 6 links to each other with the output of neighbor comparator 2, and its output links to each other with MUX 1;

MUX: the input of MUX 1 links to each other with similitude coding circuit 3, scrambler coding circuit 5, diversity coding circuit 6, synchronizing generator 8 and neighbor comparator 2, and output links to each other with the Serial data receiving end of outside;

Clock control circuit: the input of clock control circuit 7 links to each other with external video clock signal, frame synchronizing signal and line synchronizing signal; Output is anticipated circuit 1, neighbor comparator 2, similitude coding circuit 3, diversity coding circuit 5, scrambler coding circuit 6 and synchronizing generator 8 with image and is linked to each other;

Synchronizing generator: the input of synchronizing generator 8 and outside parallel audio data/address bus, row are synchronously, frame synchronization links to each other with the effective control signal of audio signal; Its output links to each other with MUX 1 with control clock circuit 7;

The described decoding circuit that unstrings comprises: clock data recovery circuit 37, serial data and conversion and clock down conversion circuit 38, identity code identification and data multiplex control circuit 39, similar solution decoding circuit 40, scrambler decoding circuit 41, diversity decoding circuit 42, synchronous and audio signal restore circuit 43 and local clock 44, and the interconnected relationship of foregoing circuit is as shown in Figure 9; The input of clock data recovery circuit 37 links to each other with the outside; The reference clock input links to each other with local clock 44; The synchronised clock that recovers links to each other with clock down conversion circuit 38 with serial data and conversion with the serial data output; Identity code identification and data multiplex control circuit 39 are comprised of 2N+2 bit data latch 7 46, synchronous mark code identification circuit 47 and Data Labels code identification circuit 48; Its parallel data input links to each other with clock down conversion circuit 38 with serial data and conversion with work clock Clock input; Work clock Clock output with similar solution decoding circuit 40, scrambler decoding circuit 41, diversity decoding circuit 42, with audio signal restore circuit 43 respectively link to each other synchronously, and link to each other with the outside as the parallel video clock output signal.

The image of described serial code circuit is anticipated circuit 1 inside and is comprised of tristimulus image data timesharing output control circuit 9, data latches 1 and data latches 2 11; Tristimulus image data timesharing output control circuit 9 odd number pixel data sequentially with the RGB image of timesharing under the control of CON signal and clock signal C K is delivered to data latches 1, and the pixel data of even number order is delivered to data latches 2 11, then when output enable signal OE is effective, simultaneously two pixel datas are outputed to neighbor comparator 2.

Described serial code circuit neighbor comparator 2, inner by with or circuit 12, similitude flag register 13, coding circuit 14 and MUX 2 15 form; 2 pairs of images of neighbor comparator are anticipated the not overlapping neighbor of circuit 1 output, carry out the same exclusive disjunction of step-by-step, and operation result is placed in the N position similitude flag register 13; Numerical value in 14 pairs of similitude flag registers 13 of coding circuit is encoded, when N-1 1 being arranged or when above in this N bit data, 14 output of coding circuit S1S2S3=100, when N-1 0 being arranged or when above in this N bit data, 14 output of coding circuit S1S2S3=010, in other situations, coding circuit 14 output S1S2S3=001; MUX 2 15 is delivered to respectively similitude coding circuit 3, diversity coding circuit 6 and scrambler coding circuit 5 with two not overlapping neighbors under the control of signal S1S2S3, simultaneously the S1S2S3 signal is respectively as the enable signal of similitude coding circuit 3, scrambler coding circuit 5 and diversity coding circuit 6.

Described serial code circuit similitude coding circuit 3 by data latches 3 16, data latches 4 20, step-by-step negate circuit 19, insert circuit 17 and sign every the position and insert circuit 18 and form; When the S1=1 of neighbor comparator 2 output, data on data latches 3 16 and the data latches 4 20 image data lines, wherein the data in the data latches 4 20 are after step-by-step negate circuit 19 is processed, inserting the 1st pixel mixing of circuit 17 neutralizations every the position, form new 2N bit data, regulation 2n+1 position from a high position is the data of the 1st pixel, and the 2n position is the data of the 2nd pixel, and n is less than 8; Sign is inserted circuit 18 and is inserted 10 in 2N bit data front, and data are become the output of 2N+2 Bits Serial code.

Described serial code circuit diversity coding circuit 6 by data latches 5 21, data latches 6 24, insert circuit 22 and sign every the position and insert circuit 23 and form; When the S2=1 of neighbor comparator 2 output, data on data latches 5 21 and the data latches 6 24 image data lines, inserting every the position in the circuit 22 the 1st pixel and the 2nd pixel mixing, form new 2N bit data, regulation 2n+1 position from a high position is the data of the 1st pixel, and the 2n position is the data (n is less than 8) of the 2nd pixel; Sign is inserted circuit 23 and is inserted 01 in 2N bit data front, and data are become the output of 2N+2 Bits Serial code.

Described serial code circuit synchronizing generator 8 can between frame synchronization and row sync period, process and the transmission of digital audio signal, when the H signal of synchronizing generator 8 output and V signal are effective, control clock circuit 7 will be exported the S0 signal, make S1S2S3=000, stop 2 work of neighbor comparator, while similitude coding circuit 3, scrambler coding circuit 5 and diversity coding circuit 6 quit work, MUX 1 is under the control of S4 signal, with synchronous mark code and audio output signal and the serial data output connection of synchronizing generator 8 generations, thus output frame synchronous mark code, row synchronous mark code and serial audio signal.

Identity code identification and the data multiplex control circuit 39 of the described decoding circuit that unstrings are comprised of 2N+2 bit data latch 7 46, synchronous mark code identification circuit 47 and Data Labels code identification circuit 48; Input clock Clock drives 2N+2 bit data latch 7 46 and latchs current data.

The described decoding circuit that unstrings similar solution decoding circuit 40, when control signal E1 is effective, adopted the data handling procedure of similitude coding circuit 3 contraries; Diversity decoding circuit 42 has adopted the data handling procedure of diversity coding circuit 6 contraries when control signal E3 is effective; Synchronously and audio signal restore circuit 44, when control signal E4 is effective, adopted the data handling procedure of synchronizing generator 8 contraries.

The implementation method of above-mentioned digital audio-video signal SerDes, pass through successively following step:

The first, when effective frame synchronization, row synchronously and after vision signal occurs, synchronizing generator 8 will send by MUX 1 the synchronous mark code of frame and row, after only having effective capable synchronous mark code to finish, control clock circuit 7 just can be exported effectively S0, CON, CK and OE signal, starts image and anticipates

circuit

1 and 2 work of neighbor comparator circuit;

The second, the grouping of neighbor: under the control of input clock, image is anticipated circuit 1 with each N bit data timesharing output of RGB of outside input, and the N bit data of first pixel is temporarily stored in data latches 1, the N bit data of the 2nd pixel is temporarily stored in data latches 2 11, and the data parallel with these two neighbors outputs to neighbor comparator 2 again.Then image is anticipated the again video data of temporary the 3rd pixel of circuit 1, forms second group of neighbor with the 4th pixel data, by that analogy;

Three, judge the similitude of every group of neighbor: the data for each group neighbor are carried out same exclusive disjunction, minute three kinds of situations are classified: when the value of the neighbor data of two N positions equates, then the result behind the two data inclusive ORs is complete 1, this situation appears at the zone of video image background or solid color, and the threshold value that we set is to have two neighbors of N-1 and N 1 expression similar; When the value of the neighbor data of two N positions was opposite, then the result behind the two data inclusive ORs was full 0, and this situation appears at the borderline region of video image, and the threshold value that we set is that N-1 and two adjacent datas of N 0 expression are different;

Four, for two neighbors with similitude, carry out similitude coding and process, with one of them pixel step-by-step negate, and insert every the position with the one other pixel step-by-step, form serial data stream output;

Five, for two neighbors with diversity, carry out the diversity coding and process, one of them pixel and one other pixel step-by-step are inserted every the position, form serial data stream output;

Six, in other cases, two neighbors form the 2N bit data, by the scrambler algorithm, form serial data stream output;

Seven, the serial data stream of processing for similitude coding forms the 2N+2 bit data stream in front titled with " 10 "; The serial data stream of processing for diversity coding forms the 2N+2 bit data stream in front titled with " 01 "; The data of processing for scrambler coding form the 2N+2 bit data stream titled with " 11 ";

Eight, between frame synchronization and row sync period, synchronizing generator 8 produces the synchronous mark code of frame and row, through MUX one 4 outputs; Row synchronous mark code is divided into two sections, and between two sections codes, voice data is processed and sent to synchronizing generator 8;

Nine, finally by cross MUX one 4 timesharing pass through optical fiber or radio wave sends frame sync mark code, capable synchronous mark code, serial voice data and serial video data.

Ten, unstring decoding circuit from by optical fiber or radio wave reception to serial data clock data recovery circuit 37, recover data and the identity code of synchronised clock and 2N+2 position;

The 11, by serial data and conversion and clock down conversion circuit 38, conversion produces the parallel data of work clock Clock and 2N+2 position;

The 12, analyze by identity code identification and 39 pairs of parallel 2N+2 bit data of data multiplex control circuit, extract data encoding identity code and synchronous mark code, produce E1, E2, E3, E4 control signal;

The 13, under the control of E1, E2, E3, E4 signal, data are carried out respectively similitude decoding, scrambler decoding, diversity decoding, synchronizing signal decoding and audio signal decoding;

The 14, the video data that obtains of decoding outputs to the external display circuit system under the control of clock signal, frame synchronizing signal and line synchronizing signal; Audio signal, clock signal, frame synchronizing signal and line synchronizing signal directly output to the external display circuit system.

The present invention adopts integral design method, serial code reconciliation circuit string decoding circuit is designed to respectively an integrated circuit, as transmitter and the receiver of transfer of data.Circuit adopts the hardware description language design, and based semiconductor technique realizes.

Advantage of the present invention and good effect:

Serial deserializer provided by the invention has adopted follow-on scrambler algorithm, can adopt the coding method of simplifying when neighbor has similitude or diversity according to the similarity principle of video image neighbor, and other situations adopt the scrambler coding.For background parts, the still image monochromatic areas of view data, adopt similitude or diversity coding, the expense that can save serial deserializer hardware and software, the efficient of raising circuit, the power consumption of reduction circuit, the dc balance characteristic is good.Simultaneously the present invention can realize the Voice ﹠ Video data transfer simultaneously, is specially adapted to Helmet Mounted Display etc.

[description of drawings]:

Fig. 1 is that image is anticipated circuit 1 structured flowchart;

Fig. 2 is neighbor comparator 2 structured flowcharts;

Fig. 3 is similitude coding circuit 3 structured flowcharts;

Fig. 4 is diversity coding circuit 6 structured flowcharts;

Fig. 5 is synchronizing generator circuit 8 structured flowcharts;

Fig. 6 is clock control circuit 7 structured flowcharts;

Fig. 7 is identity code identification and data multiplex control circuit 39 structured flowcharts;

Fig. 8 is serial code circuit structure block diagram;

Fig. 9 is the decoding circuit structured flowchart that unstrings.

[embodiment]:

Embodiment 1:

As shown in Figure 8, the serial code circuit of this digital audio-video signal SerDes is anticipated circuit 1, neighbor comparator 2, similitude coding circuit 3, scrambler coding circuit 5, diversity coding circuit 6, MUX 1, clock control circuit 7 and synchronizing generator 8 by image and is formed, and all element circuits integrate.Wherein:

The input that image is anticipated circuit 1 has the digital video signal bus of each N position of RGB, links to each other with the external video treatment circuit, and control signal CON, CK and OE input link to each other with control clock circuit 7; Its output links to each other with neighbor comparator 2, and the output of data presses 0,1,2,3,4,5 ... one group of nonoverlapping neighbor data of the each output of order to neighbor comparator 2; The input data-interface is each N position of RGB, and the output data-interface is the 2N position, and different according to the standard of input signal, N can be 6 or 8, respectively corresponding RGB565 and RGB888 standard.Image is anticipated circuit 1 inside and is comprised of tristimulus image data timesharing output control circuit 9 and data latches 1, data latches 2 11; Tristimulus image data timesharing output control circuit 9 is under the control of CON and CK signal, the odd number pixel data sequentially with the RGB data of timesharing is delivered to data latches 1, and the pixel data of even number order is delivered to data latches 2 11, then under enable signal OE control, simultaneously two pixels are outputed to neighbor comparator 2.

The input of neighbor comparator 2 has two, and the digital video signal of the one, 2N position links to each other with the output that image is anticipated circuit 1, and the 2nd, control signal S0 input links to each other with control clock circuit 7; Its output has three groups, links to each other with similitude coding circuit 3, scrambler coding circuit 5 and diversity coding circuit 6 respectively.Whether neighbor comparator 2 is the same by two N bit data of bit comparison, provide each identical sign whether of two data, be all mutually 1, be not all 0, and classify according to the data that this sign is anticipated circuit 1 output to image, when flag data has N-1 1 above, then two neighbor data of this group are delivered to similitude coding circuit 3 and process; When flag data has N-1 0 above, then two neighbor data of this group are delivered to diversity coding circuit 6 and process; Otherwise these group neighbor data are delivered to scrambler coding circuit 5 to be processed.Simultaneously neighbor comparator 2 output control signal S1S2S3 are used for starting corresponding coding circuit work, and as the gating control signal of back MUX 1.Neighbor comparator 2 inside are comprised of same or circuit 12, similitude flag register 13, coding circuit 14 and MUX 2 15; Numerical value in 14 pairs of similitude flag registers 13 of coding circuit is encoded, when this N bit data has N-1 1 or when above, 14 output of coding circuit S1S2S3=100, when this N bit data has N-1 0 or when above, 14 output of coding circuit S1S2S3=001, in other situations, coding circuit output S1S2S3=010;

The input of similitude coding circuit 3 links to each other with the output of neighbor comparator 2, and its output links to each other with MUX 1.The sign that provides when neighbor comparator 2 is when N-1 1 is above, S1S2S3=100, the data of two neighbors of this group are delivered to similitude coding circuit 3, after processing through the similitude coding, data transformation is become the serial data of a kind of 2N+2 position, through MUX one 4 outputs.Similitude coding circuit 3 by data latches 3 16, data latches 4 20, step-by-step negate circuit 19, insert circuit 17 and sign every the position and insert circuit 18 and form; When the S1=1 of neighbor comparator 2 output, data on data latches 3 16 and the data latches 4 20 image data lines, the data of the 2nd pixel are after step-by-step negate circuit 19 is processed, inserting the 1st pixel mixing of circuit 17 neutralizations every the position, form new 2N bit data, regulation 2n+1 position from a high position is the data of the 1st pixel, and the 2n position is the data (n is less than 8) of the 2nd pixel; Sign is inserted circuit and is inserted 10 in 2N bit data front, and data are become the output of 2N+2 Bits Serial code.

The input of scrambler coding circuit 5 links to each other with the output of neighbor comparator 2, and its output links to each other with MUX 1.When the flag data that provides when neighbor comparator 2 is 1～(N-2) individual 1 or 1～(N-2) individual 0, S1S2S3=010, the data of two neighbors of this group are processed by scrambler coding circuit 5, when the S3=1 of neighbor comparator 2 output, scrambler coding circuit 5 becomes the serial data of a kind of 2N+2 position with data transformation, through MUX one 4 outputs.

The input of diversity coding circuit 6 links to each other with the output of neighbor comparator 2, and its output links to each other with MUX 1.The sign that provides when neighbor comparator 2 is when N-1 0 is above, S1S2S3=001, the data of two neighbors of this group are delivered to diversity coding circuit 6, after processing through the diversity coding, data transformation is become the serial data of a kind of 2N+2 position, through MUX one 4 outputs.Diversity coding circuit 6 by data latches 5 21, data latches 6 24, insert circuit 22 and sign every the position and insert circuit 23 and form; When the S2=1 of neighbor comparator 2 output, data on data latches 5 21 and the data latches 6 24 image data lines, inserting every the position in the circuit 22 the 1st pixel and the 2nd pixel mixing, form new 2N bit data, regulation 2n+1 position from a high position is the data of the 1st pixel, and the 2n position is the data (n is less than 8) of the 2nd pixel; Sign is inserted circuit 23 and is inserted 01 in 2N bit data front, and data are become the output of 2N+2 Bits Serial code.

The data input pin of MUX 1 links to each other with similitude coding circuit 3, scrambler coding circuit 5, diversity coding circuit 6, synchronizing generator 8, and output links to each other with the serial interface receiving end of outside.MUX 1 is according to the numerical value of control signal S1S2S3S4, and the code stream similitude coding circuit 3, scrambler coding circuit 5, diversity coding circuit 6 and synchronizing generator 8 outputs of timesharing is sent to external circuit.MUX 1 can be under the control of the control signal S1S2S3 that neighbor comparator 2 is exported, the serial data bit stream of the selection similitude coding circuit 3 of timesharing, scrambler coding circuit 5 and 6 outputs of diversity coding circuit; When S1S2S3=100, the 2N+2 Bits Serial code of similitude coding circuit 3 outputs is with sign " 10 " beginning, when S1S2S3=001. the 2N+2 Bits Serial code of scrambler coding circuit 5 outputs is with sign " 11 " beginning, and when S1S2S3=010, the 2N+2 Bits Serial code of diversity coding circuit 6 outputs is with sign " 01 " beginning.

Synchronizing generator 8 has 5 inputs, effectively links to each other with the high-frequency clock CLK of clock control circuit 7 outputs with frame synchronizing signal, line synchronizing signal, parallel audio input signal, the audio signal of external circuit respectively.Its output signal has 4, frame synchronization V signal, the synchronous H signal of row link to each other with clock control circuit 7, be used for controlling the synchronous of clock circuit and vision signal, another control signal S4 links to each other with MUX 1 with the identity code output, and the timesharing of control Port Multiplier receives synchronous mark code and audio signal.

Clock control circuit 7 has 3 inputs, link to each other with frame synchronization V, the synchronous H of row of external video clock input signal and synchronizing generator 8 outputs respectively, the video clock input signal is used for the reference clock of inner phase-locked loop, the synchronous H of row and frame synchronization V signal Drive and Control Circuit are so that the vision signal of the output signal of clock control circuit 7 and input is synchronous; Its output has 5 signals, and CLK is the high speed serialization clock, links to each other with synchronizing generator 8, similitude coding circuit 3, scrambler circuit 5, diversity coding circuit 6, as the master clock of serial link and follow-up transmitter driving circuit; S0 signal controlling neighbor comparator 2 when S0 is effective, enables 2 work of neighbor comparator, and during audio video synchronization, suspends the work of neighbor comparator 2; The CON signal is the enable signal that image is anticipated circuit 1 image data, and image was anticipated the video data that circuit 1 gathers outside input when the CON signal was effective; The CK signal is the work clock of RGB data timesharing output circuit, is obtained by the external video clock multiplier; The OE signal is the control signal that neighbor comparator 2 reads the input data, and when the OE signal was effective, image was anticipated circuit 1 data of 2N position are driven on the output line.

Embodiment 2:

The realization of the serial code circuit of this serial digital audio frequency and video serial deserializer is successively through step what follows:

circuit

1 and 2 work of neighbor comparator circuit;

Three, judge the similitude of every group of neighbor: the data for each group neighbor are carried out same exclusive disjunction, minute three kinds of situations are classified: when the value of the neighbor data of two N positions equates, result behind the two data inclusive ORs is complete 1, this situation appears at the zone of video image background or solid color, and the threshold value that we set is to have two neighbors of N-1 and N 1 expression similar; When the value of the neighbor data of two N positions was opposite, the result behind the two data inclusive ORs was full 0, and this situation appears at the borderline region of video image, and the threshold value that we set is that N-1 and two adjacent datas of N 0 expression are different;

Embodiment 3:

The realization of the serial code of given figure word tone video serial deserializer, get N=8, corresponding RGB888 video standard is such as embodiment 1, when signal CON is effective, image is anticipated circuit 1 under the control of CK clock signal, time-division processing RGB view data, to each primary color image, the video data of 2 neighbors of continuous acquisition, and when the OE signal is effective, the neighbor comparator 2 of the back that parallel 16 bit data with 2 neighbors are exported.

After neighbor comparator 2 receives two neighbor video datas, two 8 data communication device crossed with exclusive disjunction circuit 12 carry out same exclusive disjunction, and the result of computing is latched in the similitude flag register 13, the numerical value of 14 pairs of similitude flag registers of coding circuit is encoded, and output control signal S1S2S3, when S0=1, S1S2S3=000; When S0=0, if similitude flag register 13 in have 7 or 81 then S1S2S3=100, if content of registers has 7 or 80, S1S2S3=001 then, S1S2S3=010 in other situations.If S1S2S3=000, MUX 2 15 is closed the data output channel; If S1S2S3=100, data output to the similitude coding circuit through MUX 2 15; If S1S2S3=001, data output to the diversity coding circuit through MUX 2 15; If S1S2S3=010, data output to the scrambler coding circuit through MUX 2 15.

Similitude coding circuit 3 is enabled when S1=1, data latches 3 16 latchs the 1st 8 digital video data, data latches 4 20 latchs the 2nd 8 digital video data, element circuit 19 with the numerical value step-by-step negate in the data latches 4 20 after, by inserting circuit 17 every the position with synthetic 16 bit data of two data, 8 bit data in the data latches 3 16 are D15D13 of synthetic rear 16 bit data ... D5D3D1,8 bit data in the data latches 4 20 are D14D12 of synthetic rear 16 bit data ... D4D2D0.It is a kind of parallel-to-serial converters that sign is inserted circuit 18, the serial data output that the insertion 10 rear formation of fixing in 16 bit data fronts are one group 18.

Diversity coding circuit 6 is enabled when S3=1, data latches 5 21 latchs the 1st 8 digital video data, data latches 6 24 latchs the 2nd 8 digital video data, by inserting circuit 22 every the position with synthetic 16 bit data of two data, 8 bit data in the data latches 5 21 are D15D13 of synthetic rear 16 bit data ... D5D3D1,8 bit data in the data latches 6 24 are D14D12 of synthetic rear 16 bit data ... D4D2D0.It is a kind of parallel-to-serial converters that sign is inserted circuit 23, the serial data output that the insertion 01 rear formation of fixing in the front of 16 bit data is one group 18.

In addition when S2=1, start scrambler coding circuit 5, the data of two neighbors to input do not carry out inserting every the position, but by the data of the 1st pixel the data of front (most-significant byte) the 2nd pixel after order, carry out 16 scrambler computings, the serial data output that the insertion 11 rear formation of fixing in 16 scrambler data fronts that generate at last are one group 18.

Embodiment 4:

The synchronizing generator 8 of given figure word tone video serial deserializer and the workflow of clock control circuit 7 are as follows:

The structure of synchronizing generator 8 as described in Example 1, the implementation process of synchronizing generator 8 is as follows: the first step, externally frame synchronizing signal is effectively when (high level), Port Multiplier 30 is delivered to synchronous mark code and audio output with 18 fractional frequency signals of CLK, output frame synchronous mark code, this identity code will continue between the high period of frame-synchronizing impulse; Second step; Externally effectively when (high level), parallel-to-serial converter 27 latchs the voice data of input to line synchronizing signal, and delivers to scrambler coding circuit 29 and process; The 3rd step, externally line synchronizing signal is effectively when (high level) and external frame synchronizing signal invalid (low level), timer 28 regularly begins, in 512 clk cycles, timer 28 output signal T are low level, this moment, Port Multiplier 30 was delivered to synchronous mark code and audio output with 9 fractional frequency signals of CLK, the leading portion of output row synchronous mark code; The 4th step, externally line synchronizing signal is effectively when (high level) and external frame synchronizing signal invalid (low level), timer 28 through 512 clk cycles after output signal T be high level, this moment is at signal T=1, H=1, when V=0 satisfied, Port Multiplier 30 was with output and synchronous mark code and the audio output connection of scrambler coding circuit 29,2 18 Bits Serial voice datas of continuous wave output; The 5th step, externally line synchronizing signal is effectively when (high level) and frame synchronizing signal invalid (low level), timer 28 through 476 clk cycles regularly after output signal T be low level, Port Multiplier 30 send synchronous mark code and audio output with 9 fractional frequency signals of CLK, the back segment of output row synchronous mark code, and be continued until that horizontal synchronizing pulse H occurs till the low level; In the 6th step, during synchronous and capable synchronized void (low level), synchronizing generator 8 is in wait state, and exports S0=0 when external frame.

The circuit structure of clock control circuit 7 as described in Example 1, the implementation process of clock control circuit 7 is as follows: be between high period at frame synchronizing signal V or line synchronizing signal H, by or the signals of door 32 outputs make control circuit 34 output S0=1, suspend neighbor comparator 2, show that be between sync period this moment; All be between low period at frame synchronizing signal V and line synchronizing signal H, or the signals of door 32 outputs make control circuit 34 output S0=0, start neighbor comparator 2, control circuit 34 output CON signals, CK signal and OE signal are effective simultaneously; The video clock input signal makes phase-locked loop 35 work together as reference clock and local clock 33, and output master clock CLK; All be between low period at frame synchronizing signal V and line synchronizing signal H, and control circuit 34 can't detect the video clock input signal, then showing does not have the signal input, and 34 closing high-speed clock driver circuits 36 of control circuit are to reduce power consumption.

Embodiment 5:

As shown in Figure 9, this digital audio-video signal SerDes unstring decoding circuit by clock data recovery circuit 37, serial data and conversion and clock down conversion circuit 38, identity code identification and data multiplex control circuit 39, similar solution decoding circuit 40, scrambler decoding circuit 41, diversity decoding circuit 42, synchronously and audio signal restore circuit 43 and local clock 44 form.

Externally the vision signal of input is in the RGB888 form situation, clock data recovery circuit 37 recovers the serial code stream of 18 words from continuous serial data bit stream, output to serial data and conversion and clock down conversion circuit 38, switching state according to serial code stream recovers the high-speed synchronous clock simultaneously, outputs to serial data and conversion and the clock of clock down conversion circuit 38 as serial data and conversion.

Serial data and conversion and clock down conversion circuit 38 under the synchronised clock control that clock data recovery circuit 37 recovers, become 18 Bits Serial code conversions 18 parallel code to output to identity code identification and data multiplex control circuit 39; And synchronised clock is carried out 18 frequency divisions process, form the needed work clock of parallel data, as the reference clock of subsequent decoding circuit and outside reading out data.

Identity code identification is comprised of 18 bit data latchs 7 46, synchronous mark code identification circuit 47 and Data Labels code identification circuit 48 with data multiplex control circuit 39; Synchronous mark code identification circuit 47 reads 18 data, judge whether 18 bit data are full 0 or complete 1, when not having full 0 or complete 1 to occur, then there is not the synchronous mark code, thereby output signal E4=0, when per 18 0 then 18 1 data flow occurs, then be judged as frame synchronizing signal and output signal E4=1 occurs; When per 90 then 91 data flow occurs, then being judged as line synchronizing signal occurs, synchronous mark code identification circuit 47 timer internal startup work this moment, catch the back segment of leading portion, voice data and the row synchronous mark code of row synchronous mark code, and output signal E4=1, and by output signal T, select the output of audio signal; Data Labels code identification circuit 48 reads the highest 2 of 18 bit data, when high 2 bit data are 10, output signal E1=1 then, send similar solution decoding circuit 40 to decode 18 bit data, when high 2 bit data are 11, output signal E2=1 then, send scrambler decoding circuit 41 to decode 18 bit data, when high 2 bit data were 01, then output signal E3=1 sent diversity decoding circuit 42 to decode 18 bit data.

Synchronously and the parallel video data exported of the signal (frame synchronizing signal Vs, line synchronizing signal Hs and voice data) of audio signal restore circuit 43 outputs and similar solution decoding circuit 40, scrambler decoding circuit 41, diversity decoding circuit 42, and the reference clock Clock that works outputs to external circuit together.

Claims

1. an implementation method of a digital audio-video signal serial deserializer, characterized in that the method passes through the following steps successively:

First, after effective frame synchronization, horizontal synchronization and video signal appear, synchronous generator (8) will send the synchronous mark code of frame and row by multiplexer one (4), only valid line synchronous mark code ends Later, the control clock circuit (7) will output valid SO, CON, CK and OE signals, start the image preprocessing circuit (1) and the adjacent pixel comparator circuit (2) to work, wherein the SO signal controls the adjacent pixel Comparator (2), when SO is valid, enables the adjacent pixel comparator (2) to work, the CON signal is the enabling signal for the image preprocessing circuit (1) to collect data, and the OE signal is the adjacent pixel comparator (2) ) read the control signal of the input data, and the image preprocessing circuit (1) processes the red, green and blue image data in time-sharing under the control of the CK clock signal;

Second, the grouping of adjacent pixels: under the control of the input clock, the image preprocessing circuit (1) outputs the N-bit data of red, green and blue input externally in time division, and temporarily stores the N-bit data of the first pixel Data latch one (10), temporarily store the N-bit data of the second pixel in data latch two (11), and then output the data of these two adjacent pixels to the adjacent pixel comparator (2) in parallel Then image preprocessing circuit (1) temporarily stores the video data of the 3rd pixel again, forms the second group of adjacent pixels with the 4th pixel data, and so on;

Third, judge the similarity of each group of adjacent pixels: perform the same OR operation on the data of each group of adjacent pixels, and classify in two cases: when the values of two N-bit adjacent pixel data are equal, then The result of the two data "exclusive OR" is all 1, this situation appears in the background of the video image or a single color area, the set threshold is N-1 or N 1 means that two adjacent pixels are similar; when two When the values of N-bit adjacent pixel data are opposite, the result of the two data "exclusive OR" is all 0. This situation occurs in the border area of the video image, and the set threshold is N-1 or N 0s. Indicates that two adjacent data are different;

Fourth, for two adjacent pixels with similarity, perform similarity encoding processing, invert one of the pixels bit by bit, and insert it with the other pixel bit by bit to form a serial data stream output;

Fifth, for two adjacent pixels with dissimilarity, perform dissimilarity coding processing, insert one pixel and the other pixel at intervals to form a serial data stream output;

Sixth, in other cases, two adjacent pixels form 2N-bit data, and through the scrambling algorithm, a serial data stream output is formed;

Seventh, for the serial data stream processed by the similarity encoding process, add "10" in front to form a 2N+2 bit data stream; for the serial data stream processed by the dissimilarity encoding process, add "01" in front to form a 2N+ 2-bit data stream; the scrambled coded data is prefixed with "11" to form a 2N+2-bit data stream;

The eighth, during frame synchronization and line synchronization, synchronous generator (8) produces the synchronous sign code of frame and line, through multiplexer one (4) output; Line synchronous sign code is divided into two sections, in two sections of codes Between, synchronous generator (8) processes and transmits audio frequency data;

Ninth, send frame synchronization flag code, line synchronization flag code, serial audio data and serial video data through optical fiber or radio wave at last through multiplexer one (4) time-division;

Tenth, deserialization decoding circuit recovers synchronous clock and 2N+2 bit data and sign code from serial data received by optical fiber or radio wave in clock data recovery circuit (37);

Eleventh, by data serial-to-parallel conversion and clock down-conversion circuit (38), conversion produces the parallel data of operating clock Clock and 2N+2 positions;

Twelfth, analyze the parallel 2N+2 bit data by identification code identification and data multiplex control circuit (39), extract data encoding identification code and synchronous identification code, produce E1, E2, E3, E4 control signal;

Thirteenth, under the control of E1, E2, E3, and E4 signals, perform similarity decoding, scrambling decoding, dissimilarity decoding, synchronization signal decoding, and audio signal decoding on the data;

Fourteenth, the decoded video data is output to the external display system circuit under the control of the clock signal, frame synchronization signal and line synchronization signal; the audio signal, clock signal, frame synchronization signal and line synchronization signal are directly output to the external display system circuit.