CN108305898A - Metal oxide semiconductor element for improving threshold voltage slide and manufacturing method thereof - Google Patents

Abstract

The invention provides a metal oxide semiconductor element for improving the threshold voltage glide and a manufacturing method thereof, comprising the following steps: the device comprises a well, an insulating structure, a grid, two lightly doped diffusion regions, a source electrode, a drain electrode and a compensation doped region. The offset doping region is substantially adjacent to at least a portion of the recessed region of the insulating structure along the length of the channel. Viewed from the cross-sectional view, the junction of the compensation doping region and the insulating structure along the channel length direction has doping widths respectively inside and outside the device region in the channel width direction, and each doping width is not greater than 10% of the width. Viewed from the cross-sectional view, the depth of the offset doped region in the channel length direction, which is calculated from the upper surface and downward along the vertical direction, is not deeper than the depth of the well calculated from the vertical direction and downward.

Description

Metal-oxide-semiconductor device with improved threshold voltage drop and manufacturing method thereof

technical field

The present invention relates to a metal oxide semiconductor element and its manufacturing method for improving critical voltage drop, in particular to a compensation doping region adjacent to a recessed region of an insulating structure along the channel length direction to improve the metal oxide semiconductor element The critical voltage drop phenomenon.

Background technique

There is a disadvantage of the existing metal oxide semiconductor (MOS) device: if the existing metal oxide semiconductor device is small in size, especially when the channel width of the existing metal oxide semiconductor device is small , at the junction of the insulating structure and the element region in the channel width direction in the existing metal oxide semiconductor element, a recessed region of the insulating structure will be formed. During the conduction operation, the electric field is relatively high compared to other parts of the element region, and It is easy to generate an inversion layer early and turn on. As a result, a threshold voltage roll-off phenomenon occurs in the existing metal oxide semiconductor device, which makes the characteristics of the existing metal oxide semiconductor device unstable and degrades the performance of the device.

In view of this, the present invention proposes a metal oxide semiconductor element capable of improving critical voltage drop and its manufacturing method, by utilizing the compensatory doped region adjacent to the recessed region of the insulating structure along the channel length direction, to improve the metal oxide semiconductor The critical voltage drop phenomenon of the component.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies and defects of the prior art, and propose a metal oxide semiconductor element and its manufacturing method that can improve the threshold voltage drop, by using the compensation doping adjacent to the recessed region of the insulating structure along the channel length direction region to improve the threshold voltage drop phenomenon of metal oxide semiconductor devices.

In order to achieve the above object, from one point of view, the present invention provides a metal oxide semiconductor (MOS) device with improved critical voltage drop, comprising: a substrate with an insulating structure to define a device region , and the substrate has an upper surface, wherein, viewed from a first cross-sectional view formed along a first section line parallel to a channel width direction, the insulating structure has a recessed region of the insulating structure, and the recessed region of the insulating structure is located at The junction of the insulating structure and the element region in the channel width direction, wherein the element region has a width in the channel width direction; a well, having a first conductivity type, is formed on the upper surface below the upper surface In the substrate; a grid is formed on the upper surface, and in a vertical direction, the grid is stacked and connected to the upper surface, wherein it is formed along a second section line parallel to a channel length direction As seen in the second cross-sectional view, the gate is located in the element region, the channel length direction is perpendicular to the channel width direction, and the second section line is perpendicular to the first section line; a source electrode and a drain electrode each have The second conductivity type, in the length direction of the channel, the source and the drain are located on the outer two sides below the gate; two lightly doped diffusions of the same conductivity type as the source and the drain , LDD) regions, respectively located on both sides below the gate; and a compensation doped (compensation doped) region, having a first conductivity type, formed in the substrate under the upper surface, wherein the compensation doped region is approximately It is adjacent to at least part of the recessed region of the insulating structure along the length direction of the channel; wherein, viewed from the first cross-sectional view formed along the first cross-hatching line, the compensation doped region is adjacent to the insulating structure along the length direction of the channel In the direction of the channel width, the junction has a doping width inside and outside the element region respectively, and each doping width is not more than 10% of the width; wherein, formed along the second section line From the second cross-sectional view, the compensation doping region has a depth calculated downwards from the upper surface along the vertical direction in the channel length direction, which is not deeper than that of the well downwards from the vertical direction Calculate the depth; thereby, in the part of the element region adjacent to the recessed region of the insulating structure, in the conduction operation, compared with other element regions, the inversion layer is not generated earlier and turned on, so as to improve the metal oxidation The threshold voltage drop phenomenon of semiconductor devices.

To achieve the above object, from another point of view, the present invention provides a method for manufacturing a metal oxide semiconductor device with improved threshold voltage drop, comprising: providing a substrate having an insulating structure to define a device region, and The substrate has an upper surface, wherein, viewed in a first cross-sectional view along a first cross-sectional line parallel to a channel width direction, the insulating structure has an insulating structure recessed region located on the insulating structure The junction of the structure and the element region in the channel width direction, wherein the element region has a width in the channel width direction; a well is formed, which has the first conductivity type, and the well is located under the upper surface In the substrate; form a grid, which is located on the upper surface, and in a vertical direction, the grid is stacked and connected to the upper surface, wherein, along a second section parallel to a channel length direction The gate is located in the element region, the channel length direction is perpendicular to the channel width direction, and the second section line is perpendicular to the first section line; a source and a drain are formed electrodes, each of which has a second conductivity type, and in the direction of the channel length, the source and the drain are located on the outer two sides below the gate; two light electrodes of the same conductivity type as the source and the drain are formed doped diffusion (lightly doped diffusion, LDD) regions, which are respectively located on both sides below the gate; and forming a compensation doped region, which has a first conductivity type, and the compensation doped region is located on the upper surface In the lower substrate, wherein the compensatory doped region is substantially adjacent to at least part of the recessed region of the insulating structure along the length direction of the channel; wherein, viewed from the first cross-sectional view formed along the first cross-hatching line, the The junction of the compensating doped region along the channel length direction and the insulating structure has a doping width in the channel width direction, inside and outside the device region, and each doping width is not greater than 10 of the width. %; where, viewed from the second cross-sectional view formed along the second cross-section line, the compensation doped region has a value calculated downwards from the upper surface along the vertical direction in the direction of the channel length The depth is not deeper than the depth of the well calculated downward from the vertical direction; thereby, in the part of the element region adjacent to the recessed region of the insulating structure, in the conduction operation, compared with other element regions, no The inversion layer is formed earlier and turned on, so as to improve the threshold voltage drop phenomenon of the metal oxide semiconductor device.

In a preferred implementation form, the impurity concentration of the first conductivity type in the compensation doped region is greater than the concentration of the impurity of the first conductivity type in the well.

In a preferred implementation form, the insulating structure includes a shallow trench isolation (STI) structure.

In a preferred implementation form, viewed from a top view, the compensation doped region completely covers the junction between the element region and the insulating structure in the channel length direction.

The following will be described in detail through specific examples, when it is easier to understand the purpose, technical content, characteristics and effects of the present invention.

Description of drawings

1A and 1B show an embodiment of the cross-sectional view of the present invention formed along a section line parallel to the channel length direction;

Fig. 2 shows the schematic top view of the present invention;

Fig. 3 shows an embodiment of the sectional view of the present invention formed along a section line parallel to the channel width direction;

Figure 4 shows a schematic top view of the present invention;

Figure 5 shows a schematic top view of the present invention;

6 shows a schematic diagram of the electrical characteristics of the present invention, which can improve the threshold voltage roll-off of metal oxide semiconductor devices compared with the prior art;

FIG. 7 is a schematic diagram showing the electrical characteristics of the turn-on operation according to the prior art and the present invention.

Explanation of symbols in the figure

200 metal oxide semiconductor components

21 Substrate

21a upper surface

21b lower surface

22 wells

23 Insulation structure

23a Component area

23b Insulation structure recessed area

24 grid

24a Dielectric layer

24b stack layer

24c spacer

25a, 25b lightly doped diffusion region

26 source

27 drain

41 Compensation doped region

AA’ section line

BB’ section line

D depth

H depth

N1, N2 boundary

Pe, Pi doping width

W width

Detailed ways

The aforementioned and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The drawings in the present invention are all schematic, mainly intended to represent the structure of components and the connection relationship between front, back, up and down of each layer, as for the shape, thickness and width, they are not drawn to scale.

Please refer to Figures 1A and 1B and compare Figures 2-3. 1A and 1B respectively show a top view and a cross-sectional view of an embodiment of the present invention along a section line parallel to the channel length direction. Figure 2 shows a schematic top view of the present invention. FIG. 3 shows an embodiment of a cross-sectional view of the present invention along a cross-sectional line parallel to the channel width direction.

First, please refer to Figures 1A and 1B and compare Figures 2-3. 1A and 1B respectively show a top view and a cross-sectional view of an embodiment of the present invention along a section line AA' parallel to the channel length direction. It should be noted that, in order to clearly express the range of the operating region 23 a , FIG. 1A only shows a schematic top view of the insulating structure 23 and the gate 24 , so as to easily understand the range of the operating region 23 a defined by the insulating structure 23 .

As shown in FIGS. 1A and 1B, the metal oxide semiconductor (metal oxide semiconductor, MOS) device 200 of the present invention is formed in a substrate 21, and the substrate 21 has an upper surface 21a in a vertical direction (as shown by the dotted line in FIG. 1B ). ) and the lower surface 21b. The MOS device 200 includes a well 22 , an insulating structure 23 , a gate 24 , lightly doped diffusion (LDD) regions 25 a and 25 b , a source 26 , and a drain 27 . The gate 24 includes a dielectric layer 24a, a stack layer 24b, and a spacer layer 24c. Wherein, the substrate 21 is, for example but not limited to, a P-type silicon substrate, and may also be other semiconductor substrates. Well 22 is formed under upper surface 21a. An insulating structure 23 is formed on the upper surface 21a to define an operating region 23a. The operating region 23a is the main active region when the MOS device 200 operates, and its range is shown in FIG. 1A and FIG. 1B .

In an embodiment, the insulating structure 23 may be, for example but not limited to, a shallow trench isolation (STI) structure as shown.

The conductivity type of the well 22 is, for example but not limited to, P type. The lightly doped diffusion regions 25a and 25b, the source 26 and the drain 27 are formed under the upper surface 21a, and their conductivity type is, for example but not limited to, N type. The gate 24 is stacked and connected on the upper surface 21 a in a vertical direction, between the source 26 and the drain 27 .

From the cross-sectional view of FIG. 1B , the gate 24 is located in the device region 23 a. Wherein, the stacking layer 24b divides the operating area 23a into a first side and a second side, as indicated by thick arrows in FIGS. 1A and 1B . The dielectric layer 24a is formed on the upper surface 21a and connected to the upper surface 21a. The stack layer 24b is formed on the dielectric layer 24a and includes conductive material, which is used as an electrical contact of the gate 24 and also serves as a self-alignment shield when forming the lightly doped diffusion regions 25a and 25b. The spacer layer 24c is formed on the outer upper surface 21a of the sidewall of the stacking layer 24b, covers the sidewall of the stacking layer 24b, includes insulating material, and can also be used as a self-alignment shield when forming the source 26 and the drain 27 .

In the channel length direction, the source 26 and the drain 27 are respectively located on the first side and the second side of the outer two sides below the gate 24 . The source electrode 26 is formed in the substrate 21 under the upper surface 21 a of the first side, and viewed from the top view of FIG. 2 , part of the source electrode 26 overlaps with the spacer layer 24 c near the first side. The drain electrode 27 is formed in the substrate 21 under the upper surface 21 a of the second side, and from the top view of FIG. 2 , part of the drain electrode 27 overlaps with the spacer layer 24 c near the second side.

The lightly doped diffusion regions 25 a and 25 b are respectively located on two sides below the gate 24 . The lightly doped diffusion region 25a is formed in the substrate 21 under the upper surface 21a of the first side, and from the top view of FIG. 2, at least part of the lightly doped diffusion region 25a overlaps with the stack layer 24b. The lightly doped diffusion region 25a completely overlaps with the stack layer 24b. The lightly doped diffusion region 25b is formed in the substrate 21 under the upper surface 21a of the second side, and from the top view of FIG. 2, at least part of the lightly doped diffusion region 25b overlaps with the stack layer 24b. The lightly doped diffusion region 25b completely overlaps with the stack layer 24b.

Next, please refer to Figure 3 and compare it to Figure 2. Fig. 3 shows an embodiment of the cross-sectional view of the present invention along the section line BB' parallel to the channel width direction. Wherein, viewed from the top view in Fig. 2, the channel length direction is perpendicular to the channel width direction, and the section line BB' is perpendicular to the section line AA'.

From the cross-sectional view of FIG. 3 , the insulating structure 23 has an insulating structure recessed region 23b. The insulating structure recessed region 23b is located at the junction of the insulating structure 23 and the element region 23a in the channel width direction (please refer to the top view in FIG. 2, the dotted lines shown in FIG. 2 indicate the upper borders N1 and N2 represent the junction). From the top view of FIG. 2 , the device region 23 a has a width W in the channel width direction.

The main difference between the present invention and the prior art is that in the conduction operation, in order to reduce the electric field intensity in the recessed region 23b of the insulating structure so that the inversion layer is not generated when a relatively low gate voltage is applied, In order to improve the threshold voltage drop phenomenon of the MOS device 200 , as shown in FIG. 3 , in this embodiment, a compensation doped region 41 is formed in the substrate 21 . The compensation doped region 41 is, for example but not limited to, P-type, and is formed in the substrate 21 under the upper surface 21 a. It should be noted that, in one embodiment, the impurity concentration in the compensation doped region 41 is, for example but not limited to, P-type impurity concentration greater than that in the well 22 , for example but not limited to.

Please refer to Figure 5 and compare it to Figure 3. Figure 5 shows a schematic top view of the present invention. In order to make the drawing clearer and easier to understand, compared with FIG. 2 , FIG. 5 omits some elements in FIG. 2 , and only shows the insulating structure 23 , the element region 23 a , the compensating doped region 41 and the stacked layer 24 b. It is worth noting that, in one embodiment, as viewed from the cross-sectional view of FIG. 3 compared with the top view of FIG. Top view Figure 2). However, in another embodiment, the compensatory doped region 41 may also completely cover the junction between the device region 23 a and the insulating structure 23 in the channel length direction.

Please refer to Figure 4 and compare it to Figure 3. Figure 4 shows a schematic top view of the present invention. In order to make the drawing clearer and easier to understand, compared with FIG. 2, FIG. 4 omits some elements in FIG. 27. Stacking layer 24b and spacer layer 24c. From the cross-sectional view of FIG. 3 compared with the top view of FIG. 4, the junction of the compensating doped region 41 along the channel length direction and the insulating structure 23 has a doping width Pi inside the element region 23 in the channel width direction and in the element region The outside of 23 has a doping width Pe (also refer to the cross-sectional view FIG. 3 and the top view FIG. 2 ). It should be noted that the doping width Pi in the present invention is not greater than 10% of the width W of the device region 23a in the channel width direction. Moreover, the doping width Pe in the present invention is not greater than 10% of the width W of the device region 23a in the channel width direction. That is, in the present invention, the doping width Pi≤width W, and the doping width Pe≤width W.

Please refer to FIG. 1B and compare with FIG. 2 . From the cross-sectional view of FIG. 1B compared with the top view of FIG. 2 , the well 22 has a depth D calculated downwards from the upper surface 21 a along the vertical direction. Please refer to Figure 3 and compare it to Figure 2. From the cross-sectional view of FIG. 3 compared with the top view of FIG. 2 , the compensation doped region 41 has a depth H in the direction of the channel length, starting from the upper surface 21 a and counting downwards along the vertical direction. It should be noted that the depth H of the compensation doped region 41 in the present invention is not deeper than the depth D of the well 22 . That is, in the present invention, depth H≦depth D.

The main difference between the present invention and the prior art is that the compensatory doping region 41 is provided at the adjacent position along the channel length direction and at least part of the insulating structure recessed region 23b (viewed from the cross-sectional view in FIG. 3 and the top view in FIG. 5 ) , in the conduction operation of the present invention, compared with other device regions, the inversion layer will not be generated earlier to conduct conduction. Therefore, the present invention can improve the threshold voltage drop phenomenon of the MOS device 200 .

Please refer to FIG. 6 , which shows a schematic diagram of the electrical characteristics of the present invention which can improve the threshold voltage drop of the metal oxide semiconductor device compared with the prior art. Wherein, the characteristic curve of the MOS device in the prior art is a solid line; while the characteristic curve of the MOS device 200 according to the present invention is a gray dotted line. First look at the threshold voltage. The threshold voltage of the MOS element in the prior art has an obvious threshold voltage drop phenomenon when the channel width is reduced, but the MOS element 200 according to the present invention significantly improves the threshold voltage drop phenomenon. For the same threshold voltage element, according to the present invention, a MOS element with a shorter channel width than the prior art can be selected, as indicated by the dotted line in the figure. Therefore, according to the present invention, the required size of the element is smaller, and the operation speed of the element is faster, which are advantages of the present invention over the prior art.

Please refer to FIG. 7 , which shows a schematic diagram of electrical characteristics of sub-threshold conduction operations according to the prior art and the present invention. Wherein, the characteristic curve of the MOS element in the prior art is a solid line curve connected by circular nodes; while the characteristic curve of the MOS element according to the present invention is a dotted line curve. As shown in FIG. 7 , compared with the prior art, the drain current of the MOS device 200 of the present invention during subthreshold conduction operation is lower than that of the prior art. That is, when the MOS element 200 of the present invention operates at the subthreshold conduction, the drain current is low, that is, the subthreshold current is low, and the leakage situation of the subthreshold conduction operation of the MOS element 200 is improved to improve the threshold voltage slipping phenomenon.

1 to 5 above are illustrated by taking N-type devices as an example, but the same concept can also be applied to P-type devices, as long as the type and concentration of doped impurities are changed accordingly.

The present invention has been described above with reference to preferred embodiments, and the above description is only for those skilled in the art to easily understand the content of the present invention, and is not intended to limit the scope of rights of the present invention. Under the same spirit of the present invention, various equivalent changes can be conceived by those skilled in the art. For example, other process steps or structures, such as deep wells, can be added without affecting the main characteristics of the device. All these can be obtained by analogy according to the teaching of the present invention. In addition, each of the described embodiments is not limited to be used alone, and can also be used in combination, for example but not limited to the combination of the two embodiments. Accordingly, the scope of the invention should encompass the above and all other equivalent variations. In addition, any embodiment of the present invention does not necessarily achieve all objects or advantages, and therefore, any one of the claims should not be limited thereto.

Claims (8)

1. a kind of metal-oxide semiconductor (MOS) MOS elements for improving critical voltage and gliding, which is characterized in that include：

One substrate has an insulation system, and to define an element region, and the substrate has a upper surface, wherein leads to along with one One first parallel hatching of road width direction and the first sectional view for being formed regards it, which has an insulation system recessed Area is fallen into, which is located at intersection of the insulation system with the element region along the channel width direction, wherein The element region has a width in the channel width direction；

One trap has the first conductive type, is formed in the substrate under the upper surface；

One grid is formed on the upper surface, and in a vertical direction, which is simultaneously connected on the upper surface, wherein The second sectional view formed along one second hatching parallel with a channel length direction regards it, which is located at the element Qu Zhong, the channel length direction is perpendicular to the channel width direction, and second hatching is perpendicular to first hatching；

One source electrode and a drain electrode, respectively have the second conductive type, and in the channel-length direction, which is located at the grid with the drain electrode Both sides external below pole；

Diffusion LDD region is lightly doped with the two of the source electrode and the drain electrode same conductivity, is located at both sides below the grid；And

One counterdopant region has the first conductive type, is formed in the substrate under the upper surface, wherein the counterdopant region Generally abutted along the channel-length direction and at least partly insulation system depressed area；

Wherein, it is regarded by first sectional view formed along first hatching, the counterdopant region is along the passage length side To the intersection with the insulation system, with outside inside the element region, a doping is respectively provided on the channel width direction Width, respectively the doping width be not more than the width 10%；

Wherein, it is regarded by second sectional view formed along second hatching, the counterdopant region is in the passage length side Upwards, possessed depth is calculated downwards along the vertical direction since the upper surface, be not deeper than the trap from the Vertical Square To and calculate possessed depth downwards；

Thereby, in the part element region abutted with the insulation system depressed area, in conducting operates, relative to other elements Area does not generate inversion layer ahead of time and is connected, to improve the critical voltage roll-off of the metal oxide semiconductor device.

2. improving the metal oxide semiconductor device that critical voltage glides as described in claim 1, wherein the compensation is adulterated The first conductive type impurity concentration in area is more than the first conductive type impurity concentration in the trap.

3. improving the metal oxide semiconductor device that critical voltage glides as described in claim 1, wherein the insulation system Including a shallow trench isolation (sti structure.

4. improving the metal oxide semiconductor device that critical voltage glides as described in claim 1, wherein by a vertical view Depending on it, which is completely covered the element region and junction of the insulation system in the channel length direction.

5. a kind of manufacturing method improving the metal oxide semiconductor device that critical voltage glides, which is characterized in that include：

One substrate is provided, there is an insulation system, to define an element region, and the substrate has a upper surface, wherein along One first hatching parallel with a channel width direction and the first sectional view for being formed regards it, which has an insulation Structure depressed area, the insulation system depressed area are located at boundary of the insulation system with the element region along the channel width direction Place, wherein the element region has a width in the channel width direction；

A trap is formed, with the first conductive type, which is located in the substrate under the upper surface；

A grid is formed, is located on the upper surface, and in a vertical direction, which is simultaneously connected to the upper surface On, wherein the second sectional view formed along one second hatching parallel with a channel length direction regards it, the grid position In the element region, the channel length direction is perpendicular to the channel width direction, and second hatching is perpendicular to first section Line；

A source electrode and a drain electrode are formed, respectively there is the second conductive type, and in the channel-length direction, the source electrode and the drain electrode Both sides external below the grid；

It is formed and diffusion LDD region is lightly doped with the two of the source electrode and the drain electrode same conductivity, be located at two below the grid Side；And

A counterdopant region is formed, with the first conductive type, which is located in the substrate under the upper surface, In, which generally abuts along the channel-length direction and at least partly insulation system depressed area；

Wherein, it is regarded by first sectional view formed along first hatching, the counterdopant region is along the passage length side To the intersection with the insulation system, with outside inside the element region, a doping is respectively provided on the channel width direction Width, respectively the doping width be not more than the width 10%；

Wherein, it is regarded by second sectional view formed along second hatching, the counterdopant region is in the passage length side Upwards, possessed depth is calculated downwards along the vertical direction since the upper surface, be not deeper than the trap from the Vertical Square To and calculate possessed depth downwards；

Thereby, in the part element region abutted with the insulation system depressed area, in conducting operates, relative to other elements Area does not generate inversion layer ahead of time and is connected, to improve the critical voltage roll-off of the metal oxide semiconductor device.

6. improving the manufacturing method for the metal oxide semiconductor device that critical voltage glides as claimed in claim 5, wherein The first conductive type impurity concentration in the counterdopant region is more than the first conductive type impurity concentration in the trap.

7. improving the manufacturing method for the metal oxide semiconductor device that critical voltage glides as claimed in claim 5, wherein The insulation system includes a shallow trench isolation sti structure.

8. improving the manufacturing method for the metal oxide semiconductor device that critical voltage glides as claimed in claim 5, wherein By a vertical view regard it, the counterdopant region be completely covered the element region with the insulation system connecing in the channel length direction Face.