CN104319284A - Semiconductor device structure and manufacturing method thereof - Google Patents

Abstract

The invention discloses a semiconductor device structure and a manufacturing method thereof. Through the method of lateral variable doping of the second columnar region, the withstand voltage performance of the semiconductor device is also improved under the condition of meeting low on-resistance, and has low Beneficial effect of high withstand voltage on-resistance. The semiconductor device structure of the present invention can be applied to metal oxide field effect transistors manufactured by trench filling process.

Description

A kind of semiconductor device structure and manufacturing method thereof

technical field

The present invention generally relates to the field of semiconductor technology. More specifically, it relates to a semiconductor device structure and a manufacturing method thereof.

Background technique

The power switch may be a semiconductor device, including a metal oxide semiconductor field effect transistor (MOSFET) and an insulated gate bipolar transistor (IGBT), among others. Among them, the MOSFET tube can have a horizontal structure and a vertical structure. In the vertical structure, a source region is formed on one side of the semiconductor substrate, and a drain region is formed on the other side. The gate conductor extends to the inside of the semiconductor substrate, and the semiconductor substrate separated by a gate dielectric.

On the basis of the MOSFET of the vertical structure, in order to further reduce the on-resistance of the device, a trench MOSFET has been developed. Referring to FIG. 1, it is a cross-sectional view of a semiconductor device structure in the prior art; the trench MOSFET includes An epitaxial semiconductor layer 11 in the substrate 10, a trench 12 and a drift region 13 located in the epitaxial semiconductor layer, the drift region is adjacent to the trench, and the trench extends inwardly from above the epitaxial semiconductor layer , terminating in the epitaxial semiconductor layer.

In the prior art, referring to FIG. 1, it is a cross-sectional view of a semiconductor device structure in the prior art; the doping of the drift region 13 is usually doped in a uniform doping manner, that is, the doping concentration of all the drift regions is uniform , this doping method will make the doping concentration higher in order to obtain a lower on-resistance, but the higher doping concentration will make the depletion layer bend and easily break down, such as the depletion layer 15 in Figure 1 As shown, the withstand voltage of the device is reduced.

Contents of the invention

In view of this, the present invention proposes a semiconductor device structure and its manufacturing method to solve the problem in the prior art that the depletion layer is easily broken down due to low on-resistance.

According to an aspect of the present invention, a semiconductor device structure is provided, comprising,

a first semiconductor layer of a first doping type;

a second semiconductor layer of the first doping type on the first semiconductor layer;

The first columnar region and the second columnar region separated from each other in the second semiconductor layer, the second columnar region is between every two adjacent first columnar regions,

Wherein, the second columnar region includes a first sub-columnar region and a second sub-columnar region arranged laterally, and the doping concentration of the first sub-columnar region is the concentration in the direction from the first columnar region to the second sub-columnar region. From high to low, the doping concentration of the second sub-columnar region changes from high to low in a direction from the first columnar region to the first sub-columnar region.

Preferably, the doping concentration of the first sub-columnar region varies from high to low in a step-like manner; the doping concentration of the second sub-columnar region varies from high to low in a step-like manner.

Preferably, the doping concentration of the first sub-columnar region varies linearly from high to low; the doping concentration of the second sub-columnar region varies linearly from high to low.

Further, the semiconductor device structure further includes: a body region of the second doping type, located in the second semiconductor layer; a source region of the first doping type, located in the body region; a drain region of the first doping type, located in the the bottom of the first semiconductor layer;

Preferably, the first columnar region is a columnar region of the second doping type.

Preferably, the first columnar region is a trench extending from above the second semiconductor layer into its interior, and the trench is filled with an insulating layer and a gate conductor.

A method of manufacturing a semiconductor device according to another aspect of the present invention, comprising,

forming a second semiconductor layer of the first doping type on the first semiconductor layer of the first doping type, wherein the second semiconductor layer is lightly doped with respect to the first semiconductor layer;

forming a first columnar region entering from above the second semiconductor layer;

implanting the first doping type into the remaining region of the second semiconductor layer at a certain oblique angle from the upper opening of the first columnar region, and forming a second columnar region whose concentration varies from high to low by thermal push junction;

Wherein, the second columnar region includes a first sub-columnar region and a second sub-columnar region, and the doping concentration of the first sub-columnar region is from high to high in the direction from the first columnar region to the second sub-columnar region. low change, the doping concentration of the second sub-columnar region changes from high to low in the direction from the first columnar region to the first sub-columnar region.

Preferably, the first columnar region is a columnar region of the second doping type.

Preferably, the first columnar region is a trench extending from above the second semiconductor layer into its interior, and the trench is filled with an insulating layer and a gate conductor.

To sum up, according to a semiconductor device structure and its manufacturing method of the present invention, by laterally variable doping of the second columnar region, the semiconductor device can achieve a low voltage withstand performance under the condition of low on-resistance. Preferably, it has the beneficial effect of low on-resistance and high withstand voltage.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only It is an embodiment of the present invention, and those skilled in the art can also obtain other drawings according to the provided drawings without creative work.

Fig. 1 shows the cross-sectional view of the semiconductor device structure of the prior art;

Figure 2A shows a cross-sectional view of a semiconductor device structure according to the present invention;

FIG. 2B is a schematic diagram of the concentration change of an embodiment of the second columnar region;

FIG. 2C is a schematic diagram of concentration change in another embodiment of the second columnar region;

3 is a cross-sectional view of a semiconductor device structure according to another embodiment of the present invention;

FIG. 4 is a cross-sectional view of a semiconductor device structure according to another embodiment of the present invention;

Detailed ways

Several preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but the present invention is not limited to these embodiments. The present invention covers any alternatives, modifications, equivalent methods and schemes made on the spirit and scope of the present invention. In order to provide the public with a thorough understanding of the present invention, specific details are set forth in the following preferred embodiments of the present invention, but those skilled in the art can fully understand the present invention without the description of these details.

It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean being directly on another layer or another region, or Other layers or regions are also included between it and another layer or another region. And, if the device is turned over, the layer, one region, will be "below" or "beneath" the other layer, another region.

If it is to describe the situation directly on another layer or another area, the expression "A is directly above B" or "A is above and adjacent to B" will be used herein. In the present application, "A is located directly in B" means that A is located in B, and A is directly adjacent to B, rather than A being located in a doped region formed in B.

In the present application, the term "semiconductor structure" refers to a general designation of the entire semiconductor structure formed in various steps of manufacturing a semiconductor device, including all layers or regions that have been formed. The term "laterally extending" means extending along a direction substantially perpendicular to the depth direction of the trench.

In the following, many specific details of the present invention are described, such as device structures, materials, dimensions, processing techniques and techniques, for a clearer understanding of the present invention. However, the invention may be practiced without these specific details, as will be understood by those skilled in the art.

2A shows a cross-sectional view of the semiconductor device structure according to the present invention; in this embodiment, the first columnar region is a trench extending from above the epitaxial semiconductor layer into its interior; the second columnar region is the first Doping type drift region.

Specifically, the semiconductor substrate 20 is made of silicon, for example, and is of the first doping type. In this embodiment, the first doping type is N-type doping, and the second doping type is P-type doping. In order to form an N-type semiconductor layer or region, an N-type dopant (eg, P, As) can be implanted in the semiconductor layer or region. To form a P-type semiconductor layer or region, a P-type dopant (such as B) can be doped into the semiconductor layer and region. In one example, semiconductor substrate 20 is N+ doped.

The epitaxial semiconductor layer 21 of the first doping type (ie, the second semiconductor layer) is located on the surface of the semiconductor substrate 20 (ie, the first semiconductor layer). The epitaxial semiconductor layer 21 is composed of silicon, for example. The epitaxial semiconductor layer 21 is a lightly doped layer with respect to the semiconductor substrate 20 . In one example, epitaxial semiconductor layer 21 is N-doped. Moreover, in the embodiment of the present invention, the doping concentration of the epitaxial semiconductor layer 21 is relatively lower than that in the prior art.

The trench extends from above the epitaxial semiconductor layer 21 into its interior. In the embodiment shown in FIG. 2A , the trench terminates in the epitaxial semiconductor layer 21 . In this embodiment, the bottom of the trench is even with the bottom of the epitaxial semiconductor layer. However, in alternative embodiments, the trench may pass through the epitaxial semiconductor layer 21 , terminating in the semiconductor substrate 20 . The body region 22 and the source region 23 are respectively adjacent to the trench.

The lower part of the trench is filled with conductive material to form a shielding conductor 26, and the shielding conductor 26 is separated from the epitaxial semiconductor layer 21 by an insulating layer, and the insulating layer includes at least one oxide layer and at least one nitride layer. In one example, shield conductor 26 is composed of doped polysilicon.

On the sidewall of the upper part of the trench, a gate dielectric 27 is formed. In one example, gate dielectric 27 is an oxide layer (eg, silicon oxide) having a thickness of about 25-150 nanometers. The upper part of the trench is filled with a conductive material to form a gate conductor 25 . The gate conductor 25 is separated from the epitaxial semiconductor layer 21 by a gate dielectric 27 . In one example, gate conductor 25 is composed of doped polysilicon.

A body region 22 of the second doping type is formed in the epitaxial semiconductor layer 21 . In one example, body region 22 is, for example, P-doped. Then, a source region 23 of the first doping type is formed in the body region 22 . In one example, the source region 23 is N ⁺ doped, for example.

In the embodiment shown in FIG. 2A, the semiconductor device structure further includes a drift region adjacent to the trench, and the drift region includes a laterally symmetrical first drift region II-1 and a second drift region II-2, The doping concentration of the first drift region II-1 changes from high to low in the direction from the trench to the second drift region, and the doping concentration of the second drift region II-2 is from the trench to the second drift region. A direction in which the concentration of the drift region changes from high to low. As shown in the schematic diagram of FIG. 2B, the change of the doping concentration of the first drift region and the second drift region shows a step-like change trend, that is, the doping concentration of the drift region shows a lateral change trend, which can make the power consumption of the device The depletion layer does not bend, so it is not easy to be punctured. In addition, the semiconductor device further includes a drain region of the first doping type located in the drift region, and the drain region is located at the bottom of the semiconductor substrate, which is not shown in FIG. 2A . It should be noted that the doping concentration of the first drift region II-1 and the second drift region II-2 can also change linearly, for example, the doping concentration of the first drift region II-1 is from the trench The concentration in the direction from the trench to the second drift region changes linearly from high to low, and the doping concentration of the second drift region II-2 changes linearly from high to low in the direction from the trench to the first drift region, A schematic diagram is shown in Figure 2C. In addition, since the semiconductor device structure of the embodiment of the present invention is a symmetrical structure in which the trench and the drift region are spaced apart, the concentration of the drift region on both sides of the trench is the same, which is not shown in FIG. 2A Concentration diagram of its symmetric structure.

In this embodiment, the doping of the lateral variation of the drift region can be implanted with doped impurities into the remaining part of the epitaxial semiconductor layer at a certain oblique angle from above the trench, and then thermally push the junction way to form a drift region of high and low concentration changes.

According to the semiconductor device structure of the embodiment of the present invention, compared with the prior art, the doping concentration adopts laterally variable doping. Correspondingly, as a schematic diagram of the depletion layer 28 is shown in FIG. 2A , it can be seen that the depletion layer of the device structure of the present invention is relatively flat, therefore, it has a high withstand voltage and is not easy to break down. In the case of ensuring low on-resistance, the semiconductor device has high concentration near the trench and does not affect the breakdown voltage, thereby realizing the beneficial effects of low on-resistance and high breakdown voltage.

It should be noted that the groove structure in the embodiment of the present invention is not limited to the above-mentioned one implementation manner, and there may also be other identical or similar structures, such as the manner in which the shielding conductor is connected to the gate conductor, but based on this The inventive concepts of the invention are all within the protection scope of the present invention.

In the cross-sectional view of a semiconductor device structure according to another embodiment of the present invention shown in FIG. 3 , the bottom of the trench is at a certain distance from the bottom of the epitaxial semiconductor layer. The semiconductor device structure shown in FIG. 3 The structure shown in FIG. 2A is the same. Therefore, when the concentration gradient doping is carried out to the drift region, the surrounding circle as shown in FIG. High to low variation.

It should be added that the laterally variable doping method of the present invention can also be applied to other device structures, such as a super junction structure, as shown in FIG. 4 , which is a semiconductor device structure according to another embodiment of the present invention. In the cross-sectional view, at this time, the first columnar region I is a columnar region of the second doping type, and the second columnar region II is a drift region of the first doping type.

Specifically, the semiconductor substrate 30 is made of silicon, for example, and is of the first doping type. The epitaxial semiconductor layer 31 (i.e. the second semiconductor layer) of the first doping type is located on the surface of the semiconductor substrate 30 (i.e. the first semiconductor layer). The epitaxial semiconductor layer 31 is made of silicon, for example. Bottom 30 is a lightly doped layer. The first columnar region 34 is located in the epitaxial semiconductor layer 31 and is of P-type doping type, the body region 32 of the second doping type is located in the epitaxial semiconductor layer 31 and is located on the first columnar region, and is formed in the body region 32 A source region 33 of the first doping type.

Similarly, in this embodiment, the second columnar region is an N-type doped drift region, and the drift region includes a laterally symmetrical first drift region II-1 and a second drift region II-2, the The doping concentration of the first drift region II-1 changes from high to low in the direction from the trench to the second drift region, and the doping concentration of the second drift region II-2 is from the trench to the first drift region. The direction concentration of the zone varies from high to low. As shown in the schematic diagram of Figure 3, the change of the doping concentration of the first drift region and the second drift region shows a step-like trend. As mentioned above, the doping concentration of the first drift region and the second drift region The change of can also show a linear change trend, that is, the doping concentration of the drift region changes laterally, which can make the depletion layer of the device relatively flat, so it is not easy to be broken down.

A gate oxide layer is formed on the epitaxial semiconductor layer, and then a gate conductor 35 is formed on the gate oxide layer. In one example, the gate conductor 35 is composed of doped polysilicon.

Similarly, in this embodiment, after adopting laterally variable doping, the concentration close to the first columnar region can be increased while ensuring low on-resistance, thereby ensuring the withstand voltage of the device. This embodiment also has The beneficial effects of low on-resistance and high breakdown voltage.

Finally, a method for manufacturing a semiconductor device according to the present invention includes the following steps:

forming a second semiconductor layer of the first doping type on the first semiconductor layer of the first doping type; wherein the second semiconductor layer is lightly doped with respect to the first semiconductor layer;

forming a first columnar region extending from above the second semiconductor layer into its interior;

implanting the first doping type into the remaining second semiconductor region at a certain oblique angle from the upper opening of the first columnar region to form a second columnar region whose concentration varies from high to low;

Wherein, the second columnar region includes a first sub-columnar region and a second sub-columnar region, and the doping concentration of the first sub-columnar region is from high to high in the direction from the first columnar region to the second sub-columnar region. low change, the doping concentration of the second sub-columnar region changes from high to low in the direction from the first columnar region to the first sub-columnar region.

Here, the first semiconductor layer and the second semiconductor layer are formed using a known process. Specifically, the step of forming the first columnar region is: using a hard mask and using a known etching process to further etch the second semiconductor layer. semiconductor layer, thereby forming a first columnar region in the second semiconductor layer.

The step of forming the second columnar region is as follows: using a hard mask, implanting doped impurities into the remaining part of the second semiconductor layer at a certain oblique angle from above the first columnar region, and then thermally pushing A junction method is used to form the second columnar region with high and low concentration changes.

Preferably, the first columnar region is a columnar region of the second doping type, a body region of the second doping type is formed in the second semiconductor, and the body region is located above the second columnar region; A source region of the first doping type is formed in the body region; a gate oxide layer is formed on the upper surface of the second semiconductor, and a gate conductor is formed on the gate oxide layer.

Preferably, the first columnar region is a trench that is insulated from the second semiconductor layer, and the trench extends from above the second semiconductor layer into its interior; the second columnar region is of the first doping type forming a conformal insulating stack within the trench, the insulating stack including at least one oxide layer and at least one nitride layer; forming a shield conductor in the trench, at least a portion of which is located the lower portion of the trench; forming a gate dielectric on the upper sidewall of the trench; forming a gate conductor in the trench, the gate conductor being located at the upper portion of the trench; here, the shielding conductor may be separated from the gate conductor or linked together. Afterwards, a body region of the second doping type is formed in the second semiconductor layer; a source region of the first doping type is formed in the body region.

The semiconductor device structure of the invention has the properties of low on-resistance and high withstand voltage, and can be applied to metal oxide field effect transistors manufactured by trench filling process.

In the above description, technical details such as patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design a method that is not exactly the same as the method described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be advantageously used in combination.

Embodiments according to the present invention are described above, and these embodiments do not describe all details in detail, nor do they limit the invention to only the specific embodiments described. Obviously many modifications and variations are possible in light of the above description. This description selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and its modification on the basis of the present invention. The invention is to be limited only by the claims, along with their full scope and equivalents.

Claims (9)

1. A semiconductor device structure, comprising: a first semiconductor layer of a first doping type; a second semiconductor layer of the first doping type on the first semiconductor layer; The first columnar region and the second columnar region separated from each other in the second semiconductor layer, the second columnar region is between every two adjacent first columnar regions, Wherein, the second columnar region includes a first sub-columnar region and a second sub-columnar region arranged laterally, and the doping concentration of the first sub-columnar region is the concentration in the direction from the first columnar region to the second sub-columnar region. From high to low, the doping concentration of the second sub-columnar region changes from high to low in a direction from the first columnar region to the first sub-columnar region. 2. The semiconductor device structure according to claim 1, comprising: the doping concentration of the first sub-columnar region varies from high to low in a stepwise manner; the doping concentration of the second sub-columnar region varies from high to low The trend of low change is step-like. 3. The semiconductor device structure according to claim 1, comprising: the doping concentration of the first sub-columnar region changes linearly from high to low; the doping concentration of the second sub-columnar region changes from high to low The low change trend is linear. 4. The semiconductor device structure according to claim 1, comprising, a body region of the second doping type in the second semiconductor layer; a source region of the first doping type located in the body region; a drain region of the first doping type, located at the bottom of the first semiconductor layer; 5. The semiconductor device structure according to claim 4, comprising that the first columnar region is a columnar region of the second doping type. 6. The semiconductor device structure according to claim 4, comprising, the first columnar region is a trench extending from above the second semiconductor layer into its interior, the trench is filled by an insulating layer and a gate conductor. 7. A method of manufacturing a semiconductor device, comprising, forming a second semiconductor layer of the first doping type on the first semiconductor layer of the first doping type, wherein the second semiconductor layer is lightly doped with respect to the first semiconductor layer; forming a first columnar region entering from above the second semiconductor layer; implanting the first doping type into the remaining region of the second semiconductor layer at a certain oblique angle from the upper opening of the first columnar region, and forming a second columnar region whose concentration varies from high to low by thermal push junction; Wherein, the second columnar region includes a first sub-columnar region and a second sub-columnar region, and the doping concentration of the first sub-columnar region is from high to high in the direction from the first columnar region to the second sub-columnar region. low change, the doping concentration of the second sub-columnar region changes from high to low in the direction from the first columnar region to the first sub-columnar region. 8. The method for a semiconductor device according to claim 7, comprising, the first columnar region is a columnar region of the second doping type. 9. The semiconductor device structure according to claim 7, comprising that the first columnar region is a trench extending from above the second semiconductor layer into its interior, the trench being filled by an insulating layer and a gate conductor.