CN108268286A - Computer system starting method and computer system - Google Patents
Computer system starting method and computer system Download PDFInfo
- Publication number
- CN108268286A CN108268286A CN201611244879.XA CN201611244879A CN108268286A CN 108268286 A CN108268286 A CN 108268286A CN 201611244879 A CN201611244879 A CN 201611244879A CN 108268286 A CN108268286 A CN 108268286A
- Authority
- CN
- China
- Prior art keywords
- signal
- cpu
- output signal
- computer system
- reset
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 18
- 238000002955 isolation Methods 0.000 abstract description 14
- 230000000630 rising effect Effects 0.000 description 4
- 230000002411 adverse Effects 0.000 description 3
- 238000001514 detection method Methods 0.000 description 3
- 241000700605 Viruses Species 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4406—Loading of operating system
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Sources (AREA)
Abstract
The present invention provides a kind of computer system starting method and computer system, the computer system includes mainboard and the safety card being inserted on the mainboard, the mainboard includes BIOS chips and CPU, and signal isolation switch is provided between the BIOS chips and CPU, the method includes：The safety card sends first and outputs signal to the signal isolation switch and second output signal to the CPU, wherein, for the first output signal for the signal isolation to be controlled to switch on-off, the second output signal is used to control the reset of the CPU；The signal isolation switch connects the signal path between the BIOS chips and CPU according to the first output signal；The CPU starts to reset according to the second output signal after specific delay time.The present invention can ensure that, when CPU starts to reset, signal isolation switch has connected the signal path between the BIOS chips and CPU, improves system startup stability.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a computer system and a method for starting the computer system.
Background
In order to better protect the client information, the computer can be matched with a safety card, when the computer system is started, the safety card is started and self-checked firstly, the BIOS is measured, for example, whether viruses exist or not is checked, then a RESET signal is sent to the CPU, the CPU receives the RESET signal and starts to RESET, and the BIOS starting code is read at the first time after the RESET is completed, so that the system is started. However, the RESET signal is the last signal for controlling the system to start, and for some special models, the inventor finds that the start of the computer system is controlled by the RESET signal, so that the start abnormality is easy to occur, and the stability is poor.
Disclosure of Invention
In view of this, the present invention provides a computer system starting method and a computer system, which can improve the system starting stability.
In a first aspect, the present invention provides a method for starting a computer system, where the computer system includes a motherboard and a security card inserted into the motherboard, the motherboard includes a BIOS chip and a CPU, and a signal isolation switch is disposed between the BIOS chip and the CPU, and the method includes:
the safety card sends a first output signal to the signal isolating switch and a second output signal to the CPU, wherein the first output signal is used for controlling the on-off of the signal isolating switch, and the second output signal is used for controlling the reset of the CPU;
the signal isolating switch is communicated with a signal path between the BIOS chip and the CPU according to the first output signal;
and the CPU starts to reset after a certain delay time according to the second output signal.
Optionally, the second output signal is a CPUPWRGD signal.
Optionally, the specific delay time is 8 ms.
Optionally, the method further comprises:
and reading the BIOS starting code after the CPU is reset.
In a second aspect, the present invention provides a computer system comprising: a main board and a safety card inserted on the main board, wherein the main board comprises a BIOS chip and a CPU, a signal isolating switch is arranged between the BIOS chip and the CPU, wherein,
the safety card is used for sending a first output signal to the signal isolating switch and a second output signal to the CPU, wherein the first output signal is used for controlling the on-off of the signal isolating switch, and the second output signal is used for controlling the reset of the CPU;
the signal isolating switch is used for communicating a signal path between the BIOS chip and the CPU according to the first output signal;
and the CPU is used for starting resetting after a certain delay time according to the second output signal.
Optionally, the second output signal sent by the security card is a CPUPWRGD signal.
Optionally, the CPU starts resetting with a delay of 8ms according to the CPUPWRGD signal.
Optionally, the CPU is further configured to read the BIOS boot code after the reset is completed.
The computer system comprises a mainboard and a safety card inserted on the mainboard, wherein the mainboard comprises a BIOS chip and a CPU, the BIOS chip uses a Read Only Memory (ROM), a signal isolating switch is arranged between the BIOS chip and the CPU, and the safety card sends a first output signal to the signal isolating switch and a second output signal to the CPU, wherein the first output signal is used for controlling the on-off of the signal isolating switch, and the second output signal is used for controlling the reset of the CPU; the signal isolating switch is communicated with a signal path between the BIOS chip and the CPU according to a first output signal; and the CPU starts to reset after a certain delay time according to the second output signal. Compared with the prior art, the invention can ensure that the isolating switch is communicated with the signal path between the BIOS chip and the CPU when the CPU begins to reset, the system can be started smoothly, and the starting stability of the system is improved. Furthermore, because the RESET signal is a very sensitive signal, the CPU has very strict control on the rising edge time of the RESET signal, and the signal fluctuates slightly to easily cause adverse phenomena such as system restart, etc., whereas the second output signal adopted by the present invention, such as the CPUPWRGD signal, is only a high/low level signal, and has better redundancy capability for very small fluctuations occurring during system operation or startup, and has strong anti-interference performance compared with the RESET signal.
Drawings
FIG. 1 is a flowchart of a computer system booting method according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a computer system according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention provides a computer system starting method, which comprises a mainboard and a safety card inserted on the mainboard, wherein the mainboard comprises a BIOS chip and a CPU, a signal isolating switch is arranged between the BIOS chip and the CPU, after the computer system is powered on, the safety card is started before the CPU, and the signal isolating switch can cut off an SPI signal path between the BIOS chip and the CPU in the first time. After the security card is started, firstly, the security card performs self-checking and measures on the BIOS, for example, whether viruses exist or not is checked, and then, system start is completed according to the following steps, as shown in fig. 1, the method includes:
s11, the safety card sends a first output signal to the signal isolation switch and sends a second output signal to the CPU, wherein the first output signal is used for controlling the on-off of the signal isolation switch, and the second output signal is used for controlling the reset of the CPU;
s12, the signal isolating switch is communicated with a signal path between the BIOS chip and the CPU according to the first output signal;
and S13, the CPU starts to reset after a certain delay time according to the second output signal.
It should be noted that, the relationships of S12 and S13 do not necessarily exist, that is, S13 is not necessarily executed after S12 is executed, and S12 and S13 may be executed simultaneously, but since the time required for the signal isolation switch to connect the signal path between the BIOS chip and the CPU is less than the specific delay time, the signal path between the BIOS chip and the CPU is already connected by the signal isolation switch when the CPU starts to reset.
The CPUPWRGD signal, i.e., the Power Good signal, P.G for short, or the p.ok signal, which is a logic compatible with the TTL signal for the dc output voltage detection signal and the ac input voltage detection signal, is generally selected as the second output signal. After the power is switched on, if the input alternating current voltage is within the rated working range and the direct current output voltages of all the circuits also reach the lowest detection level (+5V output is more than 4.75V), the security card sends out a CPUPWRGD signal (the CPUPWRGD signal is high level) after 100 ms-500 ms of delay, which indicates that the power is normal. The CPUPWRGD signal is very important, and in actual work, even if each path of direct current output of the power supply is normal, if the CPUPWRGD signal does not exist, the main board cannot work normally.
In the patent, CPUPWRGD signals are controlled in a multi-path mode, and good design redundancy is arranged on a main board to filter small signal fluctuation, so that the stability of the signals is guaranteed; meanwhile, the CPUPWRGD signal has no strict time requirement on the rising edge, and a small filter capacitor can be reserved at a CPU port to inhibit noise generated in the transmission process of the signal.
After the CPU receives the CPUPWRGD signal sent by the security card, the CPU can delay 8ms to start resetting according to the starting time sequence of the computer, and the signal isolating switch is communicated with a signal path between the BIOS chip and the CPU after receiving the first output signal and only needs less than 1ms for stable work, so that before the CPU starts resetting, the signal isolating switch is communicated with the signal path between the BIOS chip and the CPU and works stably.
After the CPU is reset, the BIOS starting code is read, the operating system is normally entered, and the system normally works under the monitoring of the security card.
According to the computer system starting method provided by the embodiment of the invention, the safety card is firstly started, self-checked and measures the BIOS, and then a first output signal is sent to the signal isolating switch and a second output signal is sent to the CPU, wherein the first output signal is used for controlling the on-off of the signal isolating switch, and the second output signal is used for controlling the resetting of the CPU; the safety card controls the start of the computer system no longer through a RESET signal, but through a second output signal, such as a CPUPWRGD signal, the start of the computer system is controlled, the CPU starts to RESET after delaying for 8ms after receiving the CPUPWRGD signal, and the BIOS start code is read at the first time after the RESET is completed. Furthermore, because the RESET signal is a very sensitive signal, the CPU has very strict control on the rising edge time of the RESET signal, and the signal fluctuates slightly to easily cause adverse phenomena such as system restart, etc., whereas the second output signal adopted by the present invention, such as the CPUPWRGD signal, is only a high/low level signal, and has better redundancy capability for very small fluctuations occurring during system operation or startup, and has strong anti-interference performance compared with the RESET signal.
An embodiment of the present invention further provides a computer system, as shown in fig. 2, where the computer system includes: the safety card comprises a main board 1 and a safety card 11 inserted on the main board 1, wherein a BIOS chip 12 and a CPU13 are arranged on the main board 1, and a signal isolating switch 14 is arranged between the BIOS chip 12 and the CPU13 in order to protect the BIOS from being invaded, so that the signal isolation of the BIOS chip and the CPU is realized. After the system is powered on, the safety card starts and performs self-checking and measurement on the BIOS, and the signal isolating switch cuts off an SPI signal path between the BIOS chip and the CPU at the first time. Wherein,
the security card 11 is configured to send a first output signal to the signal isolation switch 14 and a second output signal to the CPU13, where the first output signal is used to control on/off of the signal isolation switch 14, and the second output signal is used to control resetting of the CPU 13;
the signal isolation switch 14 is used for connecting a signal path between the BIOS chip 12 and the CPU13 according to a first output signal;
the CPU13 is configured to start resetting after a certain delay time according to the second output signal.
Optionally, the second output signal sent by the security card 11 is a CPUPWRGD signal.
Optionally, the CPU13 delays to start resetting after receiving the CPUPWRGD signal for 8ms, and reads the BIOS start code after the resetting is completed.
According to the computer system provided by the embodiment of the invention, the main board is improved, the RESET signal on the main board is not connected to the output signal of the security card any more, but the CPUPWRGD signal is connected to the output signal of the security card, the CPU starts to RESET after receiving the CPUPWRGD signal by delaying for 8ms, and the BIOS starting code is read at the first time after the resetting is finished. Furthermore, because the RESET signal is a very sensitive signal, the CPU has very strict control on the rising edge time of the RESET signal, and the signal fluctuates slightly to easily cause adverse phenomena such as system restart, etc., whereas the second output signal adopted by the present invention, such as the CPUPWRGD signal, is only a high/low level signal, and has better redundancy capability for very small fluctuations occurring during system operation or startup, and has strong anti-interference performance compared with the RESET signal.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (8)
1. A computer system starting method is characterized in that the computer system comprises a mainboard and a security card inserted on the mainboard, the mainboard comprises a BIOS chip and a CPU, a signal isolating switch is arranged between the BIOS chip and the CPU, and the method comprises the following steps:
the safety card sends a first output signal to the signal isolating switch and a second output signal to the CPU, wherein the first output signal is used for controlling the on-off of the signal isolating switch, and the second output signal is used for controlling the reset of the CPU;
the signal isolating switch is communicated with a signal path between the BIOS chip and the CPU according to the first output signal;
and the CPU starts to reset after a certain delay time according to the second output signal.
2. The method of claim 1, wherein the second output signal is a CPUPWRGD signal.
3. The method of claim 2, wherein the specific delay time is 8 ms.
4. The method of claim 1, further comprising:
and reading the BIOS starting code after the CPU is reset.
5. A computer system, comprising: a main board and a safety card inserted on the main board, wherein the main board comprises a BIOS chip and a CPU, a signal isolating switch is arranged between the BIOS chip and the CPU, wherein,
the safety card is used for sending a first output signal to the signal isolating switch and a second output signal to the CPU, wherein the first output signal is used for controlling the on-off of the signal isolating switch, and the second output signal is used for controlling the reset of the CPU;
the signal isolating switch is used for communicating a signal path between the BIOS chip and the CPU according to the first output signal;
and the CPU is used for starting resetting after a certain delay time according to the second output signal.
6. The computer system of claim 5, wherein the second output signal transmitted by the security card is a CPUPWRGD signal.
7. The computer system of claim 6, wherein the CPU initiates a reset with a delay of 8ms based on the CPUPWRGD signal.
8. The computer system of claim 5, wherein the CPU is further configured to read the BIOS boot code after the reset is complete.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611244879.XA CN108268286A (en) | 2016-12-29 | 2016-12-29 | Computer system starting method and computer system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611244879.XA CN108268286A (en) | 2016-12-29 | 2016-12-29 | Computer system starting method and computer system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108268286A true CN108268286A (en) | 2018-07-10 |
Family
ID=62753673
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611244879.XA Pending CN108268286A (en) | 2016-12-29 | 2016-12-29 | Computer system starting method and computer system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108268286A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109308414A (en) * | 2018-08-27 | 2019-02-05 | 山东超越数控电子股份有限公司 | A kind of mainboard clean boot realization system and method based on Domestic Platform |
Citations (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1101145A (en) * | 1993-07-23 | 1995-04-05 | 国际商业机器公司 | A method for preserving and restoring the state of the CPU executing code in protected mode |
| CN1103748A (en) * | 1993-03-10 | 1995-06-14 | 世嘉企业股份有限公司 | Method for executing software program and circuit device for implementing the method |
| CN1553338A (en) * | 2003-06-08 | 2004-12-08 | 华为技术有限公司 | Method and system for starting central processing unit |
| CN1713101A (en) * | 2005-07-12 | 2005-12-28 | 中国长城计算机深圳股份有限公司 | Computer power-on identity authentication system and authentication method |
| CN101504705A (en) * | 2009-03-17 | 2009-08-12 | 武汉大学 | Trusted platform module and its computer starting control method |
| CN101877040A (en) * | 2009-12-07 | 2010-11-03 | 中国航天科工集团第二研究院七○六所 | High-reliability computing platform |
| CN102270029A (en) * | 2011-07-21 | 2011-12-07 | 曙光信息产业(北京)有限公司 | Method for warmly starting mainboard of Loongson blade |
| CN102508534A (en) * | 2011-09-30 | 2012-06-20 | 中国人民解放军海军计算技术研究所 | Startup control method of credible main board |
| CN102663301A (en) * | 2012-04-13 | 2012-09-12 | 北京国基科技股份有限公司 | Trusted computer and credibility detection method |
| CN102708028A (en) * | 2012-05-18 | 2012-10-03 | 中国人民解放军第二炮兵装备研究院第四研究所 | Trusted redundant fault-tolerant computer system |
| CN102707782A (en) * | 2012-05-15 | 2012-10-03 | 江苏中科梦兰电子科技有限公司 | Multi-core central processing unit (CPU) based computer mainboard reset system and method |
| CN103593622A (en) * | 2013-11-05 | 2014-02-19 | 浪潮集团有限公司 | FPGA-based design method of safe and trusted computer |
| CN103886267A (en) * | 2012-12-20 | 2014-06-25 | 联想(北京)有限公司 | Method, device, chip and computer mainboard for isolating and switching internal and external network and computer |
| CN203720847U (en) * | 2014-02-26 | 2014-07-16 | 山东超越数控电子有限公司 | Discretionary security credible encryption equipment used in domestic computer platform |
| CN104156289A (en) * | 2014-07-09 | 2014-11-19 | 中国电子科技集团公司第三十二研究所 | Synchronous control method and system based on detection circuit |
| CN104200169A (en) * | 2014-09-09 | 2014-12-10 | 山东超越数控电子有限公司 | Method for realizing initiative measurement of trusted computing |
| CN104318142A (en) * | 2014-10-31 | 2015-01-28 | 山东超越数控电子有限公司 | Trusted booting method of computer |
| CN204203971U (en) * | 2014-10-13 | 2015-03-11 | 长城信息产业股份有限公司 | A kind of credible accounting system |
| CN104572535A (en) * | 2014-12-26 | 2015-04-29 | 中国电子科技集团公司第十五研究所 | Autonomous and controllable computing device based on CPCI-E (compact peripheral component interconnect-express) bus |
| CN105549706A (en) * | 2015-12-11 | 2016-05-04 | 华为技术有限公司 | Method, device and system for warmly restarting server |
-
2016
- 2016-12-29 CN CN201611244879.XA patent/CN108268286A/en active Pending
Patent Citations (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1103748A (en) * | 1993-03-10 | 1995-06-14 | 世嘉企业股份有限公司 | Method for executing software program and circuit device for implementing the method |
| CN1101145A (en) * | 1993-07-23 | 1995-04-05 | 国际商业机器公司 | A method for preserving and restoring the state of the CPU executing code in protected mode |
| CN1553338A (en) * | 2003-06-08 | 2004-12-08 | 华为技术有限公司 | Method and system for starting central processing unit |
| CN1713101A (en) * | 2005-07-12 | 2005-12-28 | 中国长城计算机深圳股份有限公司 | Computer power-on identity authentication system and authentication method |
| CN101504705A (en) * | 2009-03-17 | 2009-08-12 | 武汉大学 | Trusted platform module and its computer starting control method |
| CN101877040A (en) * | 2009-12-07 | 2010-11-03 | 中国航天科工集团第二研究院七○六所 | High-reliability computing platform |
| CN102270029A (en) * | 2011-07-21 | 2011-12-07 | 曙光信息产业(北京)有限公司 | Method for warmly starting mainboard of Loongson blade |
| CN102508534A (en) * | 2011-09-30 | 2012-06-20 | 中国人民解放军海军计算技术研究所 | Startup control method of credible main board |
| CN102663301A (en) * | 2012-04-13 | 2012-09-12 | 北京国基科技股份有限公司 | Trusted computer and credibility detection method |
| CN102707782A (en) * | 2012-05-15 | 2012-10-03 | 江苏中科梦兰电子科技有限公司 | Multi-core central processing unit (CPU) based computer mainboard reset system and method |
| CN102708028A (en) * | 2012-05-18 | 2012-10-03 | 中国人民解放军第二炮兵装备研究院第四研究所 | Trusted redundant fault-tolerant computer system |
| CN103886267A (en) * | 2012-12-20 | 2014-06-25 | 联想(北京)有限公司 | Method, device, chip and computer mainboard for isolating and switching internal and external network and computer |
| CN103593622A (en) * | 2013-11-05 | 2014-02-19 | 浪潮集团有限公司 | FPGA-based design method of safe and trusted computer |
| CN203720847U (en) * | 2014-02-26 | 2014-07-16 | 山东超越数控电子有限公司 | Discretionary security credible encryption equipment used in domestic computer platform |
| CN104156289A (en) * | 2014-07-09 | 2014-11-19 | 中国电子科技集团公司第三十二研究所 | Synchronous control method and system based on detection circuit |
| CN104200169A (en) * | 2014-09-09 | 2014-12-10 | 山东超越数控电子有限公司 | Method for realizing initiative measurement of trusted computing |
| CN204203971U (en) * | 2014-10-13 | 2015-03-11 | 长城信息产业股份有限公司 | A kind of credible accounting system |
| CN104318142A (en) * | 2014-10-31 | 2015-01-28 | 山东超越数控电子有限公司 | Trusted booting method of computer |
| CN104572535A (en) * | 2014-12-26 | 2015-04-29 | 中国电子科技集团公司第十五研究所 | Autonomous and controllable computing device based on CPCI-E (compact peripheral component interconnect-express) bus |
| CN105549706A (en) * | 2015-12-11 | 2016-05-04 | 华为技术有限公司 | Method, device and system for warmly restarting server |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109308414A (en) * | 2018-08-27 | 2019-02-05 | 山东超越数控电子股份有限公司 | A kind of mainboard clean boot realization system and method based on Domestic Platform |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20140143477A1 (en) | Computer system and data recovery method thereof | |
| EP2821882B1 (en) | Computer device and method for converting working mode of universal serial bus connector of the computer device | |
| CN104050061B (en) | A kind of Based PC Ie bus many master control board redundancies standby system | |
| CN103136048B (en) | Computer system | |
| US9924058B2 (en) | Information processing apparatus that controls power supply to different destinations, method of controlling the same, and storage | |
| US20090013164A1 (en) | Computer system and method of using power button to switch from one BIOS to another | |
| TW200928719A (en) | Computer, and method for error-detecting and booting of BIOS thereof | |
| US9684519B2 (en) | Electronic device using trigger signal and status signal to execute a plurality of booting modes | |
| US10678739B1 (en) | Electronic system, host device and control method | |
| CN108268286A (en) | Computer system starting method and computer system | |
| EP3240233A1 (en) | Power fail safeguard method, device and system thereof | |
| CN107678871B (en) | Electronic equipment starting method and electronic equipment | |
| WO2018121351A1 (en) | Interface card status detection method, interface card, and line card | |
| CN200986699Y (en) | Multiprocessor power-on switching circuit | |
| CN109521863B (en) | Chip and chip power-on starting method | |
| EP2750030A1 (en) | Method, apparatus and processor for reading BIOS | |
| CN106484438B (en) | Computer startup method and system | |
| US20210300271A1 (en) | Power supply circuit | |
| KR20220147992A (en) | Apparatus and method for controlling power of vehicle | |
| EP3451182A1 (en) | Connection circuit | |
| TW201218075A (en) | Dual processor startup system | |
| KR101932271B1 (en) | computing system and method of controlling computing system | |
| CN107783915B (en) | Port multiplexing method and device for MCU | |
| CN114647293B (en) | Power-down protection method, device, power monitoring component and server | |
| CN112084049B (en) | Method for monitoring resident program of baseboard management controller |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180710 |
|
| RJ01 | Rejection of invention patent application after publication |