CN104050061B - A kind of Based PC Ie bus many master control board redundancies standby system - Google Patents
A kind of Based PC Ie bus many master control board redundancies standby system Download PDFInfo
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Abstract
The invention discloses a kind of Based PC Ie bus many master control board redundancies standby system, comprising: motherboard circuit A(12), motherboard circuit B(13), motherboard circuit C(14), PCIe switched circuit (15), FC channel card circuit (10) and PCIe? Raid card circuit (11).After system electrification, initial configuration file is sent in PCIe managing chip (7) by test computer, then PCIe managing chip (7) by initial configuration file programming in serial EEPROM (8).After programming, restarting systems, PCIe managing chip (7) reads the initial configuration file of serial EEPROM (8) by SMBus bus, for the port register of PCI allocation e managing chip (7), compartment model and clock module.Present invention achieves when many master control board redundancies standby system breaks down and carry out real-time switched system, improve the real-time of system.
Description
Technical field
The present invention relates to a kind of many master control board redundancies standby system, particularly a kind of Based PC Ie bus many master control board redundancies standby system.
Background technology
Many master control board redundancies standby system is mainly used in high safety, highly-reliable system application, can carry out localization of fault and standby system switching when system occurs abnormal.Many master control board redundancies standby system in the past, comprising: mainboard, PCI peripheral hardware board, board condition monitoring system, I2C controller, CPU processor and BMC controller.The voltage of board condition monitoring system on analog input card, electric current and temperature signal, whether detection system running status is normal.But many master control board redundancies standby system is in the past the fault-tolerant computer based on cpci bus, when standby system switches, computer system need be restarted so that carry out re-enumeration and allocation space to PCI equipment, this process can not meet the requirement of high-performance real-time computer, and can not meet the high speed development of microprocessor, storer and interconnection network to the requirement of high speed data transfer process based on the computer system of cpci bus.
Summary of the invention
The object of the present invention is to provide a kind of Based PC Ie bus many master control board redundancies standby system, computer system need be restarted when solving the computer system switched system of tradition based on cpci bus and cpci bus can not meet the high speed development of microprocessor, storer and interconnection network to the problem of high speed data transfer process.
A kind of Based PC Ie bus many master control board redundancies standby system, comprise: motherboard circuit A, motherboard circuit B, motherboard circuit C, PCIe switched circuit, FC channel card circuit and PCIeRaid card circuit, wherein motherboard circuit A comprises: CPU processor A and PCIe controller A, motherboard circuit B comprises: CPU processor B and PCIe controller B, motherboard circuit C comprises: CPU processor C and PCIe controller C, PCIe switched circuit comprises: PCIe managing chip, serial EEPROM and clock chip.
PCIe controller A is bi-directionally connected by the port a of PCIe bus and PCIe managing chip, PCIe controller B is bi-directionally connected by the port b of PCIe bus and PCIe managing chip, PCIe controller C is bi-directionally connected by the port c of PCIe bus and PCIe managing chip, test computer is bi-directionally connected by SMBus bus and PCIe managing chip, FC channel card circuit is bi-directionally connected by the port e of PCIe bus and PCIe managing chip, and PCIeRaid card circuit is bi-directionally connected by the port d of PCIe bus and PCIe managing chip; In motherboard circuit A, CPU processor A and PCIe controller A are bi-directionally connected; In motherboard circuit B, CPU processor B and PCIe controller B are bi-directionally connected; In motherboard circuit C, CPU processor C and PCIe controller C is bi-directionally connected; In PCIe switched circuit, PCIe managing chip and serial EEPROM are bi-directionally connected by SMBus bus, and the output terminal of clock chip is connected with the input end of PCIe managing chip.
After many master control board redundancies standby system of Based PC Ie bus powers on, first initial configuration file is sent in PCIe managing chip by SMBus bus by test computer, then initial configuration file is passed through the total line writing of SMBus in serial EEPROM by PCIe managing chip, completes the programming of initial configuration file.The content of initial configuration file is the setting to PCIe managing chip, comprising: arranging port a is Combined-operating mode, and namely port a is simultaneously as uplink port and non-transparent bridge, and be expressed as P2P+NT, the setting of port b is identical with port a; Arranging port c is single mode of operation, and namely port c is only as non-transparent bridge, is expressed as NT; Arranging port d is single mode of operation, and namely port d is only as downlink port, and be expressed as P2P, the setting of port e is identical with port d; Subregion k is set and comprises port a and port d; Subregion m is set and comprises port b and port e; Subregion n is set and comprises port c; The clock module arranging PCIe managing chip is global clock pattern.
After programming, restarting systems, PCIe managing chip reads the initial configuration file of serial EEPROM by SMBus bus, for the port register of PCI allocation e managing chip, compartment model and clock module.After configuration, the port a in subregion k is communicated with port d by PCIe managing chip, and now PCIeRaid card circuit is as the downstream PCIe equipment of CPU processor A; Port b in subregion m is communicated with port e by PCIe managing chip, and now FC channel card circuit is as the downstream PCIe equipment of CPU processor B; The mode of operation of subregion n middle port c is set to non-transparent bridge by PCIe managing chip, now CPU processor C does not have the PCIe equipment in downstream, CPU processor C as spare main plate circuit, downstream PCIe equipment corresponding when breaking down for adapter CPU processor A or CPU processor B; PCIe managing chip provides global clock by clock chip.Then, CPU processor A carries out PCIe device scan completion system to PCIeRaid card circuit and enumerates, CPU processor B is carried out PCIe device scan completion system to FC channel card circuit and is enumerated, CPU processor C carries out PCIe device scan completion system equally and enumerates, the operating system that last normal startup is respective.
After CPU processor A, CPU processor B, CPU processor C normally start respective operating system, heartbeat message is sent by non-transparent bridge to CPU processor C by CPU processor A, CPU processor B, if CPU processor C received the heartbeat message of CPU processor A and the transmission of CPU processor B respectively in 1 second, then CPU processor C is still in stand-by state, continues the heartbeat message detecting CPU processor A and the transmission of CPU processor B.When CPU processor A occurs abnormal, CPU processor A stops sending heartbeat message to CPU processor C, CPU processor C did not receive the heartbeat message that CPU processor A is sent in 1 second, then trigger the fault recovery function of CPU processor C: change the mode of operation of PCIe managing chip port c into uplink port by non-transparent bridge dynamically by CPU processor C and add non-transparent bridge, port d in PCIe managing chip subregion k is removed, PCIe managing chip port d is joined subregion n, the mode of operation of PCIe managing chip port a is added non-transparent bridge by uplink port and changes non-transparent bridge into.Then CPU processor C carries out the re-enumeration of PCIe scan bus and equipment, to identify the PCIeRaid card circuit arrangement newly joining CPU processor C.The port c of such PCIe managing chip is communicated with port d and belongs to same subregion n, PCIeRaid card circuit and transfers PCIe equipment as CPU processor C to as the PCIe equipment of CPU processor A.When CPU processor B occurs abnormal, its processing procedure and CPU processor A occur that abnormal phase is same.
When CPU processor A, CPU processor B duty are all abnormal, then trigger the fault recovery function of CPU processor C equally: change the mode of operation of CPU processor C corresponding PCIe managing chip port c into uplink port by non-transparent bridge dynamically and add non-transparent bridge, the downstream PCIe equipment of CPU processor A, CPU processor B is all switched to the downstream PCIe equipment of CPU processor C, the mode of operation of CPU processor A, the corresponding PCIe managing chip port a and port b of CPU processor B is added non-transparent bridge by uplink port dynamically and changes non-transparent bridge into.
Present invention achieves many master control board redundancies standby system of Based PC Ie bus, make system can tackle certain block even situation of a few pieces of mainboard exceptions, improve the ability to ward off risks of system; Be applicable to the occasion that system stability, reliability tool are had high requirements.
Accompanying drawing explanation
The structural representation of a kind of Based PC Ie of Fig. 1 bus many master control board redundancies standby system.
1.CPU processor A 2.PCIe controller A3.CPU processor B 4.PCIe controller B5.CPU processor C6.PCIe controller C7.PCIe managing chip 8. serial EEPROM 9. clock chip 10.FC channel card circuit 11.PCIeRaid card circuit 12. motherboard circuit A13. motherboard circuit B14. motherboard circuit C15.PCIe switched circuit.
Embodiment
A kind of Based PC Ie bus many master control board redundancies standby system, comprise: motherboard circuit A12, motherboard circuit B13, motherboard circuit C14, PCIe switched circuit 15, FC channel card circuit 10 and PCIeRaid card circuit 11, wherein motherboard circuit A12 comprises: CPU processor A 1 and PCIe controller A2, motherboard circuit B13 comprises: CPU processor B 3 and PCIe controller B4, motherboard circuit C14 comprises: CPU processor C5 and PCIe controller C6, and PCIe switched circuit 15 comprises: PCIe managing chip 7, serial EEPROM 8 and clock chip 9.
PCIe controller A2 is bi-directionally connected by the port a of PCIe bus and PCIe managing chip 7, PCIe controller B4 is bi-directionally connected by the port b of PCIe bus and PCIe managing chip 7, PCIe controller C6 is bi-directionally connected by the port c of PCIe bus and PCIe managing chip 7, test computer is bi-directionally connected by SMBus bus and PCIe managing chip 7, FC channel card circuit 10 is bi-directionally connected by the port e of PCIe bus and PCIe managing chip 7, and PCIeRaid card circuit 11 is bi-directionally connected by the port d of PCIe bus and PCIe managing chip 7; In motherboard circuit A12, CPU processor A 1 and PCIe controller A2 are bi-directionally connected; In motherboard circuit B13, CPU processor B 3 and PCIe controller B4 are bi-directionally connected; In motherboard circuit C14, CPU processor C5 and PCIe controller C6 is bi-directionally connected; In PCIe switched circuit 15, PCIe managing chip 7 and serial EEPROM 8 are bi-directionally connected by SMBus bus, and the output terminal of clock chip 9 is connected with the input end of PCIe managing chip 7.
After many master control board redundancies standby system of Based PC Ie bus powers on, first initial configuration file is sent in PCIe managing chip 7 by SMBus bus by test computer, then initial configuration file is passed through the total line writing of SMBus in serial EEPROM 8 by PCIe managing chip 7, completes the programming of initial configuration file.The content of initial configuration file is the setting to PCIe managing chip 7, comprising: arranging port a is Combined-operating mode, and namely port a is simultaneously as uplink port and non-transparent bridge, and be expressed as P2P+NT, the setting of port b is identical with port a; Arranging port c is single mode of operation, and namely port c is only as non-transparent bridge, is expressed as NT; Arranging port d is single mode of operation, and namely port d is only as downlink port, and be expressed as P2P, the setting of port e is identical with port d; Subregion k is set and comprises port a and port d; Subregion m is set and comprises port b and port e; Subregion n is set and comprises port c; The clock module arranging PCIe managing chip 7 is global clock pattern.
After programming, restarting systems, PCIe managing chip 7 reads the initial configuration file of serial EEPROM 8 by SMBus bus, for the port register of PCI allocation e managing chip 7, compartment model and clock module.After configuration, the port a in subregion k is communicated with port d by PCIe managing chip 7, and now PCIeRaid card circuit 11 is as the downstream PCIe equipment of CPU processor A 1; Port b in subregion m is communicated with port e by PCIe managing chip 7, and now FC channel card circuit 10 is as the downstream PCIe equipment of CPU processor B 3; The mode of operation of subregion n middle port c is set to non-transparent bridge by PCIe managing chip 7, now CPU processor C5 does not have the PCIe equipment in downstream, CPU processor C5 as spare main plate circuit, downstream PCIe equipment corresponding when breaking down for adapter CPU processor A 1 or CPU processor B 3; PCIe managing chip 7 provides global clock by clock chip 9.Then, CPU processor A 1 pair of PCIeRaid card circuit 11 carries out PCIe device scan completion system and enumerates, CPU processor B 3 pairs of FC channel card circuit 10 carry out PCIe device scan completion system and enumerate, CPU processor C5 carries out PCIe device scan completion system equally and enumerates, the operating system that last normal startup is respective.
After CPU processor A 1, CPU processor B 3, CPU processor C5 normally start respective operating system, heartbeat message is sent by non-transparent bridge to CPU processor C5 by CPU processor A 1, CPU processor B 3, if CPU processor C5 received the heartbeat message of CPU processor A 1 and CPU processor B 3 transmission respectively in 1 second, then CPU processor C5 is still in stand-by state, continues the heartbeat message detecting CPU processor A 1 and CPU processor B 3 transmission.When CPU processor A 1 occurs abnormal, CPU processor A 1 stops sending heartbeat message to CPU processor C5, CPU processor C5 did not receive the heartbeat message that CPU processor A 1 is sent in 1 second, then trigger the fault recovery function of CPU processor C5: change the mode of operation of PCIe managing chip 7 port c into uplink port by non-transparent bridge dynamically by CPU processor C5 and add non-transparent bridge, port d in PCIe managing chip 7 subregion k is removed, PCIe managing chip 7 port d is joined subregion n, the mode of operation of PCIe managing chip 7 port a is added non-transparent bridge by uplink port and changes non-transparent bridge into.Then CPU processor C5 carries out the re-enumeration of PCIe scan bus and equipment, to identify PCIeRaid card circuit 11 equipment newly joining CPU processor C5.The port c of such PCIe managing chip 7 is communicated with port d and belongs to same subregion n, PCIeRaid card circuit 11 and transfers PCIe equipment as CPU processor C5 to as the PCIe equipment of CPU processor A 1.When CPU processor B 3 occurs abnormal, its processing procedure and CPU processor A 1 occur that abnormal phase is same.
When CPU processor A 1, CPU processor B 3 duty are all abnormal, then trigger the fault recovery function of CPU processor C5 equally: change the mode of operation of CPU processor C5 corresponding PCIe managing chip 7 port c into uplink port by non-transparent bridge dynamically and add non-transparent bridge, the downstream PCIe equipment of CPU processor A 1, CPU processor B 3 is all switched to the downstream PCIe equipment of CPU processor C5, the mode of operation of CPU processor A 1, CPU processor B 3 corresponding PCIe managing chip 7 port a and port b is added non-transparent bridge by uplink port dynamically and changes non-transparent bridge into.
Claims (1)
1. Based PC Ie bus many master control board redundancies standby system, it is characterized in that comprising: motherboard circuit A (12), motherboard circuit B (13), motherboard circuit C (14), PCIe switched circuit (15), FC channel card circuit (10) and PCIeRaid card circuit (11), wherein motherboard circuit A (12) comprising: CPU processor A (1) and PCIe controller A (2), motherboard circuit B (13) comprising: CPU processor B (3) and PCIe controller B (4), motherboard circuit C (14) comprising: CPU processor C (5) and PCIe controller C (6), PCIe switched circuit (15) comprising: PCIe managing chip (7), serial EEPROM (8) and clock chip (9),
PCIe controller A (2) is bi-directionally connected by the port a of PCIe bus and PCIe managing chip (7), PCIe controller B (4) is bi-directionally connected by the port b of PCIe bus and PCIe managing chip (7), PCIe controller C (6) is bi-directionally connected by the port c of PCIe bus and PCIe managing chip (7), test computer is bi-directionally connected by SMBus bus and PCIe managing chip (7), FC channel card circuit (10) is bi-directionally connected by the port e of PCIe bus and PCIe managing chip (7), PCIeRaid card circuit (11) is bi-directionally connected by the port d of PCIe bus and PCIe managing chip (7), in motherboard circuit A (12), CPU processor A (1) and PCIe controller A (2) are bi-directionally connected, in motherboard circuit B (13), CPU processor B (3) and PCIe controller B (4) are bi-directionally connected, in motherboard circuit C (14), CPU processor C (5) and PCIe controller C (6) are bi-directionally connected, in PCIe switched circuit (15), PCIe managing chip (7) and serial EEPROM (8) are bi-directionally connected by SMBus bus, and the output terminal of clock chip (9) is connected with the input end of PCIe managing chip (7).
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| US10114658B2 (en) * | 2016-05-23 | 2018-10-30 | Baida USA LLC | Concurrent testing of PCI express devices on a server platform |
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| CN108008657B (en) * | 2016-10-28 | 2020-07-21 | 北京计算机技术及应用研究所 | Load balancing redundancy switching system with control panel and switching panel buses directly connected |
| CN107085528A (en) * | 2017-05-05 | 2017-08-22 | 郑州云海信息技术有限公司 | A method and device for updating EEPROM of PEX9797 chip |
| CN107203439A (en) * | 2017-05-15 | 2017-09-26 | 中国船舶重工集团公司第七六研究所 | Modularity redundancy computer based on PCIe |
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| CN108762939A (en) * | 2018-06-29 | 2018-11-06 | 郑州云海信息技术有限公司 | A kind of PCIe port resource allocation methods, system and equipment and storage medium |
| WO2020029254A1 (en) * | 2018-08-10 | 2020-02-13 | 深圳市汇顶科技股份有限公司 | Soc chip and bus access control method |
| CN110012369A (en) * | 2019-04-12 | 2019-07-12 | 苏州浪潮智能科技有限公司 | A kind of FC sonet card |
| CN112306773B (en) * | 2020-11-05 | 2024-06-18 | 中国航空工业集团公司西安航空计算技术研究所 | Fault detection platform of FC node machine with standard serial host interface |
| CN114003170B (en) * | 2021-09-17 | 2024-03-19 | 方一信息科技（上海）有限公司 | FPGA-based Raid card driving method |
| CN116049044B (en) * | 2023-03-28 | 2023-06-23 | 飞腾信息技术有限公司 | Control method of pcie equipment, computer equipment and system on chip |
| CN116881053B (en) * | 2023-09-06 | 2023-11-17 | 苏州浪潮智能科技有限公司 | Data processing method, exchange board, data processing system and data processing device |
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| US8677180B2 (en) * | 2010-06-23 | 2014-03-18 | International Business Machines Corporation | Switch failover control in a multiprocessor computer system |
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| CN103415844A (en) * | 2011-01-18 | 2013-11-27 | Lsi公司 | Higher-level redundancy information computation |
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