CN1082268A - The power-saving method and the device that are used for data communication receiver - Google Patents
The power-saving method and the device that are used for data communication receiver Download PDFInfo
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- H—ELECTRICITY
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- H04W88/00—Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
Data communication receiver comprises receiver, the coded message signal that is transmitted in order to reception; Battery saver circuit is powered to receiver; Be coupled to the signal recovery circuitry of receiver, the coded message signal that recovery receives is to produce the nearly data flow of M * N position; Address correlator and signal recovery circuitry coupling are used at least a portion of M * N bit data stream and the appropriate section of a default M position coded word are made relevant treatment; Battery saver circuit is in response to the address correlator, and ends power supply to receiver during all above a default error count in each of N error count.
Description
The present invention is that Schwendeman etc. submitted on May 29th, 1992, title is No07/891 for " data communication receivers that the belt variable length message is handled ", serial number, the part continuation application of 363 patent application.
The present invention relates generally to the economize on electricity field in data communication receiver, or rather, relate to a kind of power-saving method and device in the data communication receiver that receives piece insertion address.
Paging receiver is when using the limited battery of energy storage, and the general technology of saving battery that adopts is with extending battery life, and the example of this class technology of having used having the relevant relevant saving with non-coding of the battery technology battery technology of saving of coding.The relevant saving of the coding that one example has been used battery technology is that paging receiver is distributed to specific frame, as commonly used in the POCSAG signaling protocol.Can distribute frame because in POCSAG signal format, there are 8, so roughly can obtain 8 to 1 battery improvement factor.Another example coding associated batteries power-saving technique is with address packets before corresponding message.This makes the paging receiver that does not detect its address in the marshalling of address save electric power during message part transmits.
One routine non-coding associated batteries power-saving technique is a scarce signal detector, and it controls a battery saver circuit, and this circuit provides a supply power voltage off and on, and responds a processed non-preset signals and make battery saver circuit be in off position.The relevant power-saving technique of another kind of non-coding is to transmit receiver identification code numeral with the order that importance increases progressively; This greatly reduces the power consumption of receiver, thereby has prolonged the life-span of battery of paging receiver.The non-coding associated batteries power-saving technique that another example is used be to receive first a default figure place littler than address size, and the first default figure place that will receive compares with corresponding address bit.When the comparison error between position that receives and address bit was preset wrong number above one, address decoder was stopped.
Though these battery power conservation technology can both improve battery life, but and seldom can obtain reliable address decoder, all the more so when the mass-sending mistake especially under the more weak situation of signal, or in the process of transfer address, occurring, thus the battery power conservation performance of having disturbed these technology to provide.So be necessary further to improve the battery life in the data communication receiver, the reception function driven with the limited battery of energy capacity, and improve the reliability of address decoder.
According to a first aspect of the invention, data communication control processor comprises the receiver of a coded message signal that is transmitted in order to reception, comprises in this signal that the insertion degree of the address that at least one M position of containing nearly N is long is the piece of N, and wherein M and N are integer; A power-supply saving circuit is powered to receiver; The inserter that goes with the receiver coupling goes to insert processing to the coded message signal that receives, to produce the data flow of M * N position; Address correlator with the coupling of removing inserter is sequentially made relevant treatment with a default M position coded word to this M * N bit data stream, to obtain N error count corresponding to N address; Battery saver circuit responds this address and all surpasses one when presetting error count when in N the error count each, and termination is to the power supply of receiver.
According to second aspect present invention, communication control processor comprises the receiver of a coded message signal that is transmitted in order to reception, this signal comprises that a plurality of insertion degree are the message flow of K, this message flow comprise address composition that at least one contains N M position nearly, the insertion degree is the piece of N, K wherein, M and N are integer; A battery saver circuit is powered to receiver; Data selector with receiver coupling, selecting the insertion degree is in the message flow of K one; The inserter that goes with data selector coupling goes to insert to the coded message signal that receives and handles, with generation M * N bit data stream; One with the address correlator that goes inserter coupling, sequentially be scheduled to M position coded word M * N bit data stream made relevant treatment, to obtain N error count corresponding to N address with one; Battery saver circuit in response to the address, and when each of N error count surpasses a default error count, is ended the power supply to receiver.
Fig. 1 is the circuit block diagram of the data communication system of most preferred embodiment according to the present invention.
Fig. 2 be according to the present invention most preferred embodiment in order to handle and to transmit the circuit block diagram of the terminal of information.
Fig. 3-the 5th, the sequential chart of the transformat of the employed signaling protocol of most preferred embodiment of the present invention.
Fig. 6 and 7 is the sequential charts that show the employed synchronizing signal of most preferred embodiment of the present invention.
Fig. 8 is the circuit block diagram of the data communication control processor of most preferred embodiment according to the present invention.
Fig. 9 is the circuit block diagram that threshold level used in the data communication receiver of Fig. 8 is extracted circuit.
Figure 10 is the circuit block diagram of the used 4 grades of decoders of data communication receiver among Fig. 8.
Figure 11 is the circuit block diagram of the used symbol synchronizer of the data communication receiver among Fig. 8.
Figure 12 is 4 grades of used circuit block diagrams to 2 system converters of data communication receiver among Fig. 8.
Figure 13 is the circuit block diagram of the used sync correlator of data communication receiver among Fig. 8.
Figure 14 is the circuit block diagram of the used phase place timing generator of data communication receiver among Fig. 8.
Figure 15 is the flow chart that shows the sync correlation sequence of most preferred embodiment according to the present invention.
Figure 16 is the sequential chart of the used transmission frame structure of demonstration most preferred embodiment of the present invention.
Figure 17 is the sequential chart that shows control word structure used in the most preferred embodiment of the present invention.
Figure 18 is the circuit block diagram of the formatter of the used frame of terminal among Fig. 2.
Figure 19-the 21st, the circuit block diagram of the data concentrator of demonstration most preferred embodiment/distributor operation according to the present invention.
Figure 22-the 24th shows the transmission phase of the most preferred embodiment according to the present invention and the sequential chart that the message traffic bit inserts
Figure 25-the 27th, the sequential chart of the message digit sampling operation in the data communication receiver of demonstration most preferred embodiment according to the present invention.
Figure 28 shows the address of the most preferred embodiment according to the present invention and the sequential chart that data are inserted form.
Figure 29 is the circuit block diagram that the part of the most preferred embodiment according to the present invention is inserted the address correlator.
Figure 30 is the sequential chart that shows that the battery life that obtains because of battery power conservation device circuit operation according to this bright most preferred embodiment improves.
Figure 31 is the flow chart that shows the battery power conservation device circuit operation of most preferred embodiment according to the present invention.
Fig. 1 is according to data communication system 100(of most preferred embodiment of the present invention such as paging system) circuit block diagram.In such data communication system 100, phone (as the system that provides numerical data to transmit) is provided, or result from message as the message input device of alphanumeric data terminal, sent to call terminal 102 by public switched telephone network (PSTN), call terminal 102 is handled these numerals or alphanumeric message information, with the one or more transmitter 104 that is located in the system it is sent.When adopting a plurality of transmitter, these transmitters 104 preferably join information simultaneously delivers to data communication receiver 106.The signaling protocol that the processing of 102 pairs of numerals of call terminal and alphanumeric information and being used for transmits message will be described below.
Fig. 2 sends the circuit block diagram of employed call terminal 102 according to most preferred embodiment of the present invention, in order to processing and control messages information.Abbreviated message (as easily by the push-button phone input, only contain the message and the digital massage of tone) be coupled to call terminal 102 in the mode of knowing in this area by telephony interface 202.Long message (adopting the alphanumeric shuffling message of a data input device as needs) by a modulator-demodulator 206, with any modulator-demodulator transportation protocol of knowing, is coupled to call terminal 102.When the arrangement request that receives a message, 204 pairs of message of controller are handled.Controller 204 is a microcomputer preferably, MC68000 or similar devices as Motorala company product, it can carry out various pre-set programs, maybe can receive terminal operation the symbol of message exchange agreement from data input device to handle the voice suggestion of importing message as indication request person.When receiving a request, controller 204 is consulted the information that exists in the customer data base 208, how to handle the message that receives with decision.Customer data base 208 comprises (but being not limited only to this) these message, as the address of giving data communication receiver, and type of message that interrelates with the address and the information that relates to the data communication receiver state are as to can not the situation of paying the bill having or not response.Be provided with a data input pin 240, it and controller 204 are coupled and are used for doing such thing, as the information that has in the customer data base 208 is imported, upgraded or eliminates, also are used for supervisory control system running and obtain information as the information of paying the bill.
Fig. 3,4 and 5 is sequential charts of the used signaling protocol transformat of explanation most preferred embodiment of the present invention, as shown in Figure 3, signaling protocol is sent to message to distribute to label one or more data communication receiver that is frame 0 in 128 frames of frame 127 is as pager.The actual frame number that provides in the signaling protocol can be said more some more or less than above-mentioned.Used frame number is many more, and the used battery life of the data communication receiver of working in system is long more.Used frame number is few more, and the data communication receiver of distributing to a certain particular frame will be lined up and deliver to message more frequently, thereby reduces the stand-by period, promptly transmits the report required time.
As shown in Figure 4, frame comprises a synchronous coding (Sync), also has thereafter, and 11 information pieces preferably, label are that piece 0 is to piece 10.As shown in Figure 5, each information piece comprises that preferably 8 addresses, control or digital coding words are that word 0 is to word 7 to each phase label.Like this, each can allow to transmit nearly 88 addresses, control and digital coding words mutually in the frame.Address, control and digital coding word preferably 31, the 21BCH coded word is added one the 32nd digit pair odd parity position, and this check digit provides an extra order to coded word group distance, also can adopt other coded word, as 23, the 12Golay coded word.The POCSAG signaling protocol that people know provides and utilizes the first coding word bit to define address and the digital coding word of the type of coded word for data type or address type, and the used signaling protocol of optimum implementation of the present invention is different with the POCSAG signaling protocol, and it does not distinguish address and data like this.Address and digital coding word are here by its determining positions in frame separately.
The sequential chart of Fig. 6 and the used synchronous coding of 7 explanation most preferred embodiments of the present invention.Especially, as shown in Figure 6, synchronous coding preferably includes three parts: one first synchronous coding (synchronous 1), a frame information coded word (frame information) and one the 2nd synchronous coding (synchronous 2).As shown in Figure 7, first synchronous coding comprises first and third part, is denoted as sync bit 1(bit sync 1) and BS1, their provide bit synchronization for 1,0 form alternately; Also comprise the second and the 4th part, they provide frame synchronization to be denoted as " A " and its complement code " A " (" A thick stick ").The second and the 4th part is preferably predefined single 32, the 21BCH coded word, and so that high coded word related reliability to be provided, they also are used for the data bit-rate that explicit address and data are transmitted.The common data bit-rate that uses of following table definition and signaling protocol.
Bit rate " A " value
1600 bps A1 and A1 thick sticks
3200 bps A2 and A2 thick sticks
6400 bps A3 and A3 thick sticks
Undefined A4 and A4 thick stick
As above shown in the table,, address and message preset three data bit rates for transmitting, and certainly also can be according to the default more or less data bit-rate of system requirements.For being equipped with the usefulness in future, also preset the 4th " A " value.
Frame information coding preferably one single 32, the 21BCH coded word, it has comprised the reservation position of preset number in data division, be used for determining frame number, for example is used for determining 7 positions that are encoded of the 0th frame to the 127 frames.
The structure of second synchronous coding preferably is similar to the structure of above-mentioned first synchronous coding.Yet, with preferably with the fixed data symbol rate, as the 1600bps(bit per second) the first synchronous coding difference that transmits, second synchronous coding is transmitted with the data symbol rate of transfer address and message in arbitrary given frame.As a result, second synchronous coding makes data communication receiver transmit at frame and obtains " meticulous " position and frame synchronization under the data bit-rate.
Generally speaking, the used signaling protocol of optimum implementation of the present invention comprises 128 frames, and each frame comprises a default synchronous coding, also has 11 data blocks, every 8 addresses, control or the message coding word of comprising mutually of each data block.Can confirm data transfer rate with synchronous coding, guarantee that data communication receiver is synchronous with the digital coding word that transmits with different transfer rates.
Fig. 8 is the circuit block diagram according to the data communication receiver 106 of most preferred embodiment of the present invention.The heart of this data communication receiver 106 is controllers 816, preferably adopts the MC68HC05HC11 microcomputer of producing as motorola inc as this controller.This micro-computer controller (below be called controller 816) receives and handles the input from the plurality of peripheral circuit, as shown in Figure 8, and controls the operation and the interaction of these peripheral circuits with software routines.Adopting micro-computer controller to handle and control is that those skilled in the art are familiar with.
When partly switching on for receiver at first, during as firm turn-on data communication control processor, by control input end (sampling core) default clock frequency selector 914, to select-128 times of clocks, that is, clock frequency equals 128 times of minimum data bit rate (top mentioned it for 1600bps).128 times of clock signals are produced by 128 times of clock generators 844, and as shown in Figure 8, it preferably is operated in 204.8KH
zThe piezo-oscillator of (KHz), the input of the output termination frequency divider 846 of 128 times of clock generators 844, frequency divider 846 divided by 2, produce 102.4KH with output frequency
z64 times of clocks.Return Fig. 9,128 times of clocks make level detector 902,904 asynchronous detection peak signal amplitude and valley signal amplitude in the very short time, thereby produce required low (Lo) of decode-regulating, average (Avg) and high (Hi) thresholding output signal value.After realizing sign synchronization with synchronizing signal, as below will as described in, controller 816 produces one second control signals (sampling core), sees Fig. 8 to select symbol synchronizer 812() 1 times of symbol clock producing.
Get back to Fig. 8, can more clearly understand the operation of 4 grades of decoders 810 with reference to Figure 10.As shown in the figure.4 grades of decoders 810 comprise 1010,1020,1030 and symbol decoders 1040 of 3 voltage comparators.The restore data signal is received an input of three comparators 1010,1020,1030.High threshold value output signal (Hi) is linked second input of comparator 1010, and average thresholding output signal (Avg) is linked second input of comparator 1020, and low threshold output signal (Lo) is linked second input of comparator 1030.Three inputs of symbol decoder 1040 are linked in the output of three comparators 1010,1020,1030.Symbol decoder 1040 is decoded to input according to following table.
Thresholding output
Hi Avg Lo MSB LSB
RC
in< RC
in< RC
in< 0 0
RC
in< RC
in< RC
in> 0 1
RC
in< RC
in> RC
in> 1 1
RC
in> RC
in> RC
in> 1 0
As above show listedly, when restore data signal (RCin) during less than all three threshold values, the symbol of generation is 00(MSB=0, LSB=0).Afterwards, when each of three threshold values is exceeded, just there is a different symbol to produce, as listed in the table.
The MSB output of 4 grades of decoders 810 connects an input of symbol synchronizer 812, and a restore data input that produces by the zero crossings that detects in the 4 level restoration data-signals is provided.Two overgauges on the occasion of the average relatively thresholding output signal of representative simulation 4 level restoration data-signals of restore data input, two minus deviation of the average relatively thresholding output signal of negative value representative simulation 4 level restoration data-signals.
Can more clearly understand the work of symbol synchronizer 812 from Figure 11.The 102.4KH that frequency divider 846 produces
z64 times of clocks be coupled to an input of 32 times of selectors 1120.32 frequency multiplication selectors 1120 are a frequency divider preferably, it can provide that 1 frequency division and 2 frequency divisions select to produce one 32 times to the sampling clock of symbol transfer rate.A control signal (1600/3200) is coupled to second input of 32 overtones band selectors 1120, and is used for selecting the sampling clock frequency into the symbol transfer rate of per second 1600 and 3200 symbols.Selected sampling clock is coupled to an input of 32 haplotype data oversampling devices 1110, and oversampling device 1110 is taken a sample to restore data signal (MSB) with the frequency of 32 samples of each symbol sampling.The symbol sample is coupled to an input of data boundary detector 1130, and detector 1130 just produces an output pulse when detecting data boundary.Sampling clock also is coupled to an input of 16/32 times of frequency dividing circuit 1140, and this frequency dividing circuit 1140 is used for producing 1 times and 2 times of symbol clocks with the restore data signal Synchronization.16/32 times of frequency dividing circuit 1140 preferably on one/following counter.Just produce a pulse when data boundary detector 1130 detects character boundary, the current counting of this pulse and 16/32 times of frequency dividing circuit 1140 is together by AND gate 1150 gatings.Data boundary detector 1130 also produces a pulse simultaneously, and the latter also is coupled to an input of 16/32 times of frequency dividing circuit 1140.When the pulse of being coupled to AND gate 1150 inputs arrived before 16/32 times of frequency dividing circuit 1140 produces one 32 countings, the counting response that the output that AND gate 1150 produces makes 16/32 times of frequency dividing circuit 1140 is from data boundary detector 1130, be coupled to the pulse of circuit 1140 inputs and advance 1, and when the pulse of being coupled to AND gate 1150 inputs arrives after 16/32 times of frequency dividing circuit 1140 produces a counting, the counting response that the output that AND gate 1150 produces makes 16/32 times of frequency dividing circuit 1140 is from data boundary detector 1130, be coupled to the pulse of circuit 1140 inputs and subtract 1, thereby make 1 times and 2 times of symbol clocks and restore data signal Synchronization.Can more clearly understand the symbol clock frequency of generation from following table.
2 times 1 times of input clock control incoming frequency selector frequency selector
Frequency dividing ratio output symbol clock symbol clock
(relatively) (SPS) (BPS) (BPS)
64 times 1,600 2 32 times 3,200 1600
64 times 3,200 1 64 times 6,400 3200
As above show listedly, 1 times and 2 times of symbol clocks produce with per second 1600,3200 and 6400 bits, and with the restore data signal Synchronization.
Can 4 grades of binary translation devices 814 of clearer understanding from Figure 12.1 times of symbol clock is coupled to first input end of clock of a clock frequency selector 1210, and 2 times of symbol clocks are linked second input of clock frequency selector 1210.Symbol output signal (MSB, LSB) is linked the input of an input data selector 1230.A selector signal (2L/4L) is linked the selector input of clock frequency selector 1210 and the selector input of input data selector 1230, and provides 2 grades of fsk datas of symbol output signal work or 4 grades of fsk data conversion controls.When selecting 2 grades of fsk data conversion (2L), have only MSB output selected, it is linked and is walked to the input of serial converters 1220.The input of 1 times of clock is selected by clock frequency selector 1210, cause and the output that walks to serial converters 1220 produce one 12 system data flow.When selecting 4 grades of fsk data conversion (4L), LSB and MSB output are all selected, and they are coupled to and walk to the input of serial converters 1220.The input of 2 times of clocks is selected by clock frequency selector 1210, cause with 2 times of symbol frequencies and the output that walks to serial converters 1220 produce 2 bit binary data stream.
Get back to Fig. 8, the serial binary data flow of 4 grades of binary translation device 814 generations is coupled to the input of sync word correlator 818 and demultiplexer 820.Can more clearly understand sync word correlator from Figure 13.Controller 816 recovers default " A " word synchronous forms come out and is coupled to " A " word correlator 1310 from coded stack 822.When the synchronous form that receives meets a certain default " A " word synchronous form in acceptable error range, just produce one " A " or " A thick stick " output, controller 816 is linked in this output.This is provided frame synchronization for the section start of frame identification (ID) word by relevant " A " or " A thick stick " synchronous form, and the data bit-rate of decision message then, as previously mentioned.
Serial 2 system data flow are also linked an input of frame word decoder 1320, and 1320 pairs of frame words of this decoder are done decoding and provided an id signal, show the frame number that current positive controlled device 816 receives.In the Synchronous Processing process, after receiver unlatching just, battery saver circuit 848(sees Fig. 8) to the receiver power supply, " A " synchronization character is received, as described above, and continue power supply so that the remainder of synchronous coding obtains handling.Controller 816 is with current received frame number and exist the regulation frame number table in the coded stack 822 to compare.If the frame number of current reception is different with the regulation frame number, controller 816 produces a battery power conservation signal, and the latter links the input of battery saver circuit 848, partly powers for receiver thereby suspend.Be assigned to receiver up to next frame, power supply just recovers; At this moment, controller 816 produces a battery power conservation signal, and the latter is led to battery saver circuit 848, makes receiver partly obtain power supply, to receive the frame that is distributed.
Get back to the operation of sync correlator shown in Figure 13, controller 816 recovers default " C " word synchronous form from coded stack 822, and it is coupled to " C " word correlator 1330.When the synchronous form that receives meets default " C " word synchronous form in acceptable error range, just there is one " C " or " C thick stick " output to produce, and is coupled to controller 816." C " that this specific relevant treatment is crossed or " C thick stick " synchronization character provide " meticulous " frame synchronization for the region frame data section start.
Get back to Fig. 8, the section start of real data part produces a start of block signal (Blk start) by controller 816, and this signal is coupled to a word and removes the input of inserter 824 and the input that data are recovered timing circuit 826.Can clearer understanding data recover timing circuit 826 from Figure 14.A control signal (2L/4L) is coupled to the input of clock frequency selector 1410, and this clock frequency selector 1410 is selected 1 times or 2 letter symbol clock inputs.Selecteed symbol clock is coupled to the input of phase generator 1430; This phase generator 1430 is a timing ring counter preferably, and it is timed to produce four phase output signals (φ 1-φ 4).A start of block signal is also linked an input of phase generator 1430, and is used for ring counter is maintained a pre-phasing, begins up to the actual decoding to information.After start of block signal discharged phase generator 1430, phase generator 1430 just began to produce regularly phase signals, and the information symbol of these signals and input is synchronous.
Referring again to Fig. 8, regularly phase signals output is coupled to the input of phase selectors 828.In the operation, controller 816 recovers to be assigned data communication receiver from coded stack 822 transmission mutually number.Mutually number be transferred to the output of selection mutually (φ selection) of controller 816, and be coupled to an input of phase selectors 828.One is sent at the output of phase selectors 828 corresponding to the compose phase clock that transmits phase, and is coupled to the input that demultiplexer 820, piece go to inserter 824, address and data decoder 830 and 832 respectively.Demultiplexer 820 is used for selecting the binary digit mutually relevant with the transmission of giving, and then it is coupled to the input that piece removes inserter 824, and with its timing going in the inserter array to each corresponding phase clock.Removing the inserter array is one 8 * 32 binary bit arrays, and it inserts address, control or message coding word corresponding to a transmission clock to 8 and goes to insert processing.The geocoding word that goes to insert is coupled to the input of address correlator 830.Controller 816 recovers the address format of giving data communication receiver, and this form is coupled to second input of this address correlator.Remove to insert the geocoding word in acceptable error range during when arbitrary with arbitrary address format coupling of giving data communication receiver, the information of relevant address is just decoded by data decoder 832, and deposits message memory 850 in this area common method.After depositing information in, controller 816 produces one can responsive alarm signal.But this sensitive alarm signal is an audible warning preferably, though but also can adopt other sensitive alarm signal, as haptic alert signal, visual alarm signal etc.Controller 816 is coupled to audible warning the warning driver that is used for driving audio alerting unit such as loudspeaker or conveyer 836.The user can replace the generation of alarm signal by this area common method with user's input controller 838.
After detecting the address relevant with data communication receiver, information just is coupled to the input of data decoder 832; (preferably) BCD or ASC II form that this decoder 832 becomes to be suitable for storing and shows subsequently the coded message information decoding.When controller 816 recovered information from memory, the user called stored information information with regard to available subscribers input control 838, and provides it to display driver 840, with at display 842, as showing on the LCD display.
Figure 15 is the operational flowchart of the data communication receiver of most preferred embodiment according to the present invention.In step 1502, when the turn-on data communication control processor, controller is started working in step 1504, and the receiver part is powered periodically, makes it to receive the information on the RF passage that appears at appointment.When in default a period of time, in passage, not detecting data, then recover the battery power conservation operation in step 1508.When detecting data in passage (step 1506), sync word correlator begins to search bit synchronization in step 1510.When step 1510 obtains bit synchronization, then in step 1512 beginning " A " word relevant treatment.When detecting non-complement code " A " word in step 1514, message delivery rate such as above-mentioned method are identified and owing to obtained frame synchronization in step 1516, so in the zero-time (T1) of step 1518 acknowledgement frame recognition coding word.When not when step 1514 detects non-complement code " A " word, show that mass-sending is wrong during non-complement code " A " word may be transmitted to disturb, then determine whether to detect complement code " A thick stick " word in step 1520.When not detecting " A thick stick " word in step 1512, show " A thick stick " word also may be transmitted in the wrong interference of mass-sending, then recover the battery power conservation operation again in step 1508.When detecting " A thick stick " word in step 1520, then message delivery rate is discerned as described above in step 1522, and owing to obtain frame synchronization, so in step 1524, the zero-time (T2) of frame recognition coding word is identified.In due course, decode at step 1526 pair frame identifier word.When detected frame identification and the frame identification of giving data communication receiver not (step 1528) simultaneously, then recover the battery power conservation operation in step 1508, and with it maintenance so up to receiving next assignment frame.At step 1528 decoded frame sign and a frame identification that distributes at once, then at step 1530 setup message acceptance rate.Then attempt making bit synchronization with message delivery rate in step 1532.When step 1533 obtains bit synchronization, in step 1534 beginning " C " word relevant treatment.When detecting non-complement code " C " word in step 1536, just obtain frame synchronization, and the zero-time (T3) that transmits in step 1538 acknowledge message.
When not detecting non-complement code " C " word in step 1536, show that non-complement code " C " word may be subjected to mass-sending wrong interference in transmission, so determine whether to detect complement code " C thick stick " word in step 1540.If do not detect complement code " C thick stick " word, show that " C thick stick " word may be subjected to mass-sending wrong interference, the work that then recovers the battery power conservation device in step 1508 once more in transmission in step 1540.If detect " C thick stick " word in step 1540, then obtain frame synchronization, and the zero-time (T4) that transmits in step 1542 acknowledge message.Carve in due course and can begin to carry out source codec in step 1544.
Generally speaking, by a plurality of synchronous coding words that separate in time are provided, improved greatly with being subject to mass-send the reliability that the wrong synchronizing information of disturbing makes Synchronous Processing.Adopt two synchronous coding words, one of them default synchronous coding word is as the first synchronous coding word, and another is the second default coded word of the complement code of the first default coded word, has guaranteed first or in second precise synchronization of presetting on the coded word.By the synchronous coding word is decoded, can obtain additional information, as rate of data signalling, carry out thereby make under the several data bit-rate speed of being transmitted in of information.By adopting second code synchronism word right, can be implemented in " meticulous " frame synchronization under the real messages rate of information transmission, and separate in time owing to the synchronous coding word again, improved greatly with being subject to mass-send the wrong synchronizing information of disturbing makes Synchronous Processing under the different pieces of information bit rate reliability, thereby improved that data communication receiver receives and to receiving the reliability that the user gives information.
Figure 16 is the sequential chart according to the transmission frame structure of most preferred embodiment of the present invention.Address once more as shown in Figure 16 as prior figures 4, transmit frame and comprise a synchronous coding word 1600, the back is connected to 11 data blocks, is designated as piece 0 to piece 10.Address, control and message blocks are distributed in 11 data blocks by preset order.Be positioned at first coded word of piece 0, always the block message coded word 1602, and it comprises the information as the original position of address field 1604 and vector field 1606, and remaining 87 coded words can be used for the transmission of address, vector sum digital coding word.By knowing the original position of address field 1604 and vector field 1606, controller can calculate the geocoding number of words order that every frame need be decoded, to determine message when occurs in the frame.As a result, address field 1604 comprises the one or more geocoding words corresponding to report in data field 1608.The geocoding word that only indicates numeral and alphanumeric shuffling information just contains corresponding message and is arranged in data field 1608.Only contain the message of tone owing to, in data field 1608, do not have corresponding message not with message part.To truly having the geocoding word of corresponding message, vector field 1606 comprises control word or claims vector, it determines message initial and end position in data field 1608, and relation is one to one arranged between geocoding word in address field 1604 and the vector in vector field 1606.
Figure 17 is the sequential chart of display frame information Control word 1702, and frame information control word 1702 is that the part as the synchronizing information of describing in the prior figures 7 is transmitted.As shown in figure 17,4 positions 1704 are used to define loop No. (0 to No. 14).When transmitting 128 frames in single cycle period, 15 128 frames required delivery time of circulating is 1 hour.Circulation 0 is always initial every 1 hour, so can draw the current time by the cycle frame counting.7 positions 1706 are used to define frame number (0-127 number).Other 4 positions 1708 are used to show that the address only is positioned at first transmission block (piece 0), when result's any in position 1708 is set, the battery power conservation performance that all can obtain adding, as among following Figure 29 will as described in.
Figure 18 is the circuit block diagram that is used in the frame formatter 212 in the controller of Fig. 2.As mentioned above, received message deposits in the active paging memory 210.Active paging memory 210 is the random access memory of dual-port, first-in first-out preferably, and it is further transmitted phase by message again and describes, and it stores message with the order that transmits the message received of joining according to the message of giving data communication receiver.Certainly the also memory of available other type, as available hard drive as active paging memory 210.
The controller 1902 that has output 1904 periodically (transmits frame period once as each) and sequentially recovers to exist message information storage area, the active paging memory 210 of representative to transmit the message of phase.The message that recovers is coupled to the input of frame decoder 1906, and frame decoder is confirmed to transmit image duration with message that is transmitted and the message that will be transmitted current during one or more subsequent frame transmits.Submit in May, 1992 by Sehwendeman etc., title is U.S. Patent application No07/891363 " data communication receiver of the long message carry of belt variable ", that entrust to assignee of the present invention, be used as documents at this, wherein separated the operation of the frame formatter of counting successive frame.Detecting message and this message in transmitting mutually in arbitrary message will be when current transmissions be transmitted image duration, then message detection signal that is coupled to controller 1902 of frame decoder 1906 generations.Then controller 1902 is analyzed relevant information, to determine that message transmits required coding number of words.According to the transmission frame of the message of giving recovery, controller 1902 is coupled to a framing counter 1908 with the message coding word count that obtains, and frame counter 1908 keeps the tale of the required message coding word of present frame (N).The message of current transmission frame deposits current transmission frame buffer register 1910 in.When the coded word counting that keeps for present frame (N) when frame counter 1908 surpassed default frame transmission queue capacity (being aforesaid 87 coded words), the detected message that has more was deposited in and is loaded buffer register 1912 when reading active paging memory 210.Exist loading the message that has more in the buffer register 1912 will or be transmitted in the follow-up transmission frame more than three at one, as people such as Schwendeman are described.
After all message of current transmission frame are resumed, exist message in the current transmission frame buffer register 1910 to be coupled to the input of data concentrator 1914, data concentrator 1914 is handled the message that exists corresponding in four information storage areas that transmit phase according to message transmission speed.The message of concentrating is coupled to the input of data distributor 1916 subsequently, and data distributor 1916 is given frame message buffer register 216 according to transfer rate with the distribution of messages of concentrating again.The Message Processing of Chuan Songing is carried out as described in Figure 2 like that afterwards.
Figure 19-the 21st, demonstration is according to the circuit block diagram of the work of the data concentrator/distributor of most preferred embodiment of the present invention.Data concentrator 1914 preferably 4 lines able to programme to 1 line, the demultiplexer of 2 lines or 4 lines, it operates 1902 controls of controlled device.Data distributor 1916 is programmable 1 line preferably, and 2 lines or 4 lines are to 4 line multiplexers, and the also controlled device 1902 of its operation is controlled.The operation of data concentrator 1914 and the data distributor 1916 all customary software of available microcomputer realizes.
When message data will transmit with per second 1600 bits (bps), exist four of the current transmission frame buffer register message sums that transmit in the phase regions to be generally 87 of no message loading or coded word still less, and generally be less than 1.5 times or 2 times of 87 coded words of message.Yet, when surpassing two times of coded word that 87 message load, preferably change next transfer rate in present frame transmission queue.As shown in figure 19, data concentrator 1914 is attached to a serial output terminal with 4 contents that send phase, and these contents are redistributed to four two (1 and 3) in the transmission mutually of frame message buffer registers then.Two frame message buffer registers transmit phase (2 and 4) and are linked a logical zero end by data distributor, the frame message buffer register of packing into then in addition.The content of frame message buffer register is by further processed for transmitting (as described in top Fig. 2), and be added to the input of 4 grades of FSK modulators at conveyer place, transmit 2 and 4 logical zero input mutually owing to offer the frame message buffer register, this just is directed at 2 grades of FSK message modulation and occurs in 1600bps, corresponding to the symbol frequency of 1600 symbols of per second.
If will transmit message data with per second 3200 bits (bps), then exist 4 of the above-mentioned current buffer register sums that transmit in the phase regions generally to be twice in 87 or the coded word that still less loads, and be generally less than three times or four times of coded word of 87 band message loading in no message.Yet, when 4 times of the present frame transmission queue coded words of the band message loading above 87, preferably change follow-up transfer rate.As shown in figure 20,4 contents (1 and 2 that transmit phase, 3 and 4) be combined into dual serial output (2 and 3) by data concentrator 1914, redistributed to 4 frame message buffer registers according to distributor 1916 by data then and transmit phase (giving 1 and 3,2 and 4 respectively).The frame message content of buffer is by further processed for transmission, as described in Figure 2, and is added to the input of 4 grades of FSK modulators at conveyer place, causes 4 grades of FSK modulation to produce with 3200bps, and this is also corresponding to the symbol frequency of per second 1600 symbols.
If will transmit message data with per second 6400 bits (bps), to have 4 of the above-mentioned current frame buffer register message sums that transmit in the phase regions generally be 87 or still less do not load 4 times of coded word with message, and generally be less than 87 6 times or 8 times of being with message loading coded words, load though lean against 16 times the message of forcing loading may reach 87 coded words in follow-up three transmission frames.As shown in figure 21,4 contents that transmit phase are directly delivered to the frame message buffer register by data concentrator 1914 and data distributor 1916.The content of frame message buffer register is further processed so that transmit, as described in Fig. 2, and be added to the input of 4 grades of FSK modulators at conveyer place, and this just causes 4 grades of FSK to be modulated at 6400bps producing down, and this is corresponding to the symbol rate of per second 3200 symbols.
Generally speaking, frame formatter be used for retrieving exist in the active paging memory shown in Figure 2, prepare the message that will transmit.Frame formatter formats message data, so that can be enough, preferably 4 grades of FSK modulators transmit under three selected transfer rates, thereby when the message number that system receives increases message handling ability is also increased.
Figure 22-the 24th shows according to the transmission phase of most preferred embodiment of the present invention and a sequential chart that inserts of message transmission.Described in Fig. 4 and Fig. 8, each transmission block comprises 8 32 coded words, these coded words are encoded as address, control or digital coding word by the signaling protocol of most preferred embodiment of the present invention, and the method that the those of ordinary skill that uses frame message to insert with this area is subsequently known is inserted into processing.Because as mentioned above, message exists in the transmission mutually, and the message during each transmits mutually is by absolute coding and insertion.According to message delivery rate, exist in arbitrary transmission mutually the transmission frame data can with exist other transmission frame data in transmitting mutually relevant, perhaps with have other transmission mutually in transmission frame data message irrelevant fully, as described in Figure 19-21.When the transmission frame data were finally handled for transmission, each transmission frame data that transmit phase was modulated to together by a phase multiplexer, thereby the transmission frame data that inserted are done further to insert processing.
Get back to Figure 22, when transmission frame data 2502 are transmitted by the effective speed with per second 1600 bits, message digit information 2504,2506,2508 usefulness usual manners, appear at 2 grades of FSK modulation formats and to transmit on the passage, these 2 grades of FSK modulation have a bit period 2512, are equivalent to per second 1600 Bit datas and insert, message 1(2504) back, position zero (BOM1) is message 2(2506 and then) position zero (BOM2), the rest may be inferred.Transmit frame data and derive from four transmission phases 2510, and explained by data communication receiver as the individual data position that the speed with per second 1600 bits transmits.
Get back to Figure 23, when transmitting frame data 2602, when 2604 effective speeds with per second 3200 bits are transmitted, message digit information 2606,2608,2610,2612,2614 and 2616 usefulness nconventional methods, appear at 4 grades of FSK modulation formats and to transmit on the passage, the bit period 2620 of this modulation is equivalent to per second 3200 Bit datas and inserts, the message 1(2612 of second group of data communication receiver is and then guided in zero (BOM1) back, position of guiding to the message (2606) of first group of data communication receiver) position zero (BOM1), by that analogy.Transmit frame data and still derive from 4 transmission phases 2618, but be interpreted as two uncorrelated data flow by the data communication receiver group, each data flow transmits with per second 1600 bit speeds.
Get back to Figure 24, when transmitting frame data 2702,2704,2706 and 2708 when being transmitted with the effective speed of per second 6400 bits, message digit information 2710,2712,2714,2716,2718 and 2720 forms with 4 grades of FSK modulating datas inserting with nconventional method appear at and transmit on the passage, 6400 bits such as bit period 2722 per seconds such as grade of this modulation, this insertion method is such, guides the message 1(2710 of first group of data communication receiver into) zero (BOM1) back, position with the message 1(2716 that guides second group of data communication receiver into) position zero (BOM1), thereafter again with the message 1(2718 that guides the 3rd group of data communication receiver into) position zero (BOM1), also transmit the message 1(2720 of receiver with guiding the 4th group of data into thereafter) zero-bit (BOM1), by that analogy.Transmit frame data and still derive from 4 transmission phases 2722, but be interpreted as 4 non-relevant data streams by 4 groups of signal communication receivers, each data flow transmits with the speed of per second 1600 bits.
Generally speaking, message is distributed on the passage one, is transmitted between end and transmitter with the constant effective speed of per second 6400 bits.Yet, how in 4 transmission mutually, to format according to message, and which synchronous coding word is transmitted, as mentioned above, the message that is transmitted is interpreted as being sent to the constant effective transfer rate of per second 1600 bits the message of 1,2 or 4 groups of data communication receivers of message by the data communication receiver.
Figure 25-the 27th shows the sequential chart according to the data communication receiver position sampling operation of most preferred embodiment of the present invention.As mentioned above, the bright relative transfer rate of the synchronous coding word table that is transmitted is per second 1600 bits, per second 3200 bits or per second 6400 bits.Compose when each data communication receiver begins to 4 and transmit phase φ 1, φ 2, and one among φ 3 and the φ 4 mutually.Below will there be the message of per second 1600 bits to transmit if the synchronous coding word table that receives is bright, among Fig. 8 phase selectors 828 accessed be that the phase clock of 1600bps offers multiple decomposer 820, piece removes inserter 830, address correlator 830 and data correlator 832 to select all 4 outputs, to produce a bit rate.As indicating the shown in Figure 25 of per second 1600 bits (1600bps), this produces the message digit that message is taken a sample by all data communication receivers, and the transmission phase no matter these data communication receivers are given; Sampling is to carry out with the center of per second 1600 Bit data positions.
If the bright transmission that per second 3200 bits will be arranged of synchronous coding word table that receives, phase selectors 828 among Fig. 8 is accessed, selecting 42 in the output mutually, be the phase clock of per second 1600 bits thereby produce one during transmitting phase φ 1 and φ 2 or during transmitting mutually φ 3 and φ 4, bit rate; This phase clock is provided for demultiplexer 820, piece removes inserter 822, address correlator 830 and data correlator 832.As indicate the shown in Figure 26 of per second 3200 bits (3200bps), this produces message by (first group: φ 1 and φ 2 of 2 groups of data communication receiver, second group: φ 3 and φ 4) sampling message digit, sampling is that carry out at the data bit center of 3200bps at transfer rate, transmits the amount of information that transmits in the passage and doubles thereby make effectively.
To there be the message of per second 6400 bits to transmit if the synchronous coding word table that receives is bright, phase selectors 828 among Fig. 8 is accessed to select four in the output mutually, thereby produce a phase clock, this phase clock is transmitting phase 1,2, produce with per second 1600 bits during 3 and 4, this phase clock is provided for multiple decomposer 820, piece removes inserter 822, address correlator 830 and data correlator 832.With indicate the shown in Figure 27 of per second 6400 bits (6400bps), this produces by (first group: 1 of four groups of data communication receiver, second group: 2, the 3rd group: 3, the 4th group: 4) Qu Yang message digit, sampling occurs in the center that transfer rate is the data bit of 6400bps, thereby makes the amount of information that transmits in the transmission passage increase by four times effectively.
The sampling operation that controller 814 is controlled the data that receive, as shown in Figure 8, sampling operation produces 1 sampling pulse under the 1600bps bit rate, produces 2 sampling pulses under the 3200bps bit rate, produces 4 sampling pulses under the 6400bps bit rate; It all is the center with the data bit that sampling pulse transmits bit rate at each.Transmit the selections that recover which data bit under the bit rates at three, the phase clock that produced by phase selectors is controlled, and the transmission that is prescribed reception as described above at first based on each data communication receivers mutually.
Can clearer understanding battery power conservation device operation from Figure 28-31.Figure 28 is the address of explanation most preferred embodiment according to the present invention, the sequential chart that the vector sum data are inserted form.As shown in Figure 28 and front Figure 17, signaling protocol comprises a synchronous coding word 2802, also has 11 transmission block 2804-2824 thereafter.Have a block message coded word at least at transmission block 0(2804) in be transmitted, its heel has adjustable length address, vector sum data field; This length of field depends on address number and the type of message that is transmitted, as pure pitch type, numeric type or alphanumeric shuffling type.All transmission blocks are gone at the receiver place to insert, described in top Fig. 8, yet, thereby address information needn't go fully to insert to make address decoder and provide and add the battery electricity saving performance, as described below.
Get back to Figure 28, the information that transmits in transmission block 2804 to 2824 is inserted into processing by inserting shown in Figure 28 26.In inserting Figure 28 26, to each transmission block at first long N the least important coding word bit of M in the transmission block (M=32 N=8), transmits time unessential, by that analogy subsequently.To inserting this first least significant bit of coded word at last for the load mode of most significant bit also provides additional battery power conservation performance, this point can more clearly understand from Figure 29.
Figure 29 is the circuit block diagram that the part of the most preferred embodiment according to the present invention is inserted the address correlator.When the structure of address correlator is arranged to such an extent that be suitable for part insertion address relevant treatment, demultiplexer 820 shown in Fig. 8 according to rate of data signalling with give receiver mutually, select the address information of recovery, and it is added to the input that piece removes inserter 824.Address information also is concatenated into input, the address correlator 830 of address correlator 830 and directly handles the insertion address information, and is as described below.Piece goes inserter to be used for recovering the block message word and the vector sum information of transmission in piece 0, and is as described above.
The (see figure 8) phase clock by mutually timing generator 826 and phase selectors 828 generations synchronous with data recovered is coupled to shown in Figure 29 input end of clock that removes inserter 824, so that data recovered periodically enters inserter, phase clock also is coupled to the input end of clock of address correlator 830, or rather, be coupled to the input end of clock of address bit demultiplexer 2902.Address bit demultiplexer 2902 a sequentially ground is selected input among 8 address correlator 2904-2918, handles thereby executive address goes to insert.Address format corresponding to address that data communication receiver is composed is added to second input of address correlator 2904-2918.This address correlator is the bit-errors detector preferably, and it comprises a comparator, compares with the address of giving data communication receivers in each 1 mode accordingly in order to the address information to recovery, thereby carries out 8 address relevant treatment basically concurrently.When arbitrary address correlator detects bit-errors (as two) more than preset number, just produce an output, it is coupled to the error detection input of the controller 816 that also is shown among Fig. 8.The address relevant treatment is proceeded, and up to detecting an address, in other words, receives that at least one has the address of receipts less than pre-determined bit mistake number, and perhaps up to finding that all addresses have the bit-errors greater than predetermined number, battery power conservation operation at this moment is activated.Above-mentioned battery power conservation operates in prior to the relevant complete block that carries out in address and when going to insert, makes the battery power conservation operation early than the time that may reach originally.
Correlator is operated (not shown) among another embodiment in address of the present invention, and data recovered is removed inserter by a ground timing input block as described above.Yet different with the foregoing description, address information goes to recover with one time one row ground of byte form the inserter from piece, and is coupled to the input of address correlator 2904-2918.Bit-errors detects relevant control with the address as hereinbefore.
The frame information control word that is transmitted as a synchronous coding part comprises 4, and the latter is used to confirm whether address information is defined as piece 0, and perhaps whether address information expands in the extra block.For convenience of description, it should be noted that when the message transmission is limited to 10 character digital massages (as telephone number), can transmit nearly 22 addresses in the single transmission frame.Figure 30 is the sequential chart that shows that battery life most preferred embodiment, that get because of the operation of battery power conservation device improves according to the present invention.Waveform 3002 and 3004 is represented a underloading system, transmits as the address to be limited to maximum 7 addresses of transmission block 0() system.Waveform 3006 and 3008 is represented loading system in, transmits as the address to be limited to transmission block 0 and maximum 15 addresses of 1() system.Waveform 3010 and 3012 is represented a fully loaded system, transmits as the address to be limited to transmission block 0,1 and maximum 22 addresses of 2() system.
Consider the underloading system, waveform 3002 is described the battery power conservation factor, and the battery power conservation factor must be received and go to insert so that just can obtain when making address decoder at whole pieces 0.As shown in the figure, the added electric power of receiver adds up to 450 (10 are used for the receiver preheating, 184 synchronous coding word bits and 256 piece 0 coding word bits) in the frame 3000, thereby obtains 6.67 to 1 the battery power conservation factor.Yet in most preferred embodiment of the present invention, because the data of inserting are walked around piece mostly and are removed inserter, as mentioned above, decoder can determine that in the beginning bit address information that receives each 8 of can be transmitted possibility address detecting probability wrong more than two in piece in each address of 8 addresses is 47% in the required time.The result address decoding is ended in advance, and battery power conservation begins.When operating part inserts address decoder, under best-case, the added electric power of receiver is only corresponding to 266 in 3000, produce 11.28 to 1 battery power conservation duty factor, when whether all 32 of all 8 geocoding words must be received when existing with the decision address, the power supply of receiver drops to worst condition, and it is 6.67 to 1 that battery power conservation fills duty factor.
When inserting address decoder with part, similarly battery power conservation improves and also occurs in middle loading system and the fully loaded system.In middle loading system, when requiring that piece goes to insert completely, can get 4.25 to 1 the battery power conservation factor, shown in waveform 3006, if operating part inserts address decoder when receiving address information, the battery power conservation factor is 5.75 to 1, shown in waveform 3008.In fully loaded system, when requiring that piece goes to insert completely, can obtain 3.12 to 1 battery and save the factor, shown in waveform 3010, as a comparison, if operating part inserts address decoder when receiving address information, then can get 4.97 to 1 the battery power conservation factor, shown in waveform 3012.In waveform 3012, battery power conservation also can begin in transmission block, for example when not being checked through the address in transmission block 1.When confirming in transmission block 2, to have extra address being transmitted (as shown), corresponding to before transmission block 2 section starts 10 power up, once more so that the receiver preheating, power up corresponding additional at least 72 or up to definite zero-address existence or detect an address afterwards again.
Figure 31 shows the operational flowchart that partly inserts another embodiment of address decoder according to the present invention.When a column address information is transfused to inserter, it is described like that to insert another embodiment of address decoder as top part, and in step 3102, block of bytes insertion data are sent to the address correlator.The byte of inserting data at this piece of step 3104 compares by turn with the address bit of giving corresponding to these row (therefrom insert data be transmitted).In step 3106, when the position (n) and the assigned address position that are subjected to comparison are not inconsistent,, rised in value corresponding to the error counter (n) of the position that is subjected to comparison in step 3108.In step 3110, a location index (n) is rised in value, and in step 3112, when n was not equal to 8, then the position of next byte (n) compared in a manner described in step 3104.In step 3112, when the bit position index value equaled 8, controller was checked to determine whether that all error counter values are all greater than 2 in step 3114.When all error counter values all greater than 2 the time, in step 3116, the power supply of receiver is ended, the battery power conservation operation is carried out in a manner described.In step 3114, when one or more error counter values were not more than 2, controller was checked to have determined whether the ending of piece in step 3118.In step 3118, if do not arrive the piece tail, then in step 3122, a column position index is rised in value, afterwards execution in step 3102 to 3118 once more as stated above.When step 3118 detects EOB, show promptly to detect an address that the value of error counter is recomputated; In step 3120, when the value of finding arbitrary error counter less than 3 the time, address detected is confirmed, and produces one and show the alarm that receives an address.
In a word, part insert address decoder can be as shown in figure 29 order or with byte mode data recovered is decoded like that as shown in figure 31 like that.The decoding of byte type can be carried out decoding function with microcomputer.Partial decoding of h to the address continues to carry out, and all addresses are identified all and the mail returned on ground of incorrect address of giving data communication receiver in inserting piece, at this moment can begin the battery power conservation operation.By as stated above the address being inserted, can not lose or mass-send under the error protection situation because of weakening, transmit the address that obtains high data rate.When adopting high-speed data transfer, guide into not the address of data communication receiver on the same group can be further as described above by inserting mutually, thereby can decode to the address information of inserting with bit rate far below actual address transfer rate in the passage.Send out now when being drawn towards not on the same group the address of insertion mutually of data communication receiver, it is unaffected that part is inserted the decoding of address.
Claims (10)
1, communication control processor comprises:
A receiver, in order to the coded message signal that reception is transmitted, that the latter comprises is that at least one is made up of the address of N M position nearly, the insertion degree is the piece of N, wherein M and N are integer;
Be used for device to described receiver power supply;
With the device that described receiver is coupled, the coded message signal that is used to recover to receive is to produce nearly M N bit data stream.
With the device of described recovery device coupling, in order to the appropriate section of an at least a portion in the data flow of M N position and a default M position coded word is carried out relevant treatment, to obtain corresponding to N the error count that reaches N receiver address;
Respond described relevant apparatus and with the device of described electric supply installation coupling, in order to termination when in N the error count each is all preset error count above a receiver is powered.
2, according to the communication control processor of claim 1, wherein said abortion means is equal to or greater than the power supply of ending receiver in 3 o'clock in each of N error count.
3, according to the communication control processor of claim 1, the wherein said device that is used for powering when any of N error count in the power supply of M * when the N bit data stream is made relevant treatment being kept less than 3 time to described receiver.
4, according to the communication control processor of claim 1, the wherein said device that is used to power is given described receiver power supply in a minimum Preset Time interval.
5, according to the communication control processor of claim 4, wherein said electric supply installation is powered to described receiver during minimum two N bit data streams.
6, communication control processor comprises:
A receiver, in order to the coded message signal that reception is transmitted, this signal comprises that a plurality of insertion degree are the message flow of K, that these message flows comprise is that at least one is made up of the address of N M position nearly, the insertion degree is the piece of N, K wherein, M, N are integer;
In order to give the device of described receiver power supply;
With the device of described receiver coupling, in order to being to select one the message flow of K from the insertion degree;
With the device of described choice device coupling, the message flow that is used to recover to select is to produce the nearly data flow of M N position.
With the device of described recovery device coupling, make relevant treatment in order at least a portion with the appropriate section of a default M position coded word to M N bit data stream, with acquisition corresponding to N the error count that reaches N address, and
With the device of described electric supply installation coupling, all surpass the power supply of a termination when presetting error count to described receiver in order in N error count each.
7, according to the communication control processor of claim 6, wherein said abortion means each in N error count is equal to or greater than the power supply of ending described receiver in 3 o'clock.
8, according to the communication control processor of claim 6, wherein said electric supply installation is kept described receiver power supply less than 3 the time during the step of M N bit data stream being made relevant treatment when in the error count of the N in the message flow of selecting any.
9, according to the communication control processor of claim 6, wherein said electric supply installation is powered to described receiver in minimum two N bit data streams during selected message flow.
10, according to the communication control processor of claim 6, further comprise the device with the coupling of described receiver, being used for synchronously described is that the message flow of K is selected one choice device from the insertion degree.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US90827192A | 1992-07-02 | 1992-07-02 | |
| US908,271 | 1992-07-02 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1082268A true CN1082268A (en) | 1994-02-16 |
| CN1028825C CN1028825C (en) | 1995-06-07 |
Family
ID=25425487
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN93108072A Expired - Fee Related CN1028825C (en) | 1992-07-02 | 1993-07-01 | Power saving device for data communication receiver |
Country Status (4)
| Country | Link |
|---|---|
| CN (1) | CN1028825C (en) |
| MX (1) | MX9303846A (en) |
| TW (1) | TW258847B (en) |
| WO (1) | WO1994001841A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102075229A (en) * | 2010-12-07 | 2011-05-25 | 北京慧达天成信息技术有限公司 | Beidou satellite-based transparent data transmission device |
| CN105393512A (en) * | 2013-06-25 | 2016-03-09 | 康杜实验室公司 | Vector signaling with reduced receiver complexity |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1126378C (en) * | 1997-01-17 | 2003-10-29 | 松下电器产业株式会社 | Message receiver |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0824386B2 (en) * | 1986-09-30 | 1996-03-06 | 日本電気株式会社 | Selective call signal receiver |
| US4914649A (en) * | 1988-09-12 | 1990-04-03 | Motorola, Inc. | Multiple frequency message system |
| US4996526A (en) * | 1988-12-01 | 1991-02-26 | Motorola, Inc. | Power conservation method and apparatus for a portion of a synchronous information signal |
| US5051993A (en) * | 1989-03-30 | 1991-09-24 | Motorola, Inc. | Mixed modulation level communication system |
| US5128665A (en) * | 1989-08-21 | 1992-07-07 | Motorola, Inc. | Selective call signalling system |
| WO1991010331A1 (en) * | 1990-01-02 | 1991-07-11 | Motorola, Inc. | Time division multiplexed selective call signalling system |
-
1993
- 1993-06-09 WO PCT/US1993/005452 patent/WO1994001841A1/en active Application Filing
- 1993-06-25 MX MX9303846A patent/MX9303846A/en unknown
- 1993-07-01 CN CN93108072A patent/CN1028825C/en not_active Expired - Fee Related
- 1993-07-06 TW TW082105362A patent/TW258847B/zh active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102075229A (en) * | 2010-12-07 | 2011-05-25 | 北京慧达天成信息技术有限公司 | Beidou satellite-based transparent data transmission device |
| CN105393512A (en) * | 2013-06-25 | 2016-03-09 | 康杜实验室公司 | Vector signaling with reduced receiver complexity |
| CN105393512B (en) * | 2013-06-25 | 2019-06-28 | 康杜实验室公司 | Vector signaling with low receiver complexity |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1028825C (en) | 1995-06-07 |
| WO1994001841A1 (en) | 1994-01-20 |
| TW258847B (en) | 1995-10-01 |
| MX9303846A (en) | 1994-05-31 |
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