CN108108312A - A kind of cache method for cleaning and processor - Google Patents
A kind of cache method for cleaning and processor Download PDFInfo
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- CN108108312A CN108108312A CN201611067101.6A CN201611067101A CN108108312A CN 108108312 A CN108108312 A CN 108108312A CN 201611067101 A CN201611067101 A CN 201611067101A CN 108108312 A CN108108312 A CN 108108312A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
- G06F12/121—Replacement control using replacement algorithms
- G06F12/122—Replacement control using replacement algorithms of the least frequently used [LFU] type, e.g. with individual count value
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
- G06F12/0873—Mapping of cache memory to specific storage devices or parts thereof
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0877—Cache access modes
- G06F12/0886—Variable-length word access
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
This application involves processor technical fields, and in particular to a kind of cache method for cleaning and processor.This method includes：Processor determines the target cache line in the cache；Processor reads the effective information that the target cache line is corresponded in the memory；When the processor determines that the target cache line fails according to the effective information, the target cache line is replaced；Or, when the processor determines that the target cache line is effective according to the effective information, retain the target cache line.It needs to judge the validity of the target cache line according to effective information in the application, the target cache line only to fail can be just replaced, and effective target cache line is then still present in cache, cache miss rates can be reduced, reduction system is to the demand of cache capacity, so as to reduce the use power consumption of CPU, so as to which reduce system builds cost and use cost.
Description
Technical field
This application involves processor technical fields by the application, and in particular to a kind of cache method for cleaning and processor.
Background technology
Cache (cache) is to be present in memory and central processing unit (CPU, Central Processing Unit)
Between memory, by static RAM (SRAM, Static Random Access Memory) form, capacity
But speed smaller than memory is more much higher than memory, close to the speed of CPU.In the hierarchical structure of computer memory system, it is
High speed small-capacity memory between central processing unit and main storage, it forms the storage of level-one with main storage together
Device.Between cache memory and main storage information scheduling and transmission carried out automatically by hardware.
It is more many soon than memory read-write rate that the appearance of cache is primarily due to CPU arithmetic speeds, can so make CPU
It takes a long time and pending datas is waited to arrive or write the data to memory.Data in the caches are the small portions in memory
Point, but this sub-fraction is that CPU will be accessed in the short time, when CPU calls mass data, so that it may avoid memory directly from
It is called in cache, so as to accelerate reading rate.Cache is very big on the performance influence of CPU, and main cause has the number of CPU
According to the bandwidth between exchange sequence and CPU and cache, wherein, the order for reading data influences whether the reading life of cache
Middle rate, the reading hit rate are an important parameters of cache, and cache is generally also used in processor technical field
The reading miss rate of miss rates, i.e. cache characterizes reading hit rate, and when cache miss occur, i.e. CPU will be read
Not in the caches and in memory, processor needs that pending datas is waited to read in cache from memory the data taken；And at a high speed
The bandwidth of caching reads the speed of cached data by CPU is directly affected, i.e., CPU is read from cache in the unit interval
Data volume size, two combinations can influence the efficiency of whole system.
In order to improve the utilization rate of cache, cache can be divided into multiple cache lines with fixed size
(cache line), it is also in units of cache lines, for example, the big I of each cache lines that CPU, which is written and read cache,
To be 32Byte or 64Byte, since the capacity of cache is much smaller than memory, most common data pre-fetching can only be stored in high
In speed caching, so inevitably not in the caches and in memory, that is, cache occurs for the CPU numbers to be read
The situation of miss just needs from the memory lookup data and reads in cache at this time, and the data of reading need to occupy slow at a high speed
The memory space deposited, and since the total capacity of cache is smaller, cause the quantity of cache lines to have the upper limit, therefore for slow
It deposits line and has some suitable replacement policies, at least used and the least frequent preferential superseded or advanced newly side of going out such as recent
Formula, and these replacement policies are the judgement that CPU is voluntarily carried out, it is possible that it is that will use that some, which replace out content,
, cache miss rates thus can be caused to increase.
The content of the invention
It is existing since CPU voluntarily judges to delay at a high speed to solve that the embodiment of the present application provides a kind of cache method for cleaning
The content to be replaced in depositing so that replace out content may be i.e. will be to be used, so as to can cause cache miss rates increase
The problem of.
In view of this, the application first aspect provides a kind of cache method for cleaning, in this method, to be removed in processor
A memory with cache with speed step is additionally provided with outside cache, for store part in cache or
The effective information of the cache lines of person's whole, when processor into cache write data when, when find cache
When not having enough space write-in data, the part cache lines in cache are just replaced with to the number of write-in when writing data
According to, at this point, the cache method for cleaning includes, the target cache line in cache is determined by processor first, determine
The effective information that this target cache line is corresponded in memory can be read when going out target cache line together, if it find that according to effective letter
Breath determines target cache line failure, then the target cache line can be replaced when writing data, and if finding the target and delaying
It deposits line not fail, then retains the target cache line when data are write.
As can be seen that using this mode when processor wants to replace certain target cache line, it is necessary to according to effective information pair
The validity of the target cache line is judged that the target cache line only to fail can be just replaced, and effective target cache
Line is then still present in cache, is not in due to before will when this measure causes processor subsequent access cache
The situation for the cache miss that effective cache lines are replaced away and occurred, so as to reduce cache miss rates, due to failure
The rejecting of cache lines can not only improve the utilization rate of cache and promote the computational efficiency of whole system, additionally it is possible to reduce
System is to the demand of cache capacity, so as to reduce the use power consumption of CPU, so as to reduce system build cost and use into
This.
In some embodiments, effective information includes virtual value, and different virtual values indicates that the difference of the cache lines is excellent
First grade so just can divide the priority of cache lines, in order to which CPU can be opened when replacing cache lines from low priority
Begin to replace, improve the utilization rate of cache, under this dividing mode, processor determines that the process of target cache line failure is variable
For processor judges virtual value, when being determined the priority of the target cache line less than default excellent according to virtual value
During first grade, it will determine that target cache line fails at this time.
In some embodiments, in the case of different priority are indicated using virtual value, similar, processor determines
The process of target cache line failure can be changed to, and processor judges virtual value, when determining that the target is delayed according to virtual value
When depositing the priority of line not less than default priority, it will determine that target cache line is effective at this time, equally, this mode can make
Obtaining the cache lines of high priority will not preferentially be replaced, and the stability of lifting system reduces cache miss rates.
In some embodiments, CPU is in addition to it can be read out the effective information of the cache lines in memory, also
It can be modified according to the application layer instruction that application layer is sent to the virtual value of memory, specific process can be processor
Application layer instruction is received, which is included by the information of the cache lines of application layer instruction instruction；And preprocessor just can
It is enough found according to the information and the virtual value of the cache lines to being instructed to is modified, the cache lines being instructed to are changed to reach
Priority purpose, enabling the priority of cache is configured by application layer so that application layer need
Cache lines will not be cleaned, and so as to not only improve the utilization rate of cache, reduce cache miss rates, lifting system well
Energy.
In some embodiments, processor can judge the information for the cache lines being instructed to, and can be taken in the information
Some information for the cache lines that band is instructed to can such as determine the cache lines being instructed to using terminating, at this time by the information
Processor will modify to virtual value so that the corresponding priority of amended virtual value less than default priority, from
And it can be preferentially replaced when replacing cache lines.
In some embodiments, the information of the cache lines being instructed to can also indicate whether the cache lines being instructed to are pass
Key cache lines, the data in the crucial cache lines i.e. cache lines are more important, can be used or even repeated more again in future
Secondary use needs by changing virtual value this kind of cache lines, its priority is adjusted to, higher than default priority, to make its nothing
Method is capped during cache lines are replaced, so as to reduce cache miss rates.
In some embodiments, processor can also periodically check the cache lines in cache, main
Check whether these cache lines have update, if find a certain cache lines have already passed through default time threshold have not occurred it is newer
Situation will modify to the virtual value of the cache lines so that the corresponding priority of amended virtual value is less than described pre-
If priority, so as to achieve the purpose that cache lines that are inapplicable to long-time but occupying cache memory space are cleared up, carry
Rise the utilization rate of cache.
In some embodiments, processor can also obtain cpu clock, which can include CPU weeks one or more
Phase then in subsequent examination cache lines, will carry out periodic test for the cycle according to the cpu clock of acquisition to cache lines.
This cycle sets one side more can timely check the update status of cache lines, on the other hand will not be to CPU's
Resource carries out excessive occupancy.
The embodiment of the present application second aspect also provides a kind of processor, cache and processing core, the cache
Inside include at least one cache lines, be additionally provided with to store the effective information of at least one cache lines in cache in processor
Memory, the memory, cache and processing core be connected by bus, and the processing core is for performing this Shen
The NVMe data read-write methods that please be provided in any embodiment of first aspect or first aspect.
The embodiment of the present application third aspect also provides a kind of computer storage media, is stored in the computer storage media
Program code such as the program code of application layer, when which is run by processor, performs first aspect or first aspect
The cache method for cleaning that any one realization method provides.The computer storage media includes but not limited to flash memory
(English：Flash memory), hard disk (English：Hard disk drive, referred to as：HDD) or solid state disk is (English：solid
State drive, referred to as：SSD).
The embodiment of the present application fourth aspect also provides a kind of computer storage media, which is arranged on meter
Inside the processor of calculation machine, for processor direct interaction, which is used to store high speed in processor
The effective information of cache lines in caching, processor is by reading the cache lines in computer storage media acquisition cache
Validity.The computer storage media can be instruction cache or data high-speed caching to be made of SRAM.
Description of the drawings
Fig. 1 is the application architecture figure of the cache method for cleaning of the embodiment of the present application；
Fig. 2 is one embodiment figure of the cache method for cleaning of the embodiment of the present application；
Fig. 3 is one embodiment figure of the processor of the embodiment of the present application.
Specific embodiment
The embodiment of the present application provides a kind of cache method for cleaning can be by the cache lines in cache
Validity is judged, preferentially the cache lines of failure are cleared up when clearing up cache content, are reduced to cache
The dependence of capacity, so as to not only reduce system build and use cost, but also improve system computational efficiency.
In order to which those skilled in the art is made to more fully understand application scheme, below in conjunction in the embodiment of the present application
The technical solution in the embodiment of the present application is clearly and completely described in attached drawing, it is clear that described embodiment is only
The embodiment of the application part, instead of all the embodiments.
It is described in detail individually below.
Term " first ", " second ", " the 3rd " " in the description and claims of this application and above-mentioned attached drawing
The (if present)s such as four " are the objects for distinguishing similar, without being used to describe specific order or precedence.It should manage
The data that solution so uses can exchange in the appropriate case, so that the embodiments described herein can be with except illustrating herein
Or the order beyond the content of description is implemented.
In view of CPU arithmetic speeds are more many soon than memory read-write rate, CPU can so taken a long time and waits pending datas
In the case of arriving or write the data to memory, the outlet of cache undoubtedly becomes the two unmatched buffering of rate.CPU's
Cache is usually larger, and CPU can't every time operate the content in entire cache in operation, therefore
Cache can be divided into multiple fixed size buffer lines, i.e. the minimum operation unit of CPU according to the least unit of CPU operation
For a cache lines；In general cache inside CPU is divided into three kinds, the first is instruction cache for storing instruction
Caching, second is cached for storing the data high-speed of data, and data high-speed caching can have for the difference of CPU architecture
Multistage, such as the desktop system haswell series CPU of Intel generally comprise three-level cache, i.e. L1cache, L2cache
With L3cache in multi-core CPU system, L1cache and L2cache are that each core is privately owned, and L3cache is then multiple cores
It is common.In addition, the third cache, translation look-aside buffer (TLB, Translation Lookaside Buffer) is then led
It is used to accelerate virtual address physical address translations.
It accesses main memory to CPU below to be introduced, CPU is during memory is accessed, due to depositing for foregoing cache
, be by cache dereference memory, and cache management system when managing cache with cache bar
The mode of mesh (cache entry), each cache entries include a cache lines, correspond to memory for tag cache line
Whether the mark and flag of address, the flag are invalid for tag cache line, if the cache lines are high for data
During speed caching, then the expression position is additionally operable to identify whether the cache lines are dirty, i.e., whether the cache lines are modified.CPU is every
It is secondary need access memory when, the cache lines of a whole can be traveled through, search the address of memory whether in some cache lines, such as not
It finds, i.e. cache miss, CPU can distribute a new cache entries at this time, then arrive the content synchronization in memory
In the cache lines, CPU reads corresponding content from the cache lines again.
Since the cache entries included in cache are limited, when cache entries reach the upper limit, need
There are suitable replacement policy, such as 1, recent minimum use (LRU, Least Recently Used) algorithm：To be minimum recently
The content used replaces out cache；2nd, (LFU, Least Frequently Used) algorithm is least commonly used：It will access
The minimum content of number replaces out cache；If the 3, all the elements are all buffered on the same day in cache, incite somebody to action
Maximum document replaces out cache, is otherwise replaced by lru algorithm；4th, first in first out (FIFO, First In First
Out) algorithm：First in, first out principle is followed, if current cache is filled, replaces that for entering cache earliest.
As can be seen that in these replacement policies, the universal law of cache is accessed only in accordance with CPU, and is not associated with working as
The application scenarios run in preceding system, although as some scenes be stored in cache in data can reuse or
It is not frequently used, but can use under certain condition, above-mentioned replacement policy just cannot take into account these applications well at this time
Scene causes the cache lines eliminated out i.e. will use the problem of arriving, increasing so as to cause cache miss.
In view of this, the embodiment of the present application proposes a kind of cache method for cleaning, will be in CPU individually in which
The memory with speed step with cache is set, which can be independently of the memory of cache setting,
Can be that a part of space is marked off from cache as the memory.The portion being stored in the memory in cache
Point or whole cache lines validity information, these effective informations can modifying with the information of connected applications layer.It please join
Fig. 1 and Fig. 2 are read, Fig. 1 is the application architecture figure of the cache method for cleaning of the embodiment of the present application, and Fig. 2 is the embodiment of the present application
Cache method for cleaning one embodiment figure, in Fig. 1 processing core, memory and the Applied layer interface of processor with
Bus connects, and is additionally provided with cache interface in the core, for accessing to the cache in processor, core is with depositing
Communication process between reservoir and Applied layer interface is carried out by bus.Cache method for cleaning is carried out below detailed
Illustrate, referring to Fig. 2, Fig. 2 is cache method for cleaning one embodiment figure of the embodiment of the present application, this method may include：
201st, processor determines the target cache line in cache.
Wherein, when being updated the data in due to cache miss or cache, it is necessary to be write to cache
Data when finding that the remaining cache line in cache is not enough to the data of reply write-in, will be washed in a pan by processor according to some
It eliminates strategy and determines target cache line to be replaced, these replacement policies can be by lru algorithm, LFU algorithms and FIFO algorithms
Etc. the target cache line determined, i.e. the cache method for cleaning of the embodiment of the present application can be compatible with current cache and wash in a pan
Eliminate strategy, naturally it is also possible to which sets itself different replacement policy determines target cache line.
202nd, processor reads the effective information that target cache line is corresponded in memory.
From figure 1 it appears that the core of processor can define mesh by bus access memory, processor
After marking cache lines, the effective information of the corresponding target cache line will be searched in the memory, which can refer to
It is effective or invalid to show the target cache line.
203rd, processor judges whether corresponding target cache line is effective according to effective information, if failure, performs step
204, perform step 205 if effectively.
Wherein, processor will perform step 204, work as place when determining that target cache line is effective according to effective information
Device is managed when determining that target cache line is invalid according to effective information, step 205 will be performed.
Optionally, which includes virtual value, and different virtual values indicates the different priorities of the cache lines, phase
When in the superseded rank of the cache lines in cache has been carried out further division according to importance.Processor is judging mesh
By judging the virtual value when whether mark cache lines fail.
Such as, determine that target cache line failure can be according to effective information：
Processor determines that the priority of the target cache line is less than default priority according to virtual value, it is determined that described
Target cache line fails.The default priority is preset, as long as less than the default priority, then it represents that the caching
The priority of line is low, belongs to what can be replaced, if not less than the default priority, then it represents that the cache lines belong to can not be by
It replaces, the corresponding virtual value of default priority can be set when system initialization, and processor also may be used
It is modified in system operation.In the setting of cache cleaning, it can be set as priority, as long as
With the presence of the cache lines of lower priority, then although the cache lines higher than the priority are still below default priority, but
It is that can wait until that the cache lines of the lower priority are replaced just to consider to be replaced the cache lines afterwards.Certainly, also may be used
As long as be set as less than default priority, and be targeted cache lines, although still having in cache lower excellent
The cache lines of first grade, but still the target cache line is cleared up.
For another example, determine that target cache line failure can be according to effective information：
Processor determines that the priority of the target cache line is not less than default priority according to virtual value, it is determined that institute
It is effective to state target cache line.
Further, since Applied layer interface is connected similarly to the bus in the embodiment of the present application, therefore application layer also can be right
Memory accesses, and specific access process can be：
Application layer instruction is received by processor, application layer instruction is included by the cache of application layer instruction instruction
In cache lines information, for example, the information includes the logical address of cache lines being instructed to and the cache lines to being instructed to
The modification information that will be carried out, which can be realized by a field or flag bit, can to the field or
The corresponding modification mode of person's flag bit is pre-defined, and after processor receives application layer instruction, can pass through logic
Corresponding cache lines in cache are found in address with the transformational relation of physical address, then pass through the mark of the expression modification information
Will position or field modify to the virtual value of the cache lines.It is carried out it is of course also possible to be instructed by processor to the application layer
Parsing obtains the information of cache lines to determine cache lines；After cache lines are determined, during processor can be instructed according to the application layer
The information of cache lines modifies to the virtual value for being instructed to cache lines to modify to priority, and different application layers refers to
Order can so that processor is different to the modification of virtual value.
For example, for application layer, after the application layer task terminates, data therein no longer need some cache lines
In the case of wanting, these cache lines should be arranged to minimum priority, i.e., be eliminated at first.Under this situation, processor according to
The virtual value for the cache lines being instructed to described in the information modification for the cache lines being instructed to can include：Processor is according to first
The information for the cache lines being instructed to determines that the cache lines use being instructed to terminates, and be instructed to described in preprocessor modification
The virtual value of cache lines, the corresponding priority of amended virtual value represent that the cache lines belong to less than default priority
The ranks that can be replaced.
Again for example, for a certain application of application layer, the cache lines in a certain cache become crucial slow
Line is deposited, i.e., during the key cache lines are the application execution, i.e., will use or need what is reused, it at this time can be right
The priority of the key cache lines is modified.Under this situation, processor is according to being changed the information for the cache lines being instructed to
The virtual value for the cache lines being instructed to can include：The information of the cache lines that processor is instructed to according to first determines described
The cache lines being instructed to are crucial cache lines, and the virtual value of the preprocessor modification crucial cache lines, amended effective
It is worth corresponding priority not less than default priority, represents that the cache lines belong to the ranks that can not be replaced, forbid CPU to it
It is covered.
In addition, it is optional, also the cache lines in cache can periodically be checked by processor, and to wherein
The virtual value of some cache lines is modified, for example, for the cache lines in cache, when can have processor according to CPU
Clock checks the update of the cache lines in the cache cache lines in cache are more than the default time if finding
Threshold value does not update, then can be default preferential less than described by the corresponding priority modification of the virtual value of the overtime cache lines
Grade, the meaning of this mode are that cache lines are operationally set higher than default preferential by a certain application program in order to prevent
Grade, i.e., it is not replaceable, but the problem of malfunction in its operational process, cause the cache lines with higher priority in high speed
It is resident, and can not be replaced in caching, thus can cause the waste of cache capacity, the volume for reducing system performs effect
Rate, therefore a time threshold can be preset, as long as newer cache lines are not just determined therefore yet more than the time threshold
Its priority is adjusted to be below default priority, in order to be able to be replaced in time by the cache lines that class is resident.
Wherein, cpu clock includes multiple cpu cycles (CPU Circle), during the minimum that cpu cycle, that is, CPU can be identified
Between unit, be usually hundred million/several seconds.Required time when CPU performs simplest instruction, such as read in register
Content.
204th, the target cache line is replaced.
When the definite target cache line is invalid, target cache line will be replaced, i.e., delayed newly-generated high speed
It deposits the corresponding cache lines of entry and replaces the target cache line.
205th, the target cache line is retained.
If it is determined that the target cache line is not invalid, but it is effective, then it will abandon replacing the target cache line.
And at this time due to be still required for replace cache in cache lines with the data to be write, a kind of mode be processor again
Memory is read, therefrom finds invalid cache lines, and the cache lines for needing to write are replaced into the invalid cache lines, is looked into certainly
The order for looking for invalid cache lines is still the principle first replaced according to low priority, that is, find the cache lines of lowest priority into
Row is replaced, if lazy weight, is found and is supplied compared with the higher leveled cache lines of lowest priority, until that can replace all write
The cache lines entered.
The method for cleaning of the cache of the embodiment of the present application is described above, below to the embodiment of the present application
Processor is introduced, referring to Fig. 3, Fig. 3 is one embodiment figure of the processor of the embodiment of the present application, which can
Including processing core 301, cache 302 and memory 303, Applied layer interface 304 is further included in certain processor, is handled
It is connected between core 301, cache 302, memory 303 and Applied layer interface 304 by bus, processing core 301 can
Think it is multiple, cache 302 can similar Intel processor set it is multistage, wherein, at least one is included in cache
Cache lines, memory are used to store the effective information of at least one cache lines in cache；
Wherein, processing core 301 is used to determine the target cache line in cache 302, is additionally operable to read the storage
The effective information of target cache line in device 303；The processing core 301 is additionally operable to work as determines the mesh according to the effective information
When marking cache lines failure, the target cache line is replaced；Or,
When it is described determine that the target cache line is effective according to the effective information when, retain the target cache line.
It should be noted that the memory 303 in the processor 3 can be arranged in cache 302, can also be used as
Another cache in processor 301, in addition, the scale removal process for the cache lines that processing core 301 performs is seen shown in Fig. 2
The scale removal process of cache lines in embodiment, details are not described herein again.
Optionally, effective information includes virtual value, and different virtual values indicates the different priorities of the cache lines, this
When, processing core 301 is specifically used for：When being determined the priority of the target cache line less than default excellent according to the virtual value
During first grade, the target cache line failure is determined.
It should be noted that the determination process is similar with the explanation that step 203 is directed in embodiment illustrated in fig. 2, herein not
It repeats again.
Optionally, processing core 301 is specifically used for：When the priority that target cache line is determined according to virtual value is not less than institute
When stating default priority, determine that the target cache line is effective.
It should be noted that the determination process is similar with the explanation that step 203 is directed in embodiment illustrated in fig. 2, herein not
It repeats again.
Optionally, the processing core 301 is additionally operable to：Application layer instruction is received, is included in the application layer instruction by institute
State the information of the cache lines of application layer instruction instruction；The cache lines being instructed to according to the modification of the information for the cache lines being instructed to
Virtual value.
It should be noted that the determination process is similar with the explanation that step 203 is directed in embodiment illustrated in fig. 2, herein not
It repeats again.
Optionally, processing core 301 also particularly useful for：Described referred to is determined according to the information of the cache lines being instructed to
The cache lines use shown terminates；The virtual value for the cache lines being instructed to described in modification, the corresponding priority of amended virtual value
Less than default priority.
It should be noted that the determination process is similar with the explanation that step 203 is directed in embodiment illustrated in fig. 2, herein not
It repeats again.
Optionally, processing core 301 also particularly useful for：Described referred to is determined according to the information of the cache lines being instructed to
The cache lines shown are crucial cache lines；Change the virtual value of the crucial cache lines, the corresponding priority of amended virtual value
Not less than default priority.
It should be noted that the determination process is similar with the explanation that step 203 is directed in embodiment illustrated in fig. 2, herein not
It repeats again.
Optionally, processing core 301 is additionally operable to：To the cache lines periodic test in the cache, when definite institute
When stating the cache lines in cache and not updated more than default time threshold, not newer cache lines is effective described in modification
Value, the corresponding priority of amended virtual value are less than the default priority.
It should be noted that the determination process is similar with the explanation that step 203 is directed in embodiment illustrated in fig. 2, herein not
It repeats again.
Optionally, processing core 301 also particularly useful for：Obtain central processor CPU clock；Using the cpu clock as week
Phase is to the cache lines periodic test in the cache.
It should be noted that the determination process is similar with the explanation that step 203 is directed in embodiment illustrated in fig. 2, herein not
It repeats again.
The memory being related in the embodiment of the present application and cache are illustrated below, the memory or height
Speed caching is made of SRAM, can be instruction cache or data high-speed caching, can be with when being cached as data high-speed
There are multiple ranks.
It is apparent to those skilled in the art that for convenience and simplicity of description, the system of foregoing description,
The specific work process of device and unit may be referred to the corresponding process in preceding method embodiment, and details are not described herein.
In several embodiments provided herein, it should be understood that disclosed system, apparatus and method can be with
It realizes by another way.For example, the apparatus embodiments described above are merely exemplary, for example, the unit
Division is only a kind of division of logic function, can there is other dividing mode, such as multiple units or component in actual implementation
It may be combined or can be integrated into another system or some features can be ignored or does not perform.It is another, it is shown or
The mutual coupling, direct-coupling or communication connection discussed can be the indirect coupling by some interfaces, device or unit
It closes or communicates to connect, can be electrical, machinery or other forms.
The unit illustrated as separating component may or may not be physically separate, be shown as unit
The component shown may or may not be physical location, you can be located at a place or can also be distributed to multiple
In network element.Some or all of unit therein can be selected to realize the mesh of this embodiment scheme according to the actual needs
's.
In addition, each functional unit in each embodiment of the application can be integrated in a processing unit, it can also
That unit is individually physically present, can also two or more units integrate in a unit.Above-mentioned integrated list
The form that hardware had both may be employed in member is realized, can also be realized in the form of SFU software functional unit.
If the integrated unit is realized in the form of SFU software functional unit and is independent production marketing or use
When, it can be stored in a computer read/write memory medium.Based on such understanding, the technical solution of the application is substantially
The part to contribute in other words to the prior art or all or part of the technical solution can be in the form of software products
It embodies, which is stored in a storage medium, is used including some instructions so that a computer
Equipment (can be personal computer, server or the network equipment etc.) performs the complete of each embodiment the method for the application
Portion or part steps.And foregoing storage medium includes：USB flash disk, mobile hard disk, read-only memory (ROM, Read-Only
Memory), random access memory (RAM, Random Access Memory), magnetic disc or CD etc. are various can store journey
The medium of sequence code.
The above, above example are only to illustrate the technical solution of the application, rather than its limitations；It still can be with
It modifies to the technical solution recorded in foregoing embodiments or which part technical characteristic is replaced；And these
Modification is replaced, and appropriate technical solution is not made to depart from the scope of each embodiment technical solution of the application.
Claims (16)
1. a kind of cache method for cleaning, the method is applied to processor, and cache is equipped in the processor, described
Include at least one cache lines in cache, which is characterized in that be additionally provided with to store in cache in the processor
The memory of the effective information of at least one cache lines, the described method includes：
Processor determines the target cache line in the cache；
The processor reads the effective information that the target cache line is corresponded in the memory；
When the processor determines that the target cache line fails according to the effective information, the target cache line is replaced；
Or,
When the processor determines that the target cache line is effective according to the effective information, retain the target cache line.
2. cache method for cleaning according to claim 1, which is characterized in that the effective information includes virtual value,
Different virtual values indicates the different priorities of the cache lines, and the processor determines the target according to the effective information
Cache lines failure includes：
When the processor determines that the priority of the target cache line is less than default priority according to the virtual value, really
The fixed target cache line failure.
3. cache method for cleaning according to claim 2, which is characterized in that the processor is according to effective letter
Breath determine the target cache line do not fail including：
When the processor determines that the priority of the target cache line is not less than the default priority according to virtual value,
Determine that the target cache line is effective.
4. the cache method for cleaning according to Claims 2 or 3, which is characterized in that the method further includes：
The processor receives application layer instruction, includes in the application layer instruction by the cache lines of application layer instruction instruction
Information；
The virtual value for the cache lines that the processor is instructed to according to being changed the information for the cache lines being instructed to.
5. cache method for cleaning according to claim 4, which is characterized in that the processor is slow according to what is be instructed to
Depositing the virtual value for the cache lines being instructed to described in the information modification of line includes：
The information for the cache lines that the processor is instructed to according to determines that the cache lines use being instructed to terminates；
The virtual value for the cache lines being instructed to described in processor modification, the corresponding priority of amended virtual value is less than pre-
If priority.
6. cache method for cleaning according to claim 4, which is characterized in that the processor is slow according to what is be instructed to
Depositing the virtual value for the cache lines being instructed to described in the information modification of line includes：
The information for the cache lines that the processor is instructed to according to determines that the cache lines being instructed to are crucial cache lines；
The virtual value of the processor modification crucial cache lines, the corresponding priority of amended virtual value is not less than default
Priority.
7. the cache method for cleaning according to any one of claim 2 to 6, which is characterized in that the method is also wrapped
It includes：
The processor to the cache lines periodic test in the cache,
When the cache lines that the processor is determined in the cache do not update more than default time threshold, described in modification
The virtual value of not newer cache lines, the corresponding priority of amended virtual value are less than the default priority.
8. cache method for cleaning according to claim 7, which is characterized in that the processor is to the cache
Interior cache lines periodic test includes：
The processor obtains central processor CPU clock；
The processor is the cycle to the cache lines periodic test in the cache using the cpu clock.
9. a kind of processor, the processor is interior to be equipped with cache and processing core, includes at least one in the cache
Cache lines, which is characterized in that be additionally provided with to store the effective of at least one cache lines in cache in the processor
The memory of information, the memory, cache and processing core are connected by bus；
The processing core for determining the target cache line in the cache, is additionally operable to read in the memory
The effective information of target cache line；
The processing core is additionally operable to, when determining that the target cache line fails according to the effective information, replace the target
Cache lines；Or,
When it is described determine that the target cache line is effective according to the effective information when, retain the target cache line.
10. processor according to claim 9, which is characterized in that the effective information includes virtual value, and different is effective
Value indicates the different priorities of the cache lines, and the processing core is specifically used for：
When the priority that the target cache line is determined according to the virtual value is less than default priority, the target is determined
Cache lines fail.
11. processor according to claim 10, which is characterized in that the processing core is specifically used for：
When the priority that the target cache line is determined according to virtual value is not less than the default priority, the mesh is determined
It is effective to mark cache lines.
12. the processor according to claim 10 or 11, which is characterized in that the processing core is additionally operable to：
Application layer instruction is received, is included in the application layer instruction by the information of the cache lines of application layer instruction instruction；
The virtual value for the cache lines being instructed to according to the modification of the information for the cache lines being instructed to.
13. processor according to claim 12, which is characterized in that the processing core also particularly useful for：
The cache lines use being instructed to according to determining the information of the cache lines being instructed to terminates；
The virtual value for the cache lines being instructed to described in modification, the corresponding priority of amended virtual value are preferential less than default
Grade.
14. processor according to claim 13, which is characterized in that the processing core also particularly useful for：
The cache lines being instructed to according to determining the information of the cache lines being instructed to are crucial cache lines；
Change the virtual value of the crucial cache lines, the corresponding priority of amended virtual value is not less than default priority.
15. the processor according to any one of claim 10 to 14, which is characterized in that the processing core is additionally operable to：
To the cache lines periodic test in the cache,
It is not newer slow described in modification when determining that the cache lines in the cache do not update more than default time threshold
Deposit the virtual value of line, the corresponding priority of amended virtual value is less than the default priority.
16. processor according to claim 15, which is characterized in that the processing core also particularly useful for：
Obtain central processor CPU clock；
It it is the cycle to the cache lines periodic test in the cache using the cpu clock.
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| CN201611067101.6A CN108108312A (en) | 2016-11-25 | 2016-11-25 | A kind of cache method for cleaning and processor |
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| CN201611067101.6A CN108108312A (en) | 2016-11-25 | 2016-11-25 | A kind of cache method for cleaning and processor |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113836053A (en) * | 2021-09-07 | 2021-12-24 | 上海砹芯科技有限公司 | Information acquisition method and device and electronic equipment |
| CN113849455A (en) * | 2021-09-28 | 2021-12-28 | 致真存储(北京)科技有限公司 | MCU based on hybrid memory and data caching method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102799538A (en) * | 2012-08-03 | 2012-11-28 | 中国人民解放军国防科学技术大学 | Cache replacement algorithm based on packet least recently used (LRU) algorithm |
| CN103076992A (en) * | 2012-12-27 | 2013-05-01 | 杭州华为数字技术有限公司 | Memory data buffering method and device |
| CN103383672A (en) * | 2012-05-01 | 2013-11-06 | 辉达公司 | Cache control to reduce transaction roll back |
| CN104166631A (en) * | 2014-09-11 | 2014-11-26 | 浪潮(北京)电子信息产业有限公司 | Replacement method for Cache row in LLC |
-
2016
- 2016-11-25 CN CN201611067101.6A patent/CN108108312A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103383672A (en) * | 2012-05-01 | 2013-11-06 | 辉达公司 | Cache control to reduce transaction roll back |
| CN102799538A (en) * | 2012-08-03 | 2012-11-28 | 中国人民解放军国防科学技术大学 | Cache replacement algorithm based on packet least recently used (LRU) algorithm |
| CN103076992A (en) * | 2012-12-27 | 2013-05-01 | 杭州华为数字技术有限公司 | Memory data buffering method and device |
| CN104166631A (en) * | 2014-09-11 | 2014-11-26 | 浪潮(北京)电子信息产业有限公司 | Replacement method for Cache row in LLC |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113836053A (en) * | 2021-09-07 | 2021-12-24 | 上海砹芯科技有限公司 | Information acquisition method and device and electronic equipment |
| CN113849455A (en) * | 2021-09-28 | 2021-12-28 | 致真存储(北京)科技有限公司 | MCU based on hybrid memory and data caching method |
| CN113849455B (en) * | 2021-09-28 | 2023-09-29 | 致真存储(北京)科技有限公司 | MCU based on hybrid memory and data caching method |
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