CN103076992A - Memory data buffering method and device - Google Patents

Abstract

The embodiment of the present invention discloses a method for memory data buffering, which includes opening a combined buffer area including at least a directory cache and a data cache in the memory of the memory agent HomeAgent, the cache lines in the directory cache and the cache lines in the data cache One-to-one correspondence of cache lines; receiving the operation address issued by the cache agent Cache Agent, judging whether the combined cache area is hit and valid according to the operation address, and if so, directly performing the corresponding operation on the combined cache area. By adopting the invention, the times of accessing the memory are reduced, and the delay of data acquisition is reduced.

Description

A memory data buffering method and device

technical field

The invention relates to the field of computers, in particular to a memory data buffering method and device.

Background technique

Modern advanced computer systems are composed of multiple CPUs. In order to increase the data access rate of the CPU and reduce the memory access delay, the Cache function will be implemented on the CPU. Its access speed is generally more than an order of magnitude faster than direct access to memory. Since each CPU will implement a cache, the memory at the same address will be cached in different CPU caches. If a CPU writes to this address, the cache in other CPUs must be invalidated. If there is dirty data in the cache must be written back to memory. In order to complete the above functions, modern multiprocessor computers implement the Cache Coherence Protocol (Cache Coherence Protocol) on the memory bus. For example, the QPI bus on the Intel CPU platform and the HT bus on the AMT CPU platform both implement the Cache Coherence Protocol. Common typical cache coherence protocols include Source Snoop and Home Snoop. In order to implement the cache coherence protocol, the cache agent (Cache Agent) function is generally implemented on the CPU side, and the memory agent (Home Agent) function is implemented on the memory side, and the two cooperate to implement the cache coherence protocol. Cache Agent mainly realizes the management of CPU Cache, and initiates the access function to memory, and responds to the listening request of other requests. The Home Agent mainly realizes the serialized access of multiple CAs to the same address and the parallelized access to different addresses.

The Home Snoop cache coherence protocol, all snooping requests are sent by the memory proxy. In order to reduce the number of listening and sending, a directory is generally stored in the memory, which is used to represent the state of each cache agent in the address. When the memory proxy receives a cache proxy request, it will read the memory data and the corresponding directory from the memory. If the memory directory indicates that no cache proxy owns the memory data, the memory proxy will directly send the data to the requester cache proxy; If it indicates that one or more caching agents own the memory data, the memory will send the caching agent that listens to the directory, wait for all the listening responses to be completed, and then send the request response to the requester caching agent.

The cache in the CPU generally has 4 states, Modefied (dirty), Exclusive (exclusive), Shared (shared), and Invalid (invalid). In order to meet the cache consistency protocol, the cache data of the M/E state of the same address can only exist in one cache agent, and the data CPU of these two states can perform direct read and write operations; for the S state of the same address, it can be in In the cache proxy of multiple CPUs, but the data can only be read by the CPU; for the invalid state, it means that there is no data at the address in the cache proxy. Different from the cache state in the caching agent, the state recorded in the memory directory does not distinguish between M/E, and these two types of states are unified into an exclusive state, and some designs do not even distinguish between the three states of M/E/S. Only records whether data is contained in a caching proxy.

The existing Home Snoop protocol, in order to speed up the reading of the memory directory, will add a cache at the memory agent (note: this cache is not the cache of the CPU cache agent). Read, and send the listener to the cache proxy as early as possible to reduce the delay of listening to the response. However, if the directory cache hits and the status of the indicated cache line is invalid, although it is not necessary to send the listening request to other cache agents, it must still read the data from the memory, and then send the data to the requester cache agent. This time the memory reading speed is often very slow, affecting the response time of the entire request cache.

Contents of the invention

The technical problem to be solved by the embodiments of the present invention is to provide a memory data buffering method and device. It can solve the problem that only directory information is optimized in the prior art. When the directory cache hits and the indicated data behavior is invalid, the data needs to be fetched from the memory to respond to the response time of the request.

In order to solve the above technical problems, the first aspect of the present invention provides a memory data buffering method, including:

In the memory of the memory agent Home Agent, open up a combined cache area comprising at least a directory cache and a data cache, and the cache lines in the directory cache correspond to the cache lines in the data cache;

Receive the operation address sent by the cache agent Cache Agent, judge whether the combined cache area is hit and valid according to the operation address, and if yes, directly perform the corresponding operation on the combined cache area.

In a first possible implementation manner, the combined buffer includes description information, and the description information includes: a comparison field, directory status information, data status information, and a valid flag bit;

The judging whether the combination cache is hit and valid according to the operation address includes:

Query whether there is a matching comparison field in the combined buffer according to the operation address, and if it exists, the combined buffer hits; and

Whether the hit cache line is valid is judged according to the valid flag bit of the hit cache line in the combined cache area.

In combination with the first aspect and the first possible implementation of the first aspect, in a second possible implementation, the operation address is a read operation address, and the directly performing the corresponding operation on the combined buffer includes :

Directly return the directory information and data information in the hit cache line to the cache proxy.

With reference to the second possible implementation of the first aspect, in a third possible implementation, the operation address is a write operation address, and the directly performing corresponding operations on the combined buffer area includes;

Write new data information and directory information in the hit cache line, update the directory status information and data status information in the combined buffer description information, and set the valid flag position as valid.

In combination with the third possible implementation of the first aspect, in the fourth possible implementation, the operation address sent by the cache agent Cache Agent is received, and when it is judged that the combined cache area misses according to the operation address, LRU is used The least recently used algorithm selects the cache line to be replaced in the combined cache area, and judges whether the directory information and data information in the cache line to be replaced need to be written according to the directory state information and data state information of the cache line to be replaced. back to memory;

Setting the effective flag position of the cache line to be replaced as invalid.

The second aspect of the present invention provides a memory data buffering method, comprising:

Open up directory cache and data cache in the memory of memory proxy Home Agent, the cache line in the directory cache and the cache line in the data cache are not one-to-one correspondence;

Receive the operation address sent by the cache agent Cache Agent, judge whether the directory cache and the data cache are hit and valid according to the operation address, if yes, directly perform corresponding operations on the directory cache and the data cache .

In a first possible implementation manner, the directory cache includes directory description information, and the directory description information includes a comparison field, directory status information, data information identification bits, data information identity identifiers, and directory effective identification bits; the data The cache includes data description information, and the data description information includes data status information and data valid identification bits;

The operation address sent by the receiving cache agent Cache Agent, judging whether the directory cache and the data cache hit and effectively include:

Query whether there is a matching comparison field in the directory cache according to the operation address, and if it exists, the directory cache hits;

Judging whether the hit cache line is valid according to the directory valid flag bit of the hit cache line in the directory cache, if yes, judging whether the data cache is hit according to the data information flag bit of the hit cache line ;

It is judged whether the hit cache line in the data cache is valid according to the data valid flag in the cache line of the hit data cache.

Combining the second aspect with the first possible implementation of the second aspect, in the second possible implementation,

The operation address is a read operation address, and the direct execution of corresponding operations on the directory cache and the data cache includes:

The directory information in the cache line of the hit directory cache and the data information in the cache line of the hit data cache are directly returned to the cache proxy.

With reference to the second possible implementation of the second aspect, in a third possible implementation, the operation address is a write operation address, and performing corresponding operations directly on the directory cache and the data cache includes :

Writing new directory information into the cache line of the hit directory cache and writing new data information into the cache line of the hit data cache.

In combination with the third possible implementation of the second aspect, the fourth possible implementation also includes:

When judging that the data cache misses according to the data information flag of the cache line of the hit data cache, an LRU least recently used algorithm is used to remove an idle cache line from the data cache.

A fourth aspect of the present invention provides a memory data buffering device, comprising:

The cache allocation module is used to open up a combined cache area including at least a directory cache and a data cache in the memory of the memory agent Home Agent, and the cache lines in the directory cache are in one-to-one correspondence with the cache lines in the data cache;

The operation execution module is used to receive the operation address sent by the cache agent Cache Agent, judge whether the combined cache area hits and is valid according to the operation address, and if yes, directly perform the corresponding operation on the combined cache area.

In a first possible implementation manner, the operation execution module includes:

A hit valid judging unit, configured to inquire whether there is a matching comparison field in the combined buffer according to the operation address, and if it exists, the combined buffer hits; and

Determine whether the hit cache line is valid according to the valid flag bit of the hit cache line in the combined cache area; wherein, the combined cache area includes description information, and the description information includes: a comparison field, directory status information, data Status information and valid flag bits.

In combination with the third aspect and the first possible implementation manner of the third aspect, in a second possible implementation manner, the operation execution module includes;

A read operation execution unit, configured to directly return the directory information and data information in the hit cache line to the cache proxy.

With reference to the second possible implementation of the third aspect, in three possible implementations, the operation execution module includes:

A write operation execution unit, configured to write new data information and directory information in the hit cache line, update the directory status information and data status information in the combined buffer description information, and set the valid flag position as valid .

In combination with the third possible implementation of the third aspect, the fourth possible implementation also includes:

The replacement module is used to receive the operation address sent by the cache agent Cache Agent, and when judging that the combined cache area misses according to the operation address, the LRU least recently used algorithm is used to select the cache line to be replaced in the combined cache area, according to The directory state information and data state information of the cache line to be replaced determine whether the directory information and data information in the cache line to be replaced need to be written back to the memory;

Setting the effective flag position of the cache line to be replaced as invalid.

A fourth aspect of the present invention provides a memory data buffering device, comprising:

The cache distribution module is used to open up a directory cache and a data cache in the memory of the memory agent Home Agent, and the cache lines in the directory cache are not in one-to-one correspondence with the cache lines in the data cache;

The operation execution module is used to receive the operation address sent by the cache agent Cache Agent, judge whether the directory cache and the data cache are hit and valid according to the operation address, and if so, directly perform the operation on the directory cache and the The data cache performs the corresponding operations.

In a first possible implementation manner, the operation execution module includes:

A hit valid judging unit, configured to inquire whether there is a matching comparison field in the directory cache according to the operation address, and if it exists, the directory cache hits;

Judging whether the hit cache line is valid according to the directory valid flag bit of the hit cache line in the directory cache, if yes, judging whether the data cache is hit according to the data information flag bit of the hit cache line ;

Judging whether the cache line in the hit data cache is valid according to the data valid flag in the cache line of the hit data cache; the directory cache includes directory description information, and the directory description information includes a comparison field, a directory State information, data information identification, data information identification and directory effective identification; the data cache includes data description information, and the data description information includes data status information and data effective identification.

With reference to the fourth aspect and the first possible implementation manner of the fourth aspect, in a second possible implementation manner, the operation execution unit includes;

The read operation execution unit is configured to directly return the directory information in the cache line of the hit directory cache and the data information in the cache line of the hit data cache to the caching agent.

With reference to the second possible implementation manner of the fourth aspect, in a third possible implementation manner, the operation execution unit includes:

A write operation executing unit, configured to write new directory information in the cache line of the hit directory cache and write new data information in the cache line of the hit data cache.

In combination with the third possible implementation of the fourth aspect, the fourth possible implementation also includes:

The replacement module is configured to use the LRU least recently used algorithm to remove an idle cache line from the data cache when judging that the data cache misses according to the data information flag of the hit cache line.

Implementing the embodiment of the present invention has the following beneficial effects:

Through the original directory cache solution, increase the corresponding data cache, reduce the number of memory accesses, and reduce the delay of data acquisition.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a first schematic flow chart of a memory data buffering method according to an embodiment of the present invention;

FIG. 2 is a second schematic flowchart of a memory data buffering method according to an embodiment of the present invention;

Fig. 3 is a third schematic flowchart of a memory data buffering method according to an embodiment of the present invention;

Fig. 4 is a fourth schematic flow chart of a memory data buffering method according to an embodiment of the present invention;

Fig. 5 is a schematic flow chart of the replacement operation in Fig. 4;

FIG. 6 is a schematic diagram of a first structure of a memory data buffering device according to an embodiment of the present invention;

FIG. 7 is a second structural schematic diagram of a memory data buffering device according to an embodiment of the present invention;

Fig. 8 is a schematic structural diagram of the operation execution module in Fig. 7;

9 is a schematic diagram of a third structure of a memory data buffering device according to an embodiment of the present invention;

10 is a schematic diagram of a fourth structure of a memory data buffering device according to an embodiment of the present invention;

11 is a schematic diagram of a fifth structure of a memory data buffering device according to an embodiment of the present invention;

Fig. 12 is a schematic structural diagram of the operation execution module in Fig. 11;

FIG. 13 is a schematic diagram of a sixth structure of a memory data buffering device according to an embodiment of the present invention.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

Referring to Fig. 1, it is a first schematic flow chart of a memory data buffering method according to an embodiment of the present invention, and the flow includes:

Step 101, open up a combined cache area including at least a directory cache and a data cache in the memory of the memory agent.

Specifically, the directory cache is a copy of the directory information memory line loaded into the memory agent in the memory. The state information of the memory line and the location information in the cache are recorded in the directory information. The state information refers to invalid, exclusive, dirty And shared state, the location information refers to which CPU cache the memory row is loaded into. Each memory row data corresponds to a directory information. According to the principle of locality, only part of the directory information that is frequently accessed is buffered in the directory cache. , the data cache line in the data cache is in one-to-one correspondence with the directory cache line in the directory cache, that is, the state information and location information of the data cache line in the corresponding data cache are recorded in the directory cache line, due to this one-to-one correspondence The relationship between the directory cache line and the data cache line can be associated into a combined cache line.

Step 102, receiving the read operation address sent by the caching proxy.

Specifically, the cache proxy sends a read operation request, and the read operation request corresponds to a read operation address.

Step 103 , whether the combination buffer is hit.

Specifically, according to the address of the read operation, it is judged whether the combination cache area is hit. The combination cache area includes description information, and the description information includes: comparison field, directory status information, data status information and valid flag bits, as shown in the following table The cache line structure of the cache area is:

Table 1

The step of judging whether the combination buffer is hit and valid according to the operation address specifically includes:

Query whether there is a matching comparison field TAG in the combined buffer according to the operation address, and if it exists, the combined buffer hits.

Step 104, whether the cache line in the combined buffer area is valid.

Specifically, it is judged whether it is valid according to the value of the VALID bit in the hit cache line, and when the VALID bit is 1, it indicates that the cache line is valid.

Step 105, initiate a read operation of the memory corresponding to the read operation address.

Specifically, when step 103 and step 104 judge no, execute step 105 to read the directory information and data information in the memory row corresponding to the operation address through the memory channel.

Step 106, write the directory information and data information obtained from the internal memory into the combined buffer area.

Specifically, a free cache line is queried from the combined cache area. If it exists, the directory information and data information obtained from the memory are written into the cache line. If there is no free cache line in the combined cache area, LRU is used. Algorithms such as least recently used or FIFO first-in-first-out eliminate a cache line to facilitate the writing of directory information and data information.

Step 107: Directly return the directory information and data information in the hit cache line to the cache proxy.

Specifically, when it is determined according to the address of the read operation that the combined cache area hits and the hit cache line is valid, the directory information and data information in the hit cache line are directly returned to the cache proxy.

In implementing the embodiment of the present invention, the original directory cache solution is used to increase the corresponding data cache, reduce the number of memory accesses, and reduce the delay of data acquisition.

Referring to FIG. 2 and FIG. 3, it is a schematic diagram of a second process flow of a memory data buffering method according to an embodiment of the present invention. The process includes;

Step 201, open up a combined cache area including at least a directory cache and a data cache in the memory of the memory agent.

Specifically, the directory cache is a copy of the directory information memory line loaded into the CPU cache in the memory. The state information of the memory line and the location information in the cache are recorded in the directory information. The state information refers to invalid, exclusive, dirty And shared state, the location information refers to which CPU cache the memory row is loaded into. Each memory row data corresponds to a directory information. According to the principle of locality, only part of the directory information that is frequently accessed is buffered in the directory cache. , the data cache line in the data cache is in one-to-one correspondence with the directory cache line in the directory cache, that is, the state information and location information of the data cache line in the corresponding data cache are recorded in the directory cache line, due to this one-to-one correspondence The relationship between the directory cache line and the data cache line can be associated into a combined cache line.

Step 202, receiving the write operation address sent by the caching agent.

Specifically, the cache proxy sends a write operation request, and the write operation request corresponds to a write operation address.

Step 203 , whether the combination buffer is hit.

Specifically, according to the address of the write operation, it is judged whether there is a matching comparison field in the cache line of the combined buffer area. If it exists, the combined buffer area hits, and step 204 is performed; if not, the combined buffer area misses, and step 205 is performed. According to the example in Table 1, it is judged according to the address of the write operation whether there is a matching TAG in the combined buffer, and if so, the combined buffer hits.

Step 204, whether the cache lines in the combined cache area are valid.

Specifically, judge whether it is valid according to the validity flag of the hit cache line, if valid, perform step 206 , and if invalid, perform step 205 . As shown in the example in Table 1, VALID is a valid identification bit. Setting VALID to 1 indicates that the hit cache line is valid, and setting VALID to 0 indicates that the hit cache line is invalid.

In step 205, a free cache line is found in the combined cache area or an idle cache line is found by using a preset algorithm to perform a replacement operation.

Specifically, when the determination in step 203 and/or step 204 is negative, that is, when the combined cache misses and/or the hit cache line is invalid, a replacement operation is performed. Specifically, the replacement operation is to query whether there are free cache lines in the combined buffer area, and if so, select one of the free cache lines to perform the replacement operation; if the cache lines in the combined buffer area are full and there are no free cache lines, then The LRU or FIFO algorithm is used to select an idle cache line to perform the replacement operation, and the replacement algorithm is not limited in the present invention. See Figure 3 for the specific replacement process, including:

Step 2051, the memory agent initiates a replacement operation of the cache line in the combined buffer area.

Specifically, when there is no free cache line in the combined cache area, a replacement operation is initiated.

Step 2052: Select a cache line using the least recently used algorithm.

Specifically, the least recently used LRU algorithm conforms to the principle of time locality and can effectively improve the cache hit rate.

Step 2053, judging whether it needs to be written back to the memory according to the directory status information and the data status information.

Specifically, before performing the replacement operation, it is judged whether the directory state information and data state information of the selected cache line are dirty. If it is dirty, it means that the data stored in the cache line is the latest and needs to be written back to the memory. As shown in the example in Table 1, DIR_DIRTY is set to 1 to indicate that the directory information in the cache line is dirty, and DATA_DIRTY is set to 1 to indicate that the data information in the cache line is dirty. Of course, other identification methods can also be used, which are not limited by the present invention.

Step 2054, write the directory information and data information in the cache line to be replaced back to the memory.

Specifically, when step 2053 judges yes, this step is executed to ensure that the data in the memory is the latest.

Step 2055, the effective identification position of the cache line to be replaced is invalid.

Specifically, the directory information and data information in the replaced cache line are rewritten, and are not valid data. In order to avoid reading wrong data, the valid identifier of the cache line to be replaced is set as invalid.

Step 206: Write new data information and directory information in the hit cache line, update the directory status information and data status information in the combined cache description information, and set the valid flag position as valid. For example, as shown in Table 1, set DIR_DIRTY, VALID, and DATA_DIRTY to 1.

In implementing the embodiment of the present invention, the original directory cache solution is used to increase the corresponding data cache, reduce the number of memory accesses, and reduce the delay of data acquisition.

Referring to FIG. 3 , it is a schematic diagram of a third process flow of a memory data buffering method of the present invention, which process includes:

Step 301, re-opening the directory cache and data cache in the memory of the memory agent.

Specifically, the directory cache is a copy of part of the directory information loaded into the memory agent in the memory. For the copy of some data information, according to the principle of program locality, the loaded directory cache and data cache are frequently accessed data. Here, there is not a one-to-one correspondence relationship between the cache lines of the directory cache and the cache lines of the data cache, and the cache lines of the directory cache are associated with the cache lines in the data cache through the data information identification bit and the data information identifier. The cache line structure of the directory cache is as follows:

Table 2

The cache line structure of the data cache is as follows:

table 3

The cache line in the directory cache uses the data information identification bit DATA_VALID to indicate whether the data cache is hit, and at the same time, queries the cache line of the data cache through the data information identifier DATA_ID. , it can be seen from the above table that when the data cache misses, that is, when the cache line storing the data information does not exist in the data cache, the data information ID DATA_ID will not be allocated.

Step 302, receiving the read operation address sent by the caching agent.

Specifically, the cache proxy sends a read operation request, and the read operation request corresponds to a read operation address.

Step 303, whether the directory cache is hit and valid.

Specifically, query whether there is a matching comparison field in the directory cache according to the operation address, such as whether there is a TAG matching the operation address in Table 2, if it exists, the directory cache hits, find the cache line in the directory cache that hits, and query The valid identification bit VALID in the cache line is used to determine whether the cache line is valid, assuming that VALID is set to 1 to be valid, and VALID is set to 0 to be invalid, then when the query finds that VALID is 1, the corresponding cache behavior is valid, and step 304 is executed. When the VALID is found to be 0, the corresponding cache behavior is invalid, and step 305 is executed.

Step 305, initiate a read operation of the memory corresponding to the operation address.

Specifically, the directory cache miss indicates that the cache line required by the caching proxy does not exist in the directory cache, and needs to be read from the memory through a memory channel.

Step 306, write the directory information and data information acquired from the internal memory into the internal proxy storage.

Specifically, the directory information is written into the directory cache, and the data information is written into the data cache.

Step 304, whether the data cache is valid.

Specifically, when step 303 judges yes, read the data information flag DATA_VALID of the cache line in the hit directory cache, and determine whether the data information exists in the data cache by the value of DATA_VALID, assuming that DATA_VALID is set to 1 to indicate that it exists in the data cache In , it is set to 0 to indicate that there is no data cache. When it is detected that DATA_VALID is set to 1, the corresponding cache line is found in the data cache through the data information identifier DATA_ID of the directory cache.

Step 307, directly returning the directory information and data information in the hit cache line to the cache proxy.

Specifically, when it is determined by the value of the valid data identification bit VALID in the data cache that the cache line of the data cache is also valid, the directory information and data information are directly returned to improve the access speed.

In implementing the embodiment of the present invention, the original directory cache solution is used to increase the corresponding data cache, reduce the number of memory accesses, and reduce the delay of data acquisition.

Referring to FIG. 5, it is a schematic diagram of a fourth process flow of a memory data buffering method of the present invention, which process includes:

Step 401, create a directory cache and a data cache in the storage of the memory agent.

Specifically, the directory cache is a copy of part of the directory information loaded into the memory agent in the memory. For the copy of some data information, according to the principle of program locality, the loaded directory cache and data cache are frequently accessed data. Here, there is not a one-to-one correspondence relationship between the cache lines of the directory cache and the cache lines of the data cache, and the cache lines of the directory cache are associated with the cache lines in the data cache through the data information identification bit and the data information identifier.

Step 402, receiving the write operation address sent by the caching agent.

Specifically, the cache proxy sends a write operation request, and the read operation request corresponds to a write operation address.

Step 403, the directory cache is hit and valid.

Specifically, it is determined that the directory cache hits and is valid according to the comparison field of the directory cache and the valid identifier bit of the directory, and the method is described above.

Step 404 , updating the cache line of the hit directory cache.

Step 405, whether the cache line in the data cache needs to be updated.

Specifically, if the write operation request involves the update of the cache lines of the data cache, then continue to perform step 406 , and if it does not involve the update of the cache lines of the data cache, then perform step 409 .

Step 406, whether the corresponding cache line is in the data cache.

Determine whether the cache line of the corresponding data cache exists in the data cache according to the data information identification bit of the directory cache. If yes, perform step 408 ; if not, perform step 409 .

Step 408, write the corresponding cache line according to the data information identifier.

Specifically, the cache line in the data cache that needs to be written is queried according to the data information identifier in the directory cache, and the updated data is written into the cache line.

In step 407, an idle cache line is found in the data cache or an idle cache line is found by using a preset algorithm to perform a replacement operation.

Specifically, the replacement operation is described above, and will not be described here. Before replacing the directory cache or data cache, first check the directory status information and data status information, that is, whether the DIR_DIRTY and DATA_DIRTY in Table 2 are dirty, and if they are dirty, write back to the memory operation, and then perform the replacement operation .

Step 409, updating data status information and directory status information.

Specifically, the cache lines in the directory cache and the data cache are modified, and the data status information and the directory status information are set as dirty.

In implementing the embodiment of the present invention, the original directory cache solution is used to increase the corresponding data cache, reduce the number of memory accesses, and reduce the delay of data acquisition.

Referring to Fig. 6, it is a schematic diagram of the first structure of a memory data buffering device of the present invention, which device includes:

The cache allocation module 11 is configured to open up a combined cache area including at least a directory cache and a data cache in the memory of the memory agent Home Agent, and the cache lines in the directory cache correspond to the cache lines in the data cache one by one.

Specifically, the directory cache is a copy of the directory information memory line loaded into the memory agent in the memory. The state information of the memory line and the location information in the cache are recorded in the directory information. The state information refers to invalid, exclusive, dirty And shared state, the location information refers to which CPU cache the memory row is loaded into. Each memory row data corresponds to a directory information. According to the principle of locality, only part of the directory information that is frequently accessed is buffered in the directory cache. , the cache allocation module 11 corresponds the data cache line in the data cache to the directory cache line in the directory cache one by one, that is, the state information and location information of the data cache line in the corresponding data cache are recorded in the directory cache line, because In this one-to-one correspondence, the directory cache line and the data cache line can be associated into a combined cache line.

The operation execution module 12 is used to receive the operation address sent by the cache agent Cache Agent, judge whether the combined cache area hits and is valid according to the operation address, and if yes, directly perform the corresponding operation on the combined cache area.

In implementing the embodiment of the present invention, the original directory cache solution is used to increase the corresponding data cache, reduce the number of memory accesses, and reduce the delay of data acquisition.

Further, referring to FIG. 7 and FIG. 8 , it is a second structural schematic diagram of a memory data buffering device of the present invention, in addition to the cache allocation module 11 and the operation execution module 12, it also includes:

Replacement module 13, replacement module, is used for receiving the operation address that cache proxy Cache Agent sends, when judging described combination cache area misses according to described operation address, adopt LRU least recently used algorithm to select the to-be-replaced in described combination cache area The cache line, judging whether the directory information and data information in the cache line to be replaced needs to be written back to the memory according to the directory state information and data state information of the cache line to be replaced; the effective flag position of the cache line to be replaced is invalid.

Wherein, the operation execution module 12 includes:

A hit valid judging unit 121, configured to query whether there is a matching comparison field in the combined buffer according to the operation address, and if so, the combined buffer hits; and

Determine whether the hit cache line is valid according to the valid flag bit of the hit cache line in the combined cache area; wherein, the combined cache area includes description information, and the description information includes: a comparison field, directory status information, data Status information and valid flag bits.

The operation execution module 12 also includes;

The read operation execution unit 122 is configured to directly return the directory information and data information in the hit cache line to the cache proxy.

The operation execution module also includes:

The write operation execution unit 123 is configured to write new data information and directory information in the hit cache line, update the directory status information and data status information in the combined buffer description information, and set the effective flag position as efficient.

In implementing the embodiment of the present invention, the original directory cache solution is used to increase the corresponding data cache, reduce the number of memory accesses, and reduce the delay of data acquisition.

Referring to FIG. 9 , it is a schematic diagram of the third structure of a memory data buffering device of the present invention, including a processor 61 and a memory 62. The number of processors 61 in the device 1 can be one or more. FIG. 9 uses one processor as an example. In some embodiments of the present invention, the processor 61 and the memory 62 may be connected through a bus or in other ways, and bus connection is taken as an example in FIG. 10 .

Wherein, a set of program codes are stored in the memory 62, and the processor 61 is used to call the program codes stored in the memory 62 to perform the following operations:

In the memory of the memory agent Home Agent, open up a combined cache area comprising at least a directory cache and a data cache, and the cache lines in the directory cache correspond to the cache lines in the data cache;

Receive the operation address sent by the cache agent Cache Agent, judge whether the combined cache area is hit and valid according to the operation address, and if yes, directly perform the corresponding operation on the combined cache area.

In some embodiments of the present invention, the processor is specifically configured to perform:

Query whether there is a matching comparison field in the combined buffer according to the operation address, and if it exists, the combined buffer hits; and

Determine whether the hit cache line is valid according to the valid flag bit of the hit cache line in the combined cache area; wherein, the combined cache area includes description information, and the description information includes: a comparison field, directory status information, data Status information and valid flag bits.

Further, the processor 61 is also specifically configured to execute:

Directly return the directory information and data information in the hit cache line to the cache proxy.

Further, the processor 61 is specifically configured to execute:

Write new data information and directory information in the hit cache line, update the directory status information and data status information in the combined buffer description information, and set the valid flag position as valid.

Further, the processor 61 is also used to execute:

Receive the operating address sent by the cache agent Cache Agent, and when judging that the combined buffer area misses according to the operating address, adopt the LRU least recently used algorithm to select the cache line to be replaced in the combined buffer area, according to the cache line to be replaced The directory status information and data status information of the line determine whether the directory information and data information in the cache line to be replaced need to be written back to the memory;

Setting the effective flag position of the cache line to be replaced as invalid.

In implementing the embodiment of the present invention, the original directory cache solution is used to increase the corresponding data cache, reduce the number of memory accesses, and reduce the delay of data acquisition.

Referring to FIG. 10 , it is a schematic diagram of the fourth structure of a memory data buffering device of the present invention, including:

The cache allocation module 21 is configured to open up a directory cache and a data cache in the memory of the memory agent Home Agent, and the cache lines in the directory cache are not in one-to-one correspondence with the cache lines in the data cache.

The operation execution module 22 is used to receive the operation address sent by the cache agent Cache Agent, judge whether the directory cache and the data cache are hit and valid according to the operation address, and if so, directly perform the operation on the directory cache and the data cache The above data cache performs the corresponding operation.

In implementing the embodiment of the present invention, the original directory cache solution is used to increase the corresponding data cache, reduce the number of memory accesses, and reduce the delay of data acquisition.

Further, referring to FIGS. 11-12 , it is a schematic diagram of the fifth structure of a memory data buffering device of the present invention, in addition to the cache allocation module 21 and the operation execution module 22, it also includes:

The replacement module 23 is configured to use the LRU least recently used algorithm to remove an idle cache line from the data cache when judging that the data cache misses according to the data information flag of the hit cache line.

Wherein, the operation execution module 22 includes:

A hit valid judging unit 221, configured to inquire whether there is a matching comparison field in the directory cache according to the operation address, and if it exists, the directory cache hits;

Judging whether the hit cache line is valid according to the directory valid flag bit of the hit cache line in the directory cache, if yes, judging whether the data cache is hit according to the data information flag bit of the hit cache line ;

Judging whether the cache line in the hit data cache is valid according to the data valid flag in the cache line of the hit data cache; the directory cache includes directory description information, and the directory description information includes a comparison field, a directory State information, data information identification, data information identification and directory effective identification; the data cache includes data description information, and the data description information includes data status information and data effective identification.

The operation execution unit 22 includes;

The read operation execution unit 222 is configured to directly return the directory information in the cache line of the hit directory cache and the data information in the cache line of the hit data cache to the caching agent.

The operation execution unit 22 includes:

The write operation execution unit 223 is configured to write new directory information in the cache line of the hit directory cache and write new data information in the cache line of the hit data cache.

In implementing the embodiment of the present invention, the original directory cache solution is used to increase the corresponding data cache, reduce the number of memory accesses, and reduce the delay of data acquisition.

Referring to FIG. 13 , it is a sixth structural diagram of a memory data buffering method of the present invention, including a processor 71 and a memory 72. The number of processors 71 in the device 1 can be one or more. FIG. 13 uses one processor as an example. In some embodiments of the present invention, the processor 71 and the memory 72 may be connected through a bus or in other ways, and bus connection is taken as an example in FIG. 13 .

Wherein, a set of program codes are stored in the memory 72, and the processor 71 is used to call the program codes stored in the memory 72 to perform the following operations:

Open up directory cache and data cache in the memory of memory proxy Home Agent, the cache line in the directory cache and the cache line in the data cache are not one-to-one correspondence;

Receive the operation address sent by the cache agent Cache Agent, judge whether the directory cache and the data cache are hit and valid according to the operation address, if yes, directly perform corresponding operations on the directory cache and the data cache .

Further, the processor 71 is specifically configured to execute:

Query whether there is a matching comparison field in the directory cache according to the operation address, and if it exists, the directory cache hits;

Judging whether the hit cache line is valid according to the directory valid flag bit of the hit cache line in the directory cache, if yes, judging whether the data cache is hit according to the data information flag bit of the hit cache line ;

Judging whether the cache line in the hit data cache is valid according to the data valid flag in the cache line of the hit data cache; the directory cache includes directory description information, and the directory description information includes a comparison field, a directory State information, data information identification, data information identification and directory effective identification; the data cache includes data description information, and the data description information includes data status information and data effective identification.

Further, the processor 71 is specifically configured to execute:

The directory information in the cache line of the hit directory cache and the data information in the cache line of the hit data cache are directly returned to the cache proxy.

Further, the processor 71 is specifically configured to execute:

Writing new directory information into the cache line of the hit directory cache and writing new data information into the cache line of the hit data cache.

In some embodiments of the present invention, the processor 71 is also used to execute:

When judging that the data cache misses according to the data information flag of the cache line of the hit data cache, an LRU least recently used algorithm is used to remove an idle cache line from the data cache.

In implementing the embodiment of the present invention, the original directory cache solution is used to increase the corresponding data cache, reduce the number of memory accesses, and reduce the delay of data acquisition.

Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be implemented through computer programs to instruct related hardware, and the programs can be stored in a computer-readable storage medium. During execution, it may include the processes of the embodiments of the above-mentioned methods. Wherein, the storage medium may be a magnetic disk, an optical disk, a read-only memory (Read-Only Memory, ROM) or a random access memory (Random Access Memory, RAM), etc.

What is disclosed above is only a preferred embodiment of the present invention, and of course it cannot limit the scope of rights of the present invention. Those of ordinary skill in the art can understand all or part of the process for realizing the above embodiments, and according to the rights of the present invention The equivalent changes required still belong to the scope covered by the invention.

Claims (20)

1. A memory data buffer method, characterized in that, comprising: In the memory of the memory agent Home Agent, open up a combined cache area comprising at least a directory cache and a data cache, and the cache lines in the directory cache correspond to the cache lines in the data cache; Receive the operation address sent by the cache agent Cache Agent, judge whether the combined cache area is hit and valid according to the operation address, and if yes, directly perform the corresponding operation on the combined cache area. 2. The method according to claim 1, wherein the combined buffer area includes description information, and the description information includes: a comparison field, directory status information, data status information and valid flag bits; The judging whether the combination cache is hit and valid according to the operation address includes: Query whether there is a matching comparison field in the combined buffer according to the operation address, and if it exists, the combined buffer hits; and Whether the hit cache line is valid is judged according to the valid flag bit of the hit cache line in the combined cache area. 3. The method according to claim 1 or 2, wherein the operation address is a read operation address, and performing corresponding operations directly on the combined buffer area comprises: Directly return the directory information and data information in the hit cache line to the cache proxy. 4. The method according to claim 3, wherein the operation address is a write operation address, and performing corresponding operations directly on the combined buffer area comprises; Write new data information and directory information in the hit cache line, update the directory status information and data status information in the combined buffer description information, and set the valid flag position as valid. 5. The method of claim 4, further comprising: Receive the operating address sent by the cache agent Cache Agent, and when judging that the combined buffer area misses according to the operating address, adopt the LRU least recently used algorithm to select the cache line to be replaced in the combined buffer area, according to the cache line to be replaced The directory status information and data status information of the line determine whether the directory information and data information in the cache line to be replaced need to be written back to the memory; Setting the effective flag position of the cache line to be replaced as invalid. 6. A memory data buffering method, characterized in that, comprising; Open up directory cache and data cache in the memory of memory proxy Home Agent, the cache line in the directory cache and the cache line in the data cache are not one-to-one correspondence; Receive the operation address sent by the cache agent Cache Agent, judge whether the directory cache and the data cache are hit and valid according to the operation address, if yes, directly perform corresponding operations on the directory cache and the data cache . 7. The method according to claim 6, wherein the directory cache includes directory description information, and the directory description information includes comparison fields, directory status information, data information identification bits, data information identity identifiers, and effective directory identifiers bit; the data cache includes data description information, and the data description information includes data status information and data valid identification bits; The operation address sent by the receiving cache agent Cache Agent, judging whether the directory cache and the data cache hit and effectively include: Query whether there is a matching comparison field in the directory cache according to the operation address, and if it exists, the directory cache hits; Judging whether the hit cache line is valid according to the directory valid flag bit of the hit cache line in the directory cache, if yes, judging whether the data cache is hit according to the data information flag bit of the hit cache line ; It is judged whether the hit cache line in the data cache is valid according to the data valid flag in the cache line of the hit data cache. 8. The method according to claim 6 or 7, wherein the operation address is a read operation address, and performing corresponding operations directly on the directory cache and the data cache comprises: The directory information in the cache line of the hit directory cache and the data information in the cache line of the hit data cache are directly returned to the cache proxy. 9. The method according to claim 8, wherein the operation address is a write operation address, and performing corresponding operations directly on the directory cache and the data cache comprises: Writing new directory information into the cache line of the hit directory cache and writing new data information into the cache line of the hit data cache. 10. The method of claim 8, further comprising: When judging that the data cache misses according to the data information flag of the cache line of the hit data cache, an LRU least recently used algorithm is used to remove an idle cache line from the data cache. 11. A memory data buffering device, characterized in that, comprising: The cache allocation module is used to open up a combined cache area including at least a directory cache and a data cache in the memory of the memory agent Home Agent, and the cache lines in the directory cache are in one-to-one correspondence with the cache lines in the data cache; The operation execution module is used to receive the operation address sent by the cache agent Cache Agent, judge whether the combined cache area hits and is valid according to the operation address, and if yes, directly perform the corresponding operation on the combined cache area. 12. The device according to claim 11, wherein the operation execution module comprises: A hit valid judging unit, configured to inquire whether there is a matching comparison field in the combined buffer according to the operation address, and if it exists, the combined buffer hits; and Determine whether the hit cache line is valid according to the valid flag bit of the hit cache line in the combined cache area; wherein, the combined cache area includes description information, and the description information includes: a comparison field, directory status information, data Status information and valid flag bits. 13. The device according to claim 11 or 12, wherein the operation execution module comprises; A read operation execution unit, configured to directly return the directory information and data information in the hit cache line to the cache proxy. 14. The device according to claim 13, wherein the operation execution module comprises: A write operation execution unit, configured to write new data information and directory information in the hit cache line, update the directory status information and data status information in the combined buffer description information, and set the valid flag position as valid . 15. The apparatus of claim 14, further comprising: The replacement module is used to receive the operation address sent by the cache agent Cache Agent, and when judging that the combined cache area misses according to the operation address, the LRU least recently used algorithm is used to select the cache line to be replaced in the combined cache area, according to The directory state information and data state information of the cache line to be replaced determine whether the directory information and data information in the cache line to be replaced need to be written back to the memory; Setting the effective flag position of the cache line to be replaced as invalid. 16. A memory data buffering device, characterized in that, comprising: The cache distribution module is used to open up a directory cache and a data cache in the memory of the memory agent Home Agent, and the cache lines in the directory cache are not in one-to-one correspondence with the cache lines in the data cache; The operation execution module is used to receive the operation address sent by the cache agent Cache Agent, judge whether the directory cache and the data cache are hit and valid according to the operation address, and if so, directly perform the operation on the directory cache and the The data cache performs the corresponding operations. 17. The device according to claim 16, wherein the operation execution module comprises: A hit valid judging unit, configured to inquire whether there is a matching comparison field in the directory cache according to the operation address, and if it exists, the directory cache hits; Judging whether the hit cache line is valid according to the directory valid flag bit of the hit cache line in the directory cache, if yes, judging whether the data cache hits according to the data information flag bit of the hit cache line ; Judging whether the cache line in the hit data cache is valid according to the data valid flag in the cache line of the hit data cache; the directory cache includes directory description information, and the directory description information includes a comparison field, a directory State information, data information identification, data information identification and directory effective identification; the data cache includes data description information, and the data description information includes data status information and data effective identification. 18. The device according to claim 16 or 17, wherein the operation execution unit comprises; The read operation execution unit is configured to directly return the directory information in the cache line of the hit directory cache and the data information in the cache line of the hit data cache to the caching agent. 19. The device according to claim 18, wherein the operation executing unit comprises: A write operation executing unit, configured to write new directory information in the cache line of the hit directory cache and write new data information in the cache line of the hit data cache. 20. The apparatus of claim 19, further comprising: The replacement module is configured to use the LRU least recently used algorithm to remove an idle cache line from the data cache when judging that the data cache misses according to the data information flag of the hit cache line.

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