CN108063164B - High-voltage bidirectional thyristor and manufacturing method thereof - Google Patents

Abstract

The invention provides a high-voltage bidirectional thyristor and a manufacturing method thereof. Belongs to the technical field of power semiconductor devices. The high-voltage thyristor is mainly used for solving the defects of more and complex structural components and the like of the existing high-voltage thyristors which are connected in series after being connected in anti-parallel. The main characteristics of the device are as follows: the semiconductor chip is four-terminal P ⁺ N ⁺ PP ^‑ N ^‑ P ^‑ PN ⁺ P ⁺ Nine layers of structures, wherein four terminals are respectively a T1 pole, an upper department pole, a T2 pole and a lower department pole, and 2 thyristors are in antiparallel connection; the center gate is of a PNP structure and is used for isolating the anti-parallel thyristors; the forward and reverse blocking voltage of the thyristor device can reach 6500V or above, and the forward and reverse conduction of the double-voltage thyristor can be controlled by a control signal; an isolation layer with low doping concentration is arranged between the anti-parallel thyristors, so that the mutual influence of the anti-parallel thyristors is reduced. The device has the characteristics of obviously improving the withstand voltage of the bidirectional thyristor device, along with simplicity, easy use, simplified process, simplified structure and improved working reliability. The method is mainly applied to alternating current motor control and high-voltage explosion-proof soft starter devices.

Description

High voltage bidirectional thyristor and manufacturing method thereof

technical field

The invention belongs to the technical field of power semiconductor devices. It specifically relates to a semiconductor bidirectional switch device with a high voltage of 6500V or more, which is mainly used in high-voltage AC motor control and high-voltage explosion-proof soft starter devices.

Background technique

At present, the semiconductor devices used in high-voltage AC motor control and high-voltage explosion-proof soft starters are high-voltage thyristors. The valve group is composed of anti-parallel high-voltage thyristors connected in series, and receives the trigger signal sent by the control unit to control the AC output. The typical valve group is shown in Figure 6. , increasing the complexity of the device. The more simplified and stable solution is to integrate the reverse-connected high-voltage thyristors into a single device (BCT), the valve group is more simplified, and the control is more convenient. The typical circuit is shown in Figure 7, making full use of radiators and other accessories to reduce peripheral resistance Capacitive absorption circuit and space occupation.

The conventional low-voltage triac is an N ⁺ PNPN ⁺ five-layer three-terminal center gate structure device. Unlike ordinary thyristors, the low-voltage triac has four pn junctions and adopts a junction gate structure. There are not only The p-type layer, as well as the n-type layer, the polarity of the gate can be positive or negative, so as to turn on two anti-parallel thyristors; it is an AC component, and its volt-ampere characteristics are symmetrical, in the first quadrant and The third quadrant can be turned on, and the gate can be positive or negative. The usual manufacturing method is to directly perform P-type diffusion on both ends of the N-type silicon wafer to form a symmetrical PNP structure, and then thin the p1 region to increase the third quadrant. Trigger sensitivity, perform N-type selective diffusion on the right or left half of the P region at the cathode end, and finally form a PNPN structure; perform N-type selective diffusion on the left or right half of the P region at the anode end, forming an NPNP structure, often positive There are differences in the blocking voltage and on-state voltage drop of reverse thyristors. The conventional blocking voltage of bidirectional thyristor devices with this structure is 600V ~ 1800V. According to this process, it is impossible to achieve higher withstand voltage and the dynamic characteristics deteriorate, which is no longer feasible. . The traditional technology no longer has the practicability of bidirectional thyristor devices above 2500V.

Contents of the invention

The object of the present invention is to address the above-mentioned shortcomings and provide a high-voltage bidirectional thyristor (BCT) device applicable to 2500V and above, that is, a high-voltage bidirectional thyristor and a manufacturing method thereof. It can significantly improve the withstand voltage of the device, that is, maintain the anti-parallel characteristics of the original design thyristor, and is simple, easy to use, and simplified in process, thereby improving the blocking voltage level and on-state capability of the device, simplifying the structure and improving work reliability.

The technical solution of the high-voltage bidirectional thyristor of the present invention is: a high-voltage bidirectional thyristor, which is packaged by the lower sealing part of the tube case, the lower gate assembly, the lower gasket, the semiconductor chip, the upper gasket, the upper gate assembly and the upper sealing part It is characterized in that: the semiconductor chip is a four-terminal P ⁺ N ⁺ PP ^- N ^- P ^- PN ⁺ P ⁺ nine-layer structure, including four terminals of T1 pole, upper gate pole, T2 pole and lower gate pole; The left half of the semiconductor chip, from bottom to top, is P ⁺ N ⁺ PP ^- N ^- P ^- PP ⁺ eight-layer structure, the lower part is the thyristor cathode, and the upper part is the thyristor anode; the right half of the semiconductor chip, from the bottom The top is P ⁺ PP ^- N ^- P ^- PN ⁺ P ⁺ eight-layer structure, the lower part is the anode of the thyristor, and the upper part is the cathode of the thyristor; the left and right sides of the semiconductor chip form an anti-parallel structure of the thyristor; the center of the upper gate and the lower gate The gate forms a PNP structure to isolate the anti-parallel thyristor; the single thyristor P ⁺ N ⁺ PP ^- N ^- P ^- PP ⁺ structure in the left half of the semiconductor chip is the anode emitter P ⁺ layer, the anode high concentration P1 layer, anode low-concentration P1 ^- layer, base N1, cathode low-concentration P2 ^- layer, cathode high-concentration P2 layer, cathode collector N ⁺ layer and cathode short-circuit P ⁺ layer; the upper gate and the upper anode or An isolation layer with a low doping concentration is provided between the lower gate electrode and the lower anode to reduce the interference and influence of turning on and off the positive and negative parallel thyristors; the surface of the high-concentration P2 layer of the cathode is provided with a cathode collector N ⁺ layer, The central gate P ⁺ layer of the upper gate, the enlarged gate P ⁺ area, and the cathode short-circuit area P ⁺ layer.

The left half of the semiconductor chip and the right half of the semiconductor chip described in the technical solution of the high-voltage bidirectional thyristor of the present invention are bounded by the vertical center line; the structure of the right half of the semiconductor chip rotates around the center point O of the chip with the thyristor structure of the left half 180°, forming an anti-parallel structure of thyristors, the two sides of the vertical center line are the central gate regions of the PNP structure, and isolating the anti-parallel thyristors; the impurity concentration distribution of the high-concentration P1 layer of the anode and the high-concentration P2 layer of the cathode Changes along the radial direction, with a low concentration of impurities in the junction terminal region.

The surface impurity concentration of the anode emitter P ⁺ layer and the cathode short-circuit region P ⁺ layer described in the technical solution of the high-voltage triac of the present invention is 0.8-4.5×10 ²⁰ /cm ³ , and the junction depth is 8-16 μm or 16-22 μm The impurity concentration on the surface of the anode high-concentration P1 layer and the cathode high-concentration P2 layer is 0.5-1.2×10 ¹⁸ /cm ³ , and the junction depth is 32-45 μm or 45-60 μm; the anode low-concentration P1 ^-layer and the cathode low-concentration ^P2 -layer The surface impurity concentration is 0.3-3.0×10 ¹⁶ /cm ³ , the junction depth is 90-120 μm or 120-145 μm; the surface impurity concentration of the cathode collector N ⁺ layer is 0.9-6.5×10 ²⁰ /cm ³ or 4.0-9.0×10 ¹⁹ /cm ³ , and the junction depth is 10-16 μm or 16-25 μm.

The width of the isolation layer with low doping concentration described in the technical solution of the high-voltage bidirectional thyristor of the present invention is 2.2 to 3.0 times the thickness of the base region N1.

The material of the lower gasket and the upper gasket described in the technical solution of the high-voltage triac of the present invention is molybdenum, silver, copper, or any combination thereof, and the surface is plated with ruthenium, rhodium or no coating.

The technical solution of the method for manufacturing a high-voltage bidirectional thyristor in the present invention is: a method for manufacturing a high-voltage bidirectional thyristor, which is characterized in that it includes the following process steps:

① Select N-type single crystal silicon wafers with a thickness of 800-1000 μm or 1020-1380 μm, a resistivity of 180-320Ω•cm or 340-520Ω•cm, and a crystal orientation of <111> or <100>. Corrosion or phosphorus absorption process treatment;

② Low-concentration distribution ^of Al impurities on both ^sides of the silicon wafer diffuses and oxidizes to form an anode P1 ^- region and a cathode P2 ^- region. 0.3～3.0×10 ¹⁶ /cm ³ ;

③High concentration distribution or selective diffusion of Al or Ga on both sides of the silicon wafer to form an anode P1 area and a cathode P2 area. 1.2×10 ¹⁸ /cm ³ ;

④Phosphorus is selectively diffused and oxidized on the cathode short base region P2 layer on the bottom of the left half of the silicon wafer and the top of the right half of the silicon wafer to form the cathode N ⁺ region, and the surface impurity concentration of the cathode N ⁺ region is 0.4 to 7.0×10 ²⁰ /cm ³ , the junction depth of the cathode N ⁺ region is 10-20μm;

⑤ The double-sided surface of the silicon wafer selectively absorbs and diffuses high-concentration boron; the anode P1 area and the cathode N ⁺ layer short circuit area form the anode P ⁺ layer and the cathode P ⁺ layer after boron diffusion, and the junction depth of the anode P ⁺ layer and the cathode P ⁺ layer is 8-22 μm, the surface impurity concentration of the anode P ⁺ layer and the cathode P ⁺ layer is 0.8-4.5×10 ²⁰ /cm ³ ;

⑥ Evaporate a metal conductive layer on the surface of the silicon wafer, and the thickness of the conductive layer is 8-15 μm or 15-30 μm; selectively etch the conductive layer on both sides of the silicon wafer to form the center gate of the upper gate and the center gate of the lower gate pole, upper amplifying gate, lower amplifying gate, upper cathode, lower cathode, upper anode and lower anode;

⑦ The chip is shaped on the table, and the shape structure is double positive angle shape or double negative angle shape; the angle size of the positive bevel angle is: 30º～80º, and the angle size of the negative bevel angle is: 20º～45º and 1.2º～4.5º;

⑧The chip table is chemically etched, and then the edge surface of the table is passivated and protected with glue to obtain a semiconductor chip;

⑨Encapsulate the semiconductor chip with the lower sealing part of the tube case, the lower gate assembly, the lower gasket, the upper gasket, the upper gate assembly, and the upper sealing part.

Between the 8th and 9th steps described in the technical solution of the method for manufacturing high-voltage bidirectional thyristors in the present invention, electron irradiation or proton irradiation is used to control the chip minority carrier lifetime and restore the charge to the required value.

The anode P+ layer and the cathode P+ layer of the fifth step described in the technical solution of the method for manufacturing high-voltage triacs of the present invention adopt high-concentration boron absorption and diffusion, and the process conditions are:

① Alcohol source or latex source is used as boron source, which is a saturated solution of boron oxide in alcohol or latex source, and boron source is sprayed or coated on both sides of the silicon wafer, and constant surface source diffusion method is used;

②Propulsion conditions: 1180～1200℃, N2=6L/min, O2=0.5L/min, time 100～200min.

Through the technical solution described in the implementation of the high-voltage bidirectional thyristor, the following technical effects can be achieved:

1. It adopts a single BCT device and integrates two anti-parallel thyristors. The number of components can be reduced by 50% compared with the anti-parallel thyristors. It can give full play to the ability of the radiator. It has the characteristics of compact device, small size and light weight. At the same time, two thyristors are combined in anti-parallel, which reduces the wiring inductance and simplifies the resistance-capacitance absorption circuit;

2. The crimping structure is adopted to improve the forward and reverse voltage blocking ability, and the short circuit structure in which the anode serves as the cathode at the same time reduces the forward a2 and improves the reliability of device voltage blocking. The forward and reverse resistance of the thyristor with the structure of the present invention The cut-off voltage can reach above 6500V;

3. When a forward voltage is applied between the T1 pole and the T2 pole of the device, a small trigger current (usually 50mA~1000mA) is applied between the gate G1 and T1 poles, the thyristor in the A1 area is turned on, and the thyristor in the A2 area is blocked; When a positive voltage is applied between the T2 pole and the T1 pole of the device, a small trigger current is applied between the gate G2 and the T2 pole, the thyristor in the A2 area is turned on, and the thyristor in the A1 area is blocked; by controlling the signal between G and T, it can be Control the positive and negative conduction of the double-voltage thyristor;

The invention integrates two anti-parallel high-voltage thyristors, utilizes crimping packaging technology, reduces device voltage drop, improves the uniformity and consistency of parameters between devices, and improves the consistency of series connection of high-voltage devices. The invention is mainly applied to devices such as AC motor control, high-voltage explosion-proof soft starter power supply and the like.

Description of drawings

In order to illustrate the technical solutions of the present invention more clearly, the following briefly introduces the accompanying drawings used in the description of the embodiments. Apparently, the drawings described below are only some embodiments of the present invention.

Fig. 1 is a schematic diagram of the product structure of the present invention.

Fig. 2 is a schematic diagram of the longitudinal structure of the chip and the shape of the double-negative mesa in the present invention.

Fig. 3 is a schematic diagram of the vertical structure of the junction terminal low-doped chip of the present invention and the shape of the double negative angle mesa.

Fig. 4 is a schematic diagram of the double positive angle mesa shape of the chip of the present invention.

Fig. 5 is a schematic diagram of double positive angle mesa modeling of a junction terminal low-doped chip of the present invention.

Fig. 6 is a schematic diagram of the valve body structure of the original product.

Fig. 7 is a schematic diagram of the valve body structure of the product of the present invention.

Fig. 8 is a schematic diagram of the longitudinal structure of a low-voltage bidirectional thyristor chip.

In the figure: 1. The lower sealing part of the tube case; 2. The lower gasket; 3. The rubber injection ring; 4. The semiconductor chip; 5. The upper gasket; 6. The upper sealing part; 7. The upper gate assembly; 7. Lower gate assembly; T1. T1 pole; T2. T2 pole, G1. Upper gate pole; G2. Lower gate pole; A1-lower anode, K1-upper cathode, G1'-upper amplified gate, A2-upper anode, K2-lower cathode, G2'-lower amplifying gate; 12. vertical centerline of the chip; 41. anode emitter P ⁺ layer; 42. anode high concentration P1 layer; 43. anode low concentration P1 ^- layer; 44. base region N1; 45. Cathode low-concentration P2 ^- layer; 46. Cathode high-concentration P2 layer; 47. Cathode collector N ⁺ layer; 48. Enlarged gate P ⁺ region; 49. Cathode short-circuit region P ⁺ layer; 50. Low doping Isolation layer with impurity concentration; 51. Junction terminal area.

Detailed ways

The embodiments of the present invention will be fully described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are only some of the embodiments of the present invention, not all of them. Any embodiment based on the present invention, and all other embodiments obtained by those skilled in the art without creative work, all belong to the scope of protection of the present invention.

Embodiment 1 As shown in Fig. 2, Fig. 4 and Fig. 1, a high-voltage bidirectional thyristor designed according to 6500V, with a chip specification of Φ50mm. It is packaged by the lower sealing part 1 of the tube case, the lower gate component 7 , the lower gasket 2 , the semiconductor chip 4 , the upper gasket 5 , the upper gate component 7 and the upper sealing part 6 . The semiconductor chip 4 has a four-terminal P ⁺ N ⁺ PP ^- N ^- P ^- PN ⁺ P ⁺ nine-layer structure, and the four terminals are respectively T1 pole, upper gate pole G1, T2 pole and lower gate pole G2. The left half of the semiconductor chip 4, from bottom to top is P ⁺ N ⁺ PP ^- N ^- P ^- PP ⁺ eight-layer structure, the lower part is the thyristor cathode, the upper part is the thyristor anode, the right half of the semiconductor chip 4, from bottom to top The order is P ⁺ PP ^- N ^- P ^- PN ⁺ P ⁺ eight-layer structure, the lower part is the anode of the thyristor, and the upper part is the cathode of the thyristor. The entire left and right sides of the semiconductor chip 4 form an anti-parallel structure of thyristors. The central gates of the upper gate G1 and the lower gate G2 form a PNP structure to isolate the anti-parallel thyristors. The single thyristor P ⁺ N ⁺ PP ^- N ^- P ^- PP ⁺ structure in the left half of the semiconductor chip 4 is the anode emitter P ⁺ layer 41, the anode high-concentration P1 layer 42, the anode low-concentration P1 ^- layer 43, and the base region N1 (44), cathode low-concentration P2 ^- layer 45, cathode high-concentration P2 layer 46, cathode collector N ⁺ layer 47 and cathode short-circuit region P ⁺ layer 49, the forward and reverse blocking voltage of the thyristor device can reach more than 6500V, and the device When a forward voltage is applied between T1 pole and T2 pole, a small trigger current (usually 50mA~1000mA) is applied between the upper gate G1 and T1 pole, the thyristor in the A1 area of the lower anode is turned on, and the thyristor in the A2 area of the upper anode is blocked. When a forward voltage is applied between the T2 and T1 poles of the device, a small trigger current is applied between the lower gate G2 and T2 poles, the thyristor in the A2 area of the upper anode is turned on, and the thyristor in the A1 area of the lower anode is blocked. By controlling the signal between G and T, the forward and reverse conduction of the double voltage thyristor can be controlled. An isolation layer 50 with a low doping concentration is provided between the upper gate G1 and the upper anode A2 or between the lower gate G2 and the lower anode G1 to reduce the interference and influence of turning on and off of the positive and negative parallel thyristors. On the surface of the cathode high-concentration P2 layer 46 are provided a cathode collector N ⁺ layer 47, a central gate P ⁺ layer of the upper gate G1, an amplifying gate P ⁺ region 48, and a cathode short-circuit region P ⁺ layer 49. The main process steps are as follows.

The silicon single crystal is made of N-type <100> or <111> crystal orientation NTD material, and the N-type single crystal silicon wafer has a resistivity of 340-420Ω•cm and a thickness of about 1280µm. Both sides of the silicon wafer are treated by chemical etching or phosphorus absorption process.

Low-concentration distribution of Al impurities on both sides of the silicon wafer diffuses and oxidizes to form an anode P1 ^- region and a cathode P2 ^- region. The junction depth of the anode P1 ^-region and the cathode ^P2 -region is 80-110 μm or 110-140 μm, and the impurity concentration on the surface is 0.3-3.0×10 ¹⁶ /cm ³ .

High concentration distribution or selective diffusion of Al or Ga on both sides of the silicon wafer to form the anode P1 area and the cathode P2 area. The junction depth between the anode P1 region and the cathode P2 region is 30-42 μm or 42-55 μm, and the impurity concentration on the surface is 0.5-1.2×10 ¹⁸ /cm ³ . The width of the isolation layer 50 with low doping concentration is 2.2-3.0 times the thickness of the base region N1 44 .

The anode high-concentration P1 layer 42, the cathode high-concentration P2 layer 46, the anode low-concentration P1 ^- layer 43, and the cathode low-concentration P2 ^- layer 45 can also adopt the simultaneous diffusion of Al and Ga double impurities, taking advantage of the different diffusion coefficients of the double impurities , The impurity distribution and junction depth with low concentration at the front and high concentration at the surface are formed at the same diffusion time.

Selective phosphorous diffusion and oxidation are carried out on the cathode short base region P2 layer on the bottom of the left half of the silicon wafer and the top of the right half of the silicon wafer to form the cathode N ⁺ region, and the surface impurity concentration of the cathode N ⁺ region is 0.4 to 7.0×10 ²⁰ / cm ³ , the junction depth of the cathode N ⁺ region is 10-20 μm.

Selective high-concentration boron absorption and diffusion on double-sided surfaces of silicon wafers. The anode P1 area and ^the cathode N ⁺ layer short-circuit area are diffused by boron to form ^the anode P ⁺ layer and the cathode P ⁺ layer. The junction depth of the anode P ⁺ layer and the cathode P ⁺ layer is 8-22 μm. The surface impurity concentration is 0.8-4.5×10 ²⁰ /cm ³ . The anode P ⁺ layer and the cathode P ⁺ layer are formed by boron spraying or boron coating diffusion. Its process conditions are:

① Alcohol source or latex source is used as boron source, which is a saturated solution of boron oxide in alcohol or latex source, and boron source is sprayed or coated on both sides of the silicon wafer, and constant surface source diffusion method is used;

②Propulsion conditions: 1180～1200℃, N2=6L/min, O2=0.5L/min, time 100～200min.

The surface impurity concentration and junction depth of each process step, after diffusion and advancement in the subsequent process, form a semiconductor chip with the following parameter structure: the surface impurity concentration of the anode emitter P ⁺ layer 41 and the cathode short-circuit region P ⁺ layer 49 is 0.8 to 4.5× 10 ²⁰ /cm ³ , the junction depth is 8-16 μm or 16-22 μm; the surface impurity concentration of the anode high-concentration P1 layer 42 and the cathode high-concentration P2 layer 46 is 0.5-1.2×10 ¹⁸ /cm ³ , and the junction depth is 32-45 μm Or 45~60μm; anode low concentration P1 ^-layer 43, cathode low concentration P2 ^-layer 45 surface impurity concentration 0.3~3.0×10 ¹⁶ /cm ³ , junction depth 90~120μm or 120~145μm; cathode collector N ⁺ The impurity concentration on the surface of layer 47 is 0.9-6.5×10 ²⁰ /cm ³ or 4.0-9.0×10 ¹⁹ /cm ³ , and the junction depth is 10-16 μm or 16-25 μm.

A metal conductive layer is evaporated on the surface of the silicon wafer, and the thickness of the conductive layer is 8-15 μm or 15-30 μm. Selectively etch the conductive layer on both sides of the silicon wafer to form the center gate of the upper gate G1, the center gate of the lower gate G2, the upper enlarged gate G1', the lower enlarged gate G2', the upper cathode K1, The lower cathode K2, the upper anode A1 and the lower anode A2. Wherein, the anode and cathode metal conductive layers on the same plane have the same thickness and are connected, and are ≥10 μm thicker than the central gate and amplifying gate metal conductive layers.

Mesa shape, the chip mesa is a double negative angle mesa shape, and the negative angles are: 1.2º～4.5º and 20º～45º.

The table top is chemically etched, and then the edge surface of the table top is passivated and protected with glue to form a glue injection ring 3 . A semiconductor chip 4 is obtained.

The left half and the right half of the semiconductor chip 4 are bounded by a vertical centerline 12 . The structure of the right half of the semiconductor chip 4, the left half of the thyristor structure is rotated 180° around the center point O of the chip to form an anti-parallel structure of the thyristors, and the two sides of the vertical center line 12 are the central gate regions of the PNP structure, which are connected in anti-parallel Thyristors are isolated.

The semiconductor chip 4 is packaged with the lower sealing member 1 of the tube case, the lower gate assembly 7 , the lower gasket 2 , the upper gasket 5 , the upper gate assembly 7 and the upper sealing member 6 .

Embodiment 2, as shown in FIG. 3 , is different from Embodiment 1 in that the impurity concentration distribution of the anode high-concentration P1 layer 42 and the cathode high-concentration P2 layer 46 changes along the radial direction, and the impurity concentration in the junction terminal region 51 is low-concentration impurity . This design reduces the thickness of the silicon chip or achieves a higher voltage with the same thickness of the silicon chip on the basis of ensuring the voltage characteristics, further reducing the voltage drop of the device.

Embodiment 3, as shown in Figure 4, differs from Embodiment 1 in that the shape of the chip mesa is a double positive angle shape: when the positive bevel angle is 30°-80°, the cathode area of the chip can be increased. The cathode area loss of the product in this embodiment is the smallest, and is suitable for bidirectional thyristor devices with larger currents with the same diameter.

Embodiment 4, as shown in Figure 5, differs from Embodiment 2 in that the shape of the chip mesa is a double positive angle shape: when the positive bevel angle is 30º to 80º, it can increase the cathode area of the chip and thin the silicon slice thickness. The loss of the cathode area of the product in this embodiment is the smallest. On the basis of ensuring the voltage characteristics, the thickness of the silicon wafer is reduced or the thickness of the silicon wafer can reach a higher voltage, which further reduces the voltage drop of the device and improves the flow capacity of the bidirectional thyristor.

Embodiment 5 differs from Embodiment 1 and Embodiment 2 in that the semiconductor chip 4 and the lower pad 2 are welded at low temperature, and then assembled with the upper pad 5 , and the chip mesa is in the shape of a positive and negative mesa. For the product of this embodiment, for large-diameter chips, because of the support of the lower gasket, it can ensure that the chip is not easy to break and easy to assemble.

A specific embodiment of the present invention is that a low-doped isolation layer 50 is provided between the gate and the anode, and the width of the low-doped isolation layer 50 is 2.2 to 3.0 times the thickness of the base region N1 44 . The width and doping concentration of the isolation layer can improve the voltage commutation blocking ability of the forward and reverse thyristors.

A specific embodiment of the present invention is that the material of the lower gasket 2 and the upper gasket 5 is molybdenum, or aluminum, or silver, or copper, or any combination thereof, and the surface can be coated on one or both sides, and the coating is Ruthenium or rhodium-plated, the chip is in contact with the plated surface of the gasket, which can reduce the contact voltage drop and improve reliability.

As a specific implementation of the high-voltage triac process method provided by the present invention, after the semiconductor chip 4 is produced and before packaging, the method of electron irradiation or proton irradiation is used to control the lifetime of the minority carrier of the chip and restore the charge to the required value. It can control and reduce the mutual influence of positive and negative thyristors.

Through the technical solution described in the implementation of the high-voltage bidirectional thyristor, the following technical effects can be achieved:

1. BCT devices are used, and two anti-parallel thyristors are integrated. The number of components can be reduced by 50% compared with anti-parallel thyristors. At the same time, bidirectional thyristors are used, which reduces the wiring inductance and simplifies the resistance-capacitance absorption circuit.

2. The crimping structure is adopted to improve the forward and reverse voltage blocking ability, and the short circuit structure in which the anode serves as the cathode at the same time reduces the forward a2 and improves the reliability of device voltage blocking. The forward and reverse resistance of the thyristor of the product of the present invention The cut-off voltage can reach above 6500V.

3. In the high-concentration P1 layer 42 and P2 layer 46, the impurity concentration distribution changes along the radial direction during diffusion, and the junction terminal region 51) and the isolation layer 50 are low-concentration impurities, which reduces the positive and negative effects of the thyristor and also reduces The mesa electric field improves the voltage blocking ability.

4. When a forward voltage is applied between the device T1 and T2, a small trigger current (usually 50~1000mA) is applied between the gate G1 and T1, the thyristor in the A1 area is turned on, and the thyristor in the A2 area is blocked; between the device T2 and the T1 When the forward voltage is applied, a small trigger current is applied between the gates G2 and T2, the thyristor in the A2 area is turned on, and the thyristor in the A1 area is blocked; the corresponding signal between G and T can be controlled to control the forward and reverse conduction of the double voltage thyristor.

5. The optimized boron diffusion process conditions reduce the impact of impurity concentration on the N ⁺ layer during P ⁺ diffusion.

6. The diameter of the semiconductor chip of the present invention can be Φ38-Φ150, the blocking voltage is 2500-8500V, and the average on-state current _IT(AV) is 400A-4000A.

The above descriptions are only preferred embodiments of the present invention, and do not limit the present invention in any form. Therefore, any modifications, equivalent replacements, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention without departing from the content of the present invention still belong to the protection scope of the technical solution of the present invention.

Claims (8)

1. The utility model provides a high-voltage bidirectional thyristor, is formed by encapsulation of seal (1), lower gate electrode subassembly (7), lower gasket (2), semiconductor chip (4), last gasket (5), last gate electrode subassembly (7) and last seal (6) under the tube shell, its characterized in that: the semiconductor chip (4) is four-terminal P ⁺ N ⁺ PP ^- N ^- P ^- PN ⁺ P ⁺ Nine-layer structure including four terminals of T1 pole, upper gate pole (G1), T2 pole and lower gate pole (G2); the left half part of the semiconductor chip (4) is sequentially P from bottom to top ⁺ N ⁺ PP ^- N ^- P ^- PP ⁺ An eight-layer structure, the lower part is a thyristor cathode, and the upper part is a thyristor anode; the right half part of the semiconductor chip (4) is sequentially P from bottom to top ⁺ PP ^- N ^- P ^- P N ⁺ P ⁺ Eight layers of structures, the lower part is a thyristor anode, the upper part is a thyristorThe part is a thyristor cathode; the left and right of the semiconductor chip (4) integrally form an anti-parallel structure of the thyristor; the central gates of the upper gate (G1) and the lower gate (G2) form a PNP structure to isolate the anti-parallel thyristors; the left half part of the semiconductor chip (4) is provided with a single crystal thyristor P ⁺ N ⁺ PP ^- N ^- P ^- PP ⁺ The structures are respectively anode emitter P ⁺ Layer (41), anode high concentration P1 layer (42), anode low concentration P1 ^- Layer (43), base region N1 (44), cathode low concentration P2 ^- Layer (45), cathode high concentration P2 layer (46), cathode collector N ⁺ Layer (47) and cathode short-circuit region P ⁺ A layer (49); an isolation layer (50) with low doping concentration is arranged between the upper gate electrode (G1) and the upper anode (A2) or between the lower gate electrode (G2) and the lower anode (G1), so that the interference and influence of the on-off of the forward-reverse parallel thyristors are reduced; the surface of the cathode high-concentration P2 layer (46) is provided with a cathode collector N ⁺ Center gate P of layer (47), upper gate G1 ⁺ Layer, amplifying gate P ⁺ Region (48), cathode short-circuit region P ⁺ A layer (49).

2. The high voltage triac as set forth in claim 1, wherein: the left half part and the right half part of the semiconductor chip (4) are defined by a vertical central line (12); the right half part structure of the semiconductor chip (4) rotates 180 degrees around the center point O of the chip by the left half part thyristor structure to form an anti-parallel structure of the thyristor, and the two sides of the vertical center line (12) are PNP structure center gate electrode areas and isolate the anti-parallel thyristor; the impurity concentration distribution of the anode high concentration P1 layer (42) and the cathode high concentration P2 layer (46) changes along the radial direction, and the impurity concentration distribution is low concentration impurity in the junction terminal region (51).

3. The high voltage triac as claimed in claim 1 or 2, wherein: the anode emitter P ⁺ Layer (41), cathode short-circuit region P ⁺ The impurity concentration of the surface of the layer (49) is 0.8-4.5X10 ²⁰ /cm ³ The junction depth is 8-16 μm or 16-22 μm; the impurity concentration of the surface of the anode high concentration P1 layer (42) and the cathode high concentration P2 layer (46) is 0.5 to 1.2X10 ¹⁸ /cm ³ The junction depth is 32-45 μm or 45-60 μm; anode low concentration P1 ^- Layer (43), cathode low concentration P2 ^- The impurity concentration of the surface of the layer (45) is 0.3-3.0X10 ¹⁶ /cm ³ The junction depth is 90-120 μm or 120-145 μm; cathode collector N ⁺ The impurity concentration of the surface of the layer (47) is 0.9-6.5X10 ²⁰ /cm ³ Or 4.0 to 9.0X10 ¹⁹ /cm ³ The junction depth is 10-16 μm or 16-25 μm.

4. The high voltage triac as claimed in claim 1 or 2, wherein: the width of the isolation layer (50) with low doping concentration is 2.2-3.0 times of the thickness of the base region N1 (44).

5. The high voltage triac as claimed in claim 1 or 2, wherein: the lower gasket (2) and the upper gasket (5) are made of molybdenum, silver, copper or any 2 combinations thereof, and the surfaces of the lower gasket and the upper gasket are plated with ruthenium, rhodium or no plating.

6. A method of manufacturing a high voltage triac as claimed in claim 1 or 2, characterized by comprising the following process steps:

(1) selecting an N-type monocrystalline silicon wafer with the thickness of 800-1000 mu m or 1020-1380 mu m and the resistivity of 180-320 omega cm or 340-520 omega cm, and the crystal orientation of <111> or <100>, wherein the two sides of the silicon wafer are treated by adopting a chemical corrosion or phosphorus absorption process;

(2) the Al impurity on the two sides of the silicon wafer is diffused and oxidized in low concentration distribution to form an anode P1 ^- Region, cathode P2 ^- Zone, anode P1 ^- Region and cathode P2 ^- The junction depth of the region is 80-110 μm or 110-140 μm, and the surface impurity concentration is 0.3-3.0X10 ¹⁶ /cm ³ ；

(3) The double-sided Al or Ga high concentration distribution or selective diffusion of the silicon wafer forms an anode P1 region and a cathode P2 region, and the junction depth of the anode P1 region and the cathode P2 region is 30-42 mu mOr 42-55 μm, and the surface impurity concentration is 0.5-1.2X10 ¹⁸ /cm ³ ；

(4) Selective phosphorus diffusion and oxidation are carried out on the cathode short base region P2 layer below the left half part and above the right half part of the silicon wafer to form a cathode N ⁺ Zone, cathode N ⁺ The impurity concentration of the surface of the region is 0.4-7.0X10 ²⁰ /cm ³ Cathode N ⁺ The junction depth of the region is 10-20 mu m;

(5) the double-sided surface of the silicon chip selectively absorbs and diffuses high-concentration boron; anode P1 region and cathode N ⁺ Boron diffusion in the layer short-circuit region forms anode P ⁺ Layer and cathode P ⁺ Layer, anode P ⁺ Layer and cathode P ⁺ The layer junction depth is 8-22 mu m, and the anode P ⁺ Layer and cathode P ⁺ The surface impurity concentration of the layer is 0.8-4.5X10 ²⁰ /cm ³ ；

(6) Evaporating a metal conductive layer on the surface of the silicon wafer, wherein the thickness of the conductive layer is 8-15 mu m or 15-30 mu m; selectively etching the double-sided conductive layer of the silicon wafer to form a central gate electrode of an upper gate electrode (G1), a central gate electrode of a lower gate electrode (G2), an upper amplifying gate electrode (G1 '), a lower amplifying gate electrode (G2'), an upper cathode (K1), a lower cathode (K2), an upper anode (A1) and a lower anode (A2);

(7) the chip is subjected to mesa modeling, and the modeling structure is double positive angle modeling or double negative angle modeling; wherein the angle size at the positive oblique angle is: the angle size is 1.2-4.5 degrees and 20-45 degrees under the negative oblique angle of 30-80 degrees;

(8) carrying out chemical corrosion on the chip table top, and then carrying out passivation and gluing protection on the edge surface of the table top to obtain a semiconductor chip (4);

(9) and packaging the semiconductor chip (4) with the lower sealing part (1), the lower gate electrode assembly (7), the lower gasket (2), the upper gasket (5), the upper gate electrode assembly (7) and the upper sealing part (6) of the tube shell.

7. The method of manufacturing a high voltage triac as recited in claim 6, wherein: and (3) between the step (8) and the step (9), controlling the minority carrier lifetime of the chip and recovering the charge to be a required value by adopting an electron irradiation or proton irradiation method.

8. The method of manufacturing a high voltage triac as recited in claim 6, wherein: the anode P+ layer and the cathode P+ layer in the step (5) adopt high-concentration boron absorption diffusion, and the process conditions are as follows:

the boron source adopts an alcohol source or a latex source, is an alcohol or latex source saturated solution of boron oxide, and adopts a method of spraying or coating the boron source on the two sides of the silicon wafer and diffusing the constant surface source;

propulsion conditions: 1180-1200 ℃, N ₂ =6L/ min，O ₂ =0.5L/min, time 100-200 min.