CN108039888B - DDS signal source clock generation circuit, signal source and method thereof - Google Patents
DDS signal source clock generation circuit, signal source and method thereof Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/1806—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop the frequency divider comprising a phase accumulator generating the frequency divided signal
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Abstract
The invention relates to a DDS signal source clock generation circuit, which comprises: the ARM processor calculates a first reference frequency according to waveform output frequency and reference frequency, sends the first reference frequency to the first DDS module, generates a sine wave signal of the first reference frequency according to the reference frequency by the first DDS module, outputs the sine wave signal to the first DAC module, outputs the sine wave signal to the comparator module after digital-to-analog conversion by the first DAC module, generates a square wave signal by the comparator module, and then feeds the square wave signal back to the PLL module to be multiplied to form a sampling rate clock signal, and sends the sampling rate clock signal to the second DDS module by the PLL module to provide an integer clock signal. By the scheme, the defect that the generated waveforms are inconsistent at the starting point of each period is overcome.
Description
Technical Field
The invention belongs to the field of signal sources, and particularly relates to a DDS signal source clock generation circuit, a signal source and a method thereof.
Background
At present, for a direct digital frequency Synthesizer DDS (DIRECT DIGITAL Synthesizer) signal source, a mode of clock fixing and sampling rate fixing is basically adopted to generate required waveforms, and the advantages of the fixed clock and the fixed sampling rate are that the implementation technology is relatively simple and the cost is low. However, when periodic signals are generated, when the phases are accumulated to the maximum value due to the DDS, the situation that the phases overflow exists, so that the signals of each period cannot be generated from the same point at the same time is mainly shown as the most obvious when the sampling rate and the waveform frequency cannot be divided, when the generated pulse waves with the sampling rate and the waveform frequency not being divided are generated, the waveform of the generated pulse waves is observed on an oscilloscope, and the situation that the pulse waves have jitter of one sampling rate period except the trigger edge can be observed.
Disclosure of Invention
In view of the foregoing, an object of the present invention is to provide a DDS signal source clock generating circuit, a signal source and a method thereof, so as to overcome the defect that the generated waveforms are inconsistent at the starting point of each period.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
The DDS signal source clock generating circuit of the present invention includes: the ARM processor calculates a first reference frequency according to waveform output frequency and reference frequency, sends the first reference frequency to the first DDS module, generates a sine wave signal of the first reference frequency according to the reference frequency by the first DDS module, outputs the sine wave signal to the first DAC module, outputs the sine wave signal to the comparator module after digital-to-analog conversion by the first DAC module, generates a square wave signal by the comparator module, and then feeds the square wave signal back to the PLL module to be multiplied to form a sampling rate clock signal, and sends the sampling rate clock signal to the second DDS module by the PLL module to provide an integer clock signal.
In the DDS signal source clock generating circuit, preferably, the clock generating circuit includes: and the second DAC module is used for receiving data generated according to the integer clock signal and performing digital-to-analog conversion.
In the DDS signal source clock generating circuit, preferably, the duty ratio of the square wave signal is 50%.
In the DDS signal source clock generating circuit, preferably, the frequency of the sine wave signal is a first reference frequency of 1/8.
Preferably, the DDS signal source clock generating circuit further includes: the frequency control device comprises a phase accumulator, a phase accumulated value register and a read-only memory, wherein the phase accumulator accumulates frequency control words, the phase accumulated value register is used for buffering phase values and feeding the phase values back to the phase accumulator to accumulate the next phase value, and the read-only memory is used for storing waveform data after sine wave digitization.
A signal source according to the present invention comprises: the DDS signal source clock generation circuit as described above.
The invention relates to a DDS signal source clock generation method, which comprises the following steps:
Acquiring a first reference frequency, wherein the first reference frequency is the product of an integer part of the ratio of the reference frequency to the waveform output frequency and the waveform output frequency;
generating a sine wave signal of the first reference frequency according to the reference frequency;
performing digital-to-analog conversion on the sine wave signal to generate a square wave signal;
the square wave signal is multiplied to a sample rate clock signal to provide an integer clock signal.
Preferably, the DDS signal source clock generating method further includes: data generated from the integer clock signal is received and digital-to-analog converted.
In the DDS signal source clock generating method, preferably, the frequency of the sine wave signal is a first reference frequency of 1/8.
Preferably, the DDS signal source clock generating method further includes:
Acquiring a frequency control word through a phase accumulator and accumulating the frequency control word;
the phase accumulated value register feeds back a phase value to the phase accumulator to accumulate a next phase value;
And reading the waveform data of the digitized sine wave according to the phase value to generate a sine wave signal.
The DDS signal source clock generating circuit, the signal source and the method provided by the invention can keep consistency of the generated waveforms at the starting point of each period to generate stable data output, and finally solve the defects brought by the conventional DDS signal source.
Drawings
FIG. 1 is a schematic diagram of a DDS signal source clock generating circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a first DDS module according to an embodiment of the present invention;
fig. 3 is a flowchart of a DDS signal source clock generation method according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail with reference to the accompanying drawings and examples.
An embodiment of the present invention provides a DDS signal source clock generating circuit, as shown in fig. 1, where the clock generating circuit includes: ARM (Advanced RISC Machines) a processor 1, a first DDS (DIRECT DIGITAL Synthesizer) module 21, a second DDS module 22, a PLL (Phase Locked Loop) module 23, a first DAC (Digital Analogue Converter) module 3 and a comparator module 4, wherein the ARM processor 1 calculates a first reference frequency according to a waveform output frequency and a reference frequency, sends the first reference frequency to the first DDS module 21, the first DDS module 21 generates a sine wave signal of the first reference frequency according to the reference frequency and outputs the sine wave signal to the first DAC module 3, the first DAC module 3 performs digital-to-analog conversion and outputs the sine wave signal to the comparator module 4, the comparator module 4 generates the square wave signal and then feeds the square wave signal back to the PLL module 23 to perform frequency multiplication to form a sampling rate clock signal, and the PLL module 23 sends the sampling rate clock signal to the second DDS module 22 to provide an integer clock signal. Preferably, the first reference frequency Fref1 is the product of the integer part of the ratio of the reference frequency Fref to the waveform output frequency Fout and the waveform output frequency Fout. Specifically, as shown in formula 1 and formula 2:
taking the value of D and calculating to obtain a first reference frequency Fref1:
fref1=fout x D formula 2,
Wherein D is an integer part of the ratio of the reference frequency Fref to the waveform output frequency Fout, and D is a fractional part of the ratio of the reference frequency Fref to the waveform output frequency Fout. The condition of integer division can be always satisfied between the calculated first reference frequency Fref and the waveform output frequency Fout.
And then generating a sine wave signal of a first reference frequency Fref1 through a first DDS module according to a clock of the reference frequency Fref, outputting the sine wave signal to a first DAC module, and performing digital-to-analog conversion on the sine wave signal by the first DAC module and outputting the sine wave signal to a comparator module. Preferably, the comparator module is an analog comparator, which can generate a TTL square wave signal Fref2 according to the output of the first DAC module, where Fref2 is a non-standard dynamic value, and the Fref2 signal is fed back to the PLL module as a clock signal, and the PLL module multiplies the clock signal to generate a stable sampling rate clock signal Fsample to provide the integer clock signal to the second DDS module 22.
In a preferred embodiment, the first DDS module, the second DDS module and the PLL module in the foregoing embodiments may be implemented by FPGA technology, so as to improve the integration level of the clock generation circuit.
According to the DDS signal source clock generation circuit disclosed by the embodiment of the invention, the condition of integer division is met between the first reference frequency Fref and the waveform output frequency Fout, so that the generated waveform and the sampling rate are in an integer division state, a stable integer clock signal is provided for the second DDS module through the setting of the analog comparator and the PLL, the second DDS module calculates according to the newly generated sampling rate clock signal, the calculated frequency control words are in integer multiple relation, and therefore, the generated waveform can be kept consistent at the starting point of each period to generate stable data output, and finally, the defects brought by the conventional DDS signal source are solved.
The DDS signal source clock generating circuit provided by the embodiment of the present invention preferably, as shown in fig. 1, the clock generating circuit further includes: the second DAC module 5 is configured to receive data generated according to the integer clock signal and perform digital-to-analog conversion, and the stable integer clock signal provided by the second DDS module is thus generated and output to the second DAC module 5 for performing digital-to-analog conversion.
Preferably, in the DDS signal source clock generating circuit in the embodiment of the present invention, the duty ratio of the square wave signal TTL is 50%.
In the DDS signal source clock generating circuit provided by the embodiment of the invention, preferably, the frequency of the sine wave signal is the first reference frequency of 1/8. Specifically, after the first reference frequency Fref1 is calculated, the first DDS module and the reference frequency Fref are used to generate a sine wave signal of the first reference frequency Fref1 with the frequency of 1/8.
In the DDS signal source clock generating circuit provided in the embodiment of the present invention, preferably, as shown in fig. 2, the first DDS module 21 further includes: a phase accumulator 211, a phase accumulation value register (DFF) 212 and a Read Only Memory (ROM) 213, wherein the phase accumulator 211 accumulates the frequency control word, the phase accumulation value register 212 is used for buffering the phase value, and simultaneously feeding back the phase value to the phase accumulator 211 to accumulate the next phase value, and the ROM 213 is used for storing the waveform data after the sine wave is digitized. Specifically, the ARM processor calculates the frequency control word Freq_word and provides the frequency control word Freq_word to the phase accumulator 211 for accumulation; the phase accumulated value register 212 caches the phase value, and feeds back the cached phase value to the phase accumulator 211 to accumulate the phase value of the next time, the read-only memory 213 stores the waveform data after sine wave digitization, and the waveform data after sine wave digitization, that is, the value of the sine wave, in the read-only memory 213 can be read through the 48-bit data output by the phase accumulated value register 212.
Preferably, in the embodiment of the invention, the data adopts a width of 48 bits, and the frequency can be accurate to 0.8uHz, so that the application scene of the embodiment of the invention is met. Specifically, the wider the frequency control word freq_word bit width is, the higher the frequency accuracy is, and the frequency control word freq_word bit width is determined according to practical situations. That is, in other embodiments, frequency control words of different bit widths may be employed as desired. The waveform data digitized for the sine wave is stored in the rom 213, and the sine wave value in the rom 213 is read by the 48-bit data output from the phase accumulation value register 212. Preferably, since the ROM size is limited by resources, it is necessary to truncate 48 bits of data before reading, taking the upper 10 bits of data in the first DDS module 21 and the upper 16 bits of data in the second DDS module 22. Specifically, in the first DDS module 21, in order to generate the high-frequency clock Fref2 signal, the first DAC module and the comparator module are arranged in the peripheral circuit, so that the high-order 10 bits of data have no influence on the quality of the generated signal, and in the second DDS module 22, the generated signal has a wider frequency range, but the vertical effective value of the second DAC is 16 bits, so that the high-order 16 bits of data are taken in order to give consideration to the low-frequency signal, the signal quality can be ensured, and the hardware resources are not wasted. The sine wave signal is output from the FPGA to the first DAC module 3, and the comparator module 4 generates a TTL level square wave signal Fref2, so that the Fref2 has small jitter due to the characteristics of the 48-bit high-precision phase and analog comparator in the first DDS module. The output signal Fref2 of the comparator module 4 is used as a clock source for generating waveforms inside the FPGA, meanwhile, the square wave signal Fref2 output by the comparator module 4 is connected to a special clock I/O pin of the FPGA, a digital phase-locked loop is internally instantiated, and the digital phase-locked loop has a large input dynamic range, and the performance is similar to that of an analog phase-locked loop under the conditions of integral multiple frequency multiplication and frequency division, so that the digital phase-locked loop 23 module is used for 8 times of the input square wave of the comparator module 4 to generate a clock Fsample required by the second DDS module, the second DDS module 22 calculates according to the newly generated Fsample clock frequency, and calculated frequency words are integral multiple relations, so that the starting point of each period of the generated waveform can be kept consistent, and the defect brought by the conventional DDS is overcome.
The embodiment of the invention also provides a signal source, and specifically, the signal source comprises the DDS signal source clock generation circuit according to any embodiment.
In the scheme of adding an analog comparator, compared with the scheme of adding a phase-locked loop at the periphery, the signal source provided by the embodiment of the invention is cheaper, the response time of the peripheral phase-locked loop is slower than that of the digital phase-locked loop in the FPGA, the input dynamic range is smaller, and the scheme of using the embodiment of the invention is better than that of an external phase-locked loop in performance, and is better than that of the traditional fixed sampling rate and fixed clock mode. Performance and waveform quality are effectively improved with little increase in cost overall.
The embodiment of the invention provides a DDS signal source clock generation method, as shown in fig. 3, comprising the following steps:
Step 301, obtaining a first reference frequency, where the first reference frequency is a product of an integer part of a ratio of the reference frequency to the waveform output frequency and the waveform output frequency;
Specifically, the calculation formulas between the first reference frequency Fref1 and the reference frequency Fref and the waveform output frequency Fout are shown in formula 1 and formula 2:
taking the value of D and calculating to obtain a first reference frequency Fref1:
fref1=fout x D formula 2,
Wherein D is an integer part of the ratio of the reference frequency Fref to the waveform output frequency Fout, and D is a fractional part of the ratio of the reference frequency Fref to the waveform output frequency Fout. The condition of integer division can be always satisfied between the calculated first reference frequency Fref and the waveform output frequency Fout.
Step 302, generating a sine wave signal of the first reference frequency according to the reference frequency;
Step 303, performing digital-to-analog conversion on the sine wave signal to generate a square wave signal;
step 304 multiplies the square wave signal into a sample rate clock signal to provide an integer clock signal.
Preferably, the TTL square wave signal Fref2 generated after digital-to-analog conversion is a non-standard dynamic value, and after the Fref2 signal is fed back and input as a clock signal, frequency multiplication is performed to generate a stable sampling rate clock signal Fsample, and finally an integer clock signal is provided for the second DDS module. In a preferred embodiment of the present invention, the duty cycle of the square wave signal TTL is 50%.
According to the DDS signal source clock generation method disclosed by the embodiment of the invention, the condition of integer division is met between the first reference frequency Fref1 and the waveform output frequency Fout, so that the generated waveform and the sampling rate are in an integer division state, the calculated frequency control words are in integer multiple relation according to the newly generated sampling rate clock signal through the stable integer clock signal, the generated waveform can be kept consistent at the starting point of each period to generate stable data output, and the defects brought by a conventional DDS signal source are finally solved.
The DDS signal source clock generation method provided by the embodiment of the invention is better, and the method further comprises the following steps: data generated from the integer clock signal is received and digital-to-analog converted.
According to the DDS signal source clock generation method provided by the embodiment of the invention, preferably, the frequency of the sine wave signal is the first reference frequency of 1/8. Specifically, after the first reference frequency Fref1 is calculated, a sine wave signal of the first reference frequency Fref1 with a frequency of 1/8 is generated.
The embodiment of the invention provides a DDS signal source clock generation method, which preferably further comprises the following steps:
Acquiring a frequency control word through a phase accumulator and accumulating the frequency control word;
the phase accumulation register feeds back a phase value to the phase accumulator to accumulate a next phase value;
And reading the waveform data of the digitized sine wave according to the phase value to generate a sine wave signal.
Specifically, the frequency control word freq_word is provided for a phase accumulator for accumulation; the phase accumulated value register caches the phase value, and meanwhile, the cached phase value is fed back to the phase accumulator to accumulate the phase value of the next time, the read-only memory stores waveform data after sine wave digitization, and the waveform data after sine wave digitization in the read-only memory, namely the value of the sine wave, can be read through the 48-bit phase data output by the phase accumulated value register.
In summary, according to the DDS signal source clock generation circuit, the signal source and the method provided by the embodiment of the invention, the first reference frequency Fref1 and the waveform output frequency Fout meet the condition of integer division, so that the generated waveform and the sampling rate are ensured to be in the integer division state, and the second DDS module is provided with a stable integer clock signal through the arrangement of the analog comparator and the PLL, so that the second DDS module calculates according to the newly generated sampling rate clock signal, the calculated frequency control words are in integer multiple relation, and the generated waveform can keep consistent at the starting point of each period to generate stable data output, and finally the defects brought by the conventional DDS signal source are solved.
The present application is not limited to the above-mentioned preferred embodiments, and any person who can obtain other various products under the teaching of the present application can make any changes in shape or structure, and all the technical solutions that are the same or similar to the present application fall within the scope of the present application.
Claims (8)
1. A DDS signal source clock generation circuit, the clock generation circuit comprising: the system comprises an ARM processor, a first DDS module, a second DDS module, a PLL module, a first DAC module and a comparator module, wherein the ARM processor calculates a first reference frequency according to waveform output frequency and reference frequency and sends the first reference frequency to the first DDS module, the first DDS module generates a sine wave signal of the first reference frequency according to the reference frequency and outputs the sine wave signal to the first DAC module, the first DAC module performs digital-to-analog conversion and outputs the sine wave signal to the comparator module, the comparator module generates a square wave signal and then feeds the square wave signal back to the PLL module to perform frequency multiplication to form a sampling rate clock signal, and the PLL module sends the sampling rate clock signal to the second DDS module to provide an integer clock signal;
The first reference frequency Fref1 is the product of the integer part of the ratio of the reference frequency Fref to the waveform output frequency Fout and the waveform output frequency Fout; d = Fre/Fou, D being the integer part of the ratio of the reference frequency Fref to the waveform output frequency Fout, D being the fractional part of the ratio of the reference frequency Fref to the waveform output frequency Fout;
the clock generation circuit includes: the second DAC module is used for receiving data generated according to the integer clock signal and performing digital-to-analog conversion;
The duty cycle of the square wave signal is 50%.
2. The DDS signal source clock generating circuit of claim 1, wherein the sine wave signal has a first reference frequency of 1/8.
3. The DDS signal source clock generating circuit of claim 1, wherein said first DDS module further comprises: the frequency control device comprises a phase accumulator, a phase accumulated value register and a read-only memory, wherein the phase accumulator accumulates frequency control words, the phase accumulated value register is used for buffering phase values and feeding the phase values back to the phase accumulator to accumulate next phase values, and the read-only memory is used for storing waveform data after sine wave digitization.
4. A signal source, the signal source comprising: a DDS signal source clock generation circuit as recited in any one of claims 1-3.
5. A DDS signal source clock generation method applied to the DDS signal source clock generation circuit as claimed in claim 1, wherein the method comprises: acquiring a first reference frequency, wherein the first reference frequency is the product of an integer part of the ratio of the reference frequency to the waveform output frequency and the waveform output frequency; generating a sine wave signal of the first reference frequency according to the reference frequency; performing digital-to-analog conversion on the sine wave signal to generate a square wave signal; the square wave signal is multiplied to a sample rate clock signal to provide an integer clock signal.
6. The DDS signal source clock generating method of claim 5, characterized in that the method further comprises: data generated from the integer clock signal is received and digital-to-analog converted.
7. The DDS signal source clock generating method of claim 5, wherein the sine wave signal has a first reference frequency of 1/8.
8. The DDS signal source clock generating method of claim 5, characterized in that the method further comprises:
Acquiring a frequency control word through a phase accumulator and accumulating the frequency control word; the phase accumulated value register feeds back a phase value to the phase accumulator to accumulate a next phase value; and reading the waveform data of the digitized sine wave according to the phase value to generate a sine wave signal.
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| CN109324215B (en) * | 2018-09-21 | 2022-04-19 | 北京无线电计量测试研究所 | DDS-based standard phase generation method and device |
| CN109617540B (en) * | 2018-11-28 | 2023-09-01 | 北京宏动科技股份有限公司 | Signal delay device |
| US11146280B2 (en) * | 2018-12-31 | 2021-10-12 | Tektronix, Inc. | Digital signal processing waveform synthesis for fixed sample rate signal sources |
| CN109857188B (en) * | 2019-01-08 | 2020-06-23 | 优利德科技(中国)股份有限公司 | A method, device and system for generating pulse wave based on DDS |
| CN109542161A (en) * | 2019-01-30 | 2019-03-29 | 北京昊海雅正科技有限公司 | A kind of clock signal generating apparatus and method |
| CN110768665B (en) * | 2019-11-07 | 2023-05-09 | 电子科技大学 | DDS signal sweep frequency source system with double clock sampling rate |
| CN111693837B (en) * | 2020-06-29 | 2024-09-10 | 核动力运行研究所 | Low-voltage signal source |
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