CN109324215B - DDS-based standard phase generation method and device - Google Patents
DDS-based standard phase generation method and device Download PDFInfo
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Abstract
The invention discloses a DDS-based standard phase generation method and a DDS-based standard phase generation device, which comprise the following steps: s1, calculating a frequency control word, an amplitude control word and a phase control word according to the reference clock frequency; s2, respectively generating two sine digital sequences with fixed frequency, amplitude and phase according to the frequency control word, the amplitude control word and the phase control word obtained by calculation, wherein the phase control word of one sine digital sequence is set to be 0; s3, converting the two sine digital sequences into two step-type waveforms respectively; and S4, respectively adjusting the signal amplitudes of the two step-type waveforms, and calculating the phase difference. The method generates the standard phase based on the DDS principle, has continuous phase transformation, high frequency stability and easy control, and simultaneously ensures high resolution and accuracy of the output phase, thereby ensuring the determination and recurrence of the phase difference value.
Description
Technical Field
The invention relates to the technical field of signal processing. And more particularly, to a DDS-based standard phase generation method and apparatus.
Background
Phase is one of the basic parameters in the field of radio metrology and is an important parameter for studying the relationship between two ac signals at the same frequency. The phase measurement and control technology can solve many problems of electrical, electronic and other non-electrical measurement, such as measuring time delay characteristics, measuring distance and positioning, measuring and correcting servo systems, and the like, so that the determination and reproduction of standard phase is a basic problem in the field. The standard phase is defined based on two sinusoidal signals of the same frequency and their phase difference.
In the prior art, a passive delay network is adopted to shift the phase of a reference phase signal, so that higher accuracy can be obtained at a determined frequency and a specific phase position, but high-resolution phase adjustment fineness cannot be obtained, and obvious additional error of the phase shift frequency appears along with the increase of the frequency, so that the expansion of the upper limit frequency is limited. Another common way to generate a standard phase is to construct a standard phase generator. The standard phase generator is a double-channel signal generator and can simultaneously output two paths of sine signals with the same frequency and the accurately adjustable phase difference. The standard phase at this time is adjusted on the basis of the generation of the sinusoidal signal.
Direct Digital Synthesis (DDS) is the most common signal generation technology at present, and is based on the sampling theorem, in which digital waveforms stored in advance are reproduced after digital-to-analog conversion and filtering. At this time, the phase resolution is not only directly related to the number of bits of the DDS system phase accumulator, but also affected by the addressing phase truncation and the number of bits of the analog-to-digital conversion (DAC). In addition, a certain phase jitter exists at a frequency point with an uneven number of periodic sampling points, which affects the final phase accuracy.
Therefore, it is desirable to provide a DDS-based standard phase generation method and apparatus.
Disclosure of Invention
The invention aims to provide a DDS-based standard phase generation method and device, which are used for determining and reproducing a high-accuracy phase difference value.
In order to achieve the purpose, the invention adopts the following technical scheme:
a DDS-based standard phase generating method, comprising:
s1, calculating a frequency control word, an amplitude control word and a phase control word according to the reference clock frequency;
s2, respectively generating two sine digital sequences with fixed frequency, amplitude and phase according to the frequency control word, the amplitude control word and the phase control word obtained by calculation, and setting the phase control word of one of the sine digital sequences to be 0;
s3, converting the two sine digital sequences into two step-type waveforms respectively;
and S4, respectively adjusting the signal amplitudes of the two step-type waveforms, and calculating the phase difference.
Further, the method further comprises: in step S3, the step waveform is filtered to remove components outside the required frequency band.
Further, the method further comprises: and when the parameters of the stepped waveform after the signal amplitude is adjusted do not reach the set conditions, taking the frequency of the stepped waveform after the signal amplitude is adjusted as a second reference clock frequency, and executing the method in the steps S1-S4 again to obtain a second stepped waveform.
Further, the reference clock frequency is an integer multiple of the second reference clock frequency, and the second reference clock frequency is an integer multiple of the second stepped-waveform frequency.
The invention also discloses a DDS-based standard phase generating device, which comprises a first DDS system, wherein the first DDS system comprises:
a time schedule controller: the frequency control word, the amplitude control word and the phase control word are calculated according to the reference clock frequency and input into the digital sequence generation module;
a number sequence generation module: the device is used for respectively generating two sine digital sequences with fixed frequency, amplitude and phase according to the frequency control word, the amplitude control word and the phase control word obtained by calculation, and setting the phase control word of one of the sine digital sequences to be 0;
a digital-to-analog converter: the digital sequence generating module is connected with the digital sequence generating module and is used for converting the two sinusoidal digital sequences into two step-type waveforms respectively;
an amplitude controller: and the digital-to-analog converter is connected and used for respectively adjusting the signal amplitudes of the two step-type waveforms so as to enable subsequent equipment to calculate the phase difference.
Furthermore, the device also comprises a low-pass filter which is respectively connected with the digital-to-analog converter and the amplitude controller and is used for filtering the step-type waveform and filtering out the components outside the required frequency band.
Further, the device further comprises a second DDS system, which is the same as the first DDS system, and is used for calculating the phase again by taking the frequency of the step-like waveform after the signal amplitude is adjusted as the frequency of a second reference clock when the parameter of the step-like waveform after the signal amplitude is adjusted does not reach the set condition.
Further, the reference clock frequency is an integer multiple of the second reference clock frequency, and the second reference clock frequency is an integer multiple of the second stepped-waveform frequency.
The invention also discloses a computer readable storage medium having instructions stored therein, which when run on a computer, cause the computer to perform the above method.
The invention also discloses an electronic device, which comprises a memory and a processor, wherein the memory stores a computer program, and the program is executed by the processor to enable the processor to execute the method.
The invention has the following beneficial effects:
the technical scheme of the invention has the advantages that the standard phase is generated based on the DDS principle, the phase transformation is continuous, the frequency stability is high, the control is easy, the high resolution and the accuracy of the output phase are ensured, and the determination and the recurrence of the phase difference value are further ensured.
Drawings
The following describes embodiments of the present invention in further detail with reference to the accompanying drawings;
FIG. 1 is a flow chart of a DDS-based standard phase generation method according to the present invention;
FIG. 2 is a schematic diagram of a DDS-based standard phase generator according to the present invention;
FIG. 3 is a flow chart of the algorithm associated with the DDS based standard phase generation method of the present invention;
fig. 4 is a schematic structural diagram of a terminal device or a server system for implementing the embodiment of the present invention.
Detailed Description
In order to more clearly illustrate the invention, the invention is further described below with reference to preferred embodiments and the accompanying drawings. Similar parts in the figures are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and is not to be taken as limiting the scope of the invention.
As shown in fig. 1, the present invention discloses a DDS-based standard phase generating method, which includes:
and S1, calculating a frequency control word, an amplitude control word and a phase control word according to the reference clock frequency.
According to the desired output frequency foutAnd phase
Separately calculating a frequency control word k and a phase control word p, setting fcFor reference clock frequency, N is the number of sampling points in each signal period, and N is the number of bits in the phase accumulator, the output frequency foutIs composed of
Output phase
Is composed of
Selecting a suitable reference clock frequency fcThe number of sampling points N and the frequency control word k are integers.
And S2, generating a sine digital sequence with fixed frequency, amplitude and phase according to the frequency control word, the amplitude control word and the phase control word.
And respectively writing the frequency control word k and the phase control word p into a digital sequence generation module, wherein the digital sequence generation module generates a sinusoidal digital sequence with fixed frequency, amplitude and phase with the parameters.
The phase accumulator output bits N are not all used for addressing, but are truncated to m bits;
when the frequency control word k is greater than 2mThe phase resolution is 2 pi/2m(ii) a And when the frequency control word k is not more than 2mThe phase resolution is 2 pi/N, i.e., (k.2 pi)/2n。
And S3, converting the sine digital sequence into a step-type waveform.
The digital signal sequence is converted into an analog signal, which is represented by a staircase-type waveform.
And S4, adjusting the signal amplitude of the step-type waveform and calculating the phase.
And placing the amplitude controller in proper attenuation and amplification gears according to the amplitude control words, and adjusting the amplitude of the output signal.
In addition, in order to improve the accuracy, a filtering process is added after step S3, the step-shaped waveform is smoothed by a low-pass filter, and the spectral components outside the desired frequency band are filtered.
Preferably, the reference clock frequency should satisfy the nyquist theorem, i.e. at least 2 times greater than the output frequency of the DDS system, to avoid aliasing or harmonics falling within the output frequency band.
If the method cannot achieve the required high resolution, a DDS system cascade mode is adopted, and the output of a previous DDS system is used as a reference clock and connected to a next DDS system. According to the frequency f of the output signal of the second stage DDS system2Sequentially determining the frequency f of the first stage DDS output signal1And a first stage DDS system reference clock frequency fcThe sampling point number and the frequency control word of the two-stage DDS system are both integers;
specifically, as shown in FIG. 3, let k be1And k2Frequency control words p of the first-stage DDS system and the second-stage DDS system respectively1And p2Phase control words, n, for first and second DDS systems, respectively1And n2The number of bits is respectively the number of bits of the first-stage DDS system phase accumulator and the second-stage DDS system phase accumulator;
first stage DDS system output frequency f1Is composed of
First stage DDS system signal phase
Is composed of
The signal delay delta T after the first DDS system1Is composed of
Second stage DDS system output frequency f2Is composed of
Second stage DDS system signal phase
Is composed of
Output phase shift after second stage DDS system
Is composed of
First stage DDS System reference clock frequency fcSecond stage DDS system reference clock frequency (first stage DDS system output signal frequency f)1) And its output signal frequency f2Satisfy a multiple relationship, i.e., fc/f1And f1/f2The number of sampling points and the frequency control word of the two-stage DDS system are both integers. At this time, the process of the present invention,
will be subdivided into smaller phase increments and thus first order phases
After passing through the second stage DDS, the phase is finely adjusted, and the second stage phase
And the phase is coarsely adjusted.
The number of the DDS systems can be 1 or more, the DDS systems are added according to actual needs, and corresponding frequency control words and phase control words are respectively written into digital sequence generating modules of the DDS systems at all levels when the DDS systems are used. The standard phase generated after being filtered by a plurality of DDS systems has continuous phase transformation, high frequency stability and easy control, and simultaneously ensures the high resolution and accuracy of the output phase, thereby ensuring the determination and recurrence of the phase difference value.
As shown in fig. 2, another embodiment of the present invention further discloses a DDS-based standard phase generating apparatus, which includes a first DDS system, where the first DDS system is divided into two paths, and includes:
the timing controller 9: the device comprises a frequency control word, an amplitude control word and a phase control word, wherein the frequency control word, the amplitude control word and the phase control word are calculated according to the frequency of a reference clock, input into a digital sequence generation module and input into an amplitude control module;
number sequence generation modules 1, 2: generating a sine digital sequence with fixed frequency, amplitude and phase according to the frequency control word, the amplitude control word and the phase control word; the input phase of the digital sequence generation module 1 is a reference phase 0 °, that is, the input phase control word is 0, the input phase control word of the digital sequence generation module 2 is a phase control word calculated by the timing controller 9, and the upper path and the lower path have a phase difference due to the difference of the initially input phase control words, which results in the final output waveform.
The digital sequence generation module can adopt a phase/amplitude conversion mode and a waveform storage direct-reading mode, and the generation mechanism is as follows: the phase amplitude conversion mode is to read digital waveform by phase addressing; the waveform storage direct-reading mode is to introduce the needed waveform into the memory at one time and read the waveform in real time by a system clock.
Digital-to-analog converters 3, 4: the digital sequence generating module is connected with the digital sequence generating module and is used for converting the sinusoidal digital sequence into a step-type waveform; the digital-to-analog converter 3 is connected with the digital sequence generation module 1, and the digital-to-analog converter 4 is connected with the digital sequence generation module 2.
Low-pass filters 5, 6: smoothing the step-type waveform, and filtering out frequency spectrum components outside a required frequency band; the low-pass filter 5 is connected to the digital-to-analog converter 3, and the low-pass filter 6 is connected to the digital-to-analog converter 4.
The device also comprises a second DDS system which is the same as the first DDS system and is used for calculating the phase difference again by taking the frequency of the step-shaped waveform after the signal amplitude is adjusted as the frequency of a second reference clock when the parameter of the step-shaped waveform after the signal amplitude is adjusted does not reach the set condition until the phase difference meets the standard.
Another embodiment of the present invention provides a server, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the computer program, the server implements the above method for aggregating learning data in an online classroom. As shown in fig. 4, a computer system suitable for implementing the server provided in the present embodiment includes a Central Processing Unit (CPU) that can perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM) or a program loaded from a storage section into a Random Access Memory (RAM). In the RAM, various programs and data necessary for the operation of the computer system are also stored. The CPU, ROM, and RAM are connected thereto via a bus. An input/output (I/O) interface is also connected to the bus.
An input section including a keyboard, a mouse, and the like; an output section including a speaker and the like such as a Liquid Crystal Display (LCD); a storage section including a hard disk and the like; and a communication section including a network interface card such as a LAN card, a modem, or the like. The communication section performs communication processing via a network such as the internet. The drive is also connected to the I/O interface as needed. A removable medium such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is mounted on the drive as necessary, so that a computer program read out therefrom is mounted into the storage section as necessary.
In particular, it is mentioned that the processes described in the above flowcharts can be implemented as computer software programs according to the present embodiment. For example, the present embodiments include a computer program product comprising a computer program tangibly embodied on a computer-readable medium, the computer program comprising program code for performing the method illustrated in the flow chart. In such an embodiment, the computer program may be downloaded and installed from a network via the communication section, and/or installed from a removable medium.
The flowchart and schematic diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to the present embodiments. In this regard, each block in the flowchart or schematic diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the schematic and/or flowchart illustration, and combinations of blocks in the schematic and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
On the other hand, the present embodiment also provides a nonvolatile computer storage medium, which may be the nonvolatile computer storage medium included in the apparatus in the foregoing embodiment, or may be a nonvolatile computer storage medium that exists separately and is not assembled into a terminal. The non-volatile computer storage medium stores one or more programs that, when executed by a device, cause the device to: calculating a frequency control word, an amplitude control word and a phase control word according to the reference clock frequency; generating a sine digital sequence with fixed frequency, amplitude and phase according to the frequency control word, the amplitude control word and the phase control word; converting the sinusoidal digital sequence into a step-like waveform; and adjusting the signal amplitude of the step-type waveform, and calculating the phase.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (devices) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It should be understood that the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention, and it will be obvious to those skilled in the art that other variations or modifications may be made on the basis of the above description, and all embodiments may not be exhaustive, and all obvious variations or modifications may be included within the scope of the present invention.
Claims (6)
1. A DDS-based standard phase generation method is characterized by comprising the following steps:
s1, calculating a frequency control word, an amplitude control word and a phase control word according to the reference clock frequency;
s2, respectively generating two sine digital sequences with fixed frequency, amplitude and phase according to the frequency control word, the amplitude control word and the phase control word obtained by calculation, and setting the phase control word of one of the sine digital sequences to be 0;
s3, converting the two sine digital sequences into two step-type waveforms respectively;
s4, adjusting the signal amplitudes of the two step waveforms respectively, calculating the phase difference, wherein the reference clock frequency is more than 2 times of the DDS system output frequency;
the amplitude controller is arranged in a proper attenuation and amplification gear according to the amplitude control word, and the amplitude of the output signal is adjusted;
when the step-type waveform parameters after the signal amplitude is adjusted do not reach the set conditions, taking the step-type waveform frequency after the signal amplitude is adjusted as a second reference clock frequency, and executing the method of the steps S1-S4 again to obtain a second step-type waveform;
the reference clock frequency is an integer multiple of the second reference clock frequency, and the second reference clock frequency is an integer multiple of the second stepped waveform frequency.
2. The method of claim 1, further comprising: in step S3, the step waveform is filtered to remove components outside the required frequency band.
3. A DDS based standard phase generating apparatus, comprising a first DDS system, the first DDS system comprising:
a time schedule controller: the DDS system comprises a DDS system, a frequency control word, an amplitude control word and a phase control word, wherein the DDS system is used for generating a digital sequence according to the frequency of a reference clock, and the frequency control word, the amplitude control word and the phase control word are input into a digital sequence generation module, wherein the frequency of the reference clock is 2 times greater than the output frequency of the DDS system;
a number sequence generation module: the device is used for respectively generating two sine digital sequences with fixed frequency, amplitude and phase according to the frequency control word, the amplitude control word and the phase control word which are obtained by calculation, and setting the phase control word of one of the sine digital sequences to be 0;
a digital-to-analog converter: the digital sequence generating module is connected with the digital sequence generating module and is used for converting the two sinusoidal digital sequences into two step-shaped waveforms respectively and inputting amplitude control words into the amplitude control module;
the amplitude controller is arranged in a proper attenuation and amplification gear according to the amplitude control word, and the amplitude of the output signal is adjusted;
an amplitude controller: the digital-to-analog converter is connected and used for respectively adjusting the signal amplitudes of the two step-type waveforms so as to enable subsequent equipment to calculate the phase difference;
the device also comprises a second DDS system which is the same as the first DDS system and is used for taking the step-shaped waveform frequency after the signal amplitude is adjusted as the reference clock frequency of the second DDS system, namely the second reference clock frequency, when the step-shaped waveform parameter after the signal amplitude is adjusted does not reach the set condition, obtaining the second step-shaped waveform frequency through the second DDS system, and calculating the phase difference again;
the reference clock frequency of the first DDS system is an integral multiple of the second reference clock frequency, and the second reference clock frequency is an integral multiple of the second stepped waveform frequency.
4. The apparatus of claim 3, further comprising a low pass filter respectively connected to the digital-to-analog converter and the amplitude controller for filtering the stepped waveform to remove components outside a desired frequency band.
5. A computer-readable storage medium having instructions stored thereon, which when run on a computer, cause the computer to perform the method of any one of claims 1-2.
6. An electronic device, comprising a memory and a processor, the memory having stored thereon a computer program that, when executed by the processor, causes the processor to perform the method of any of claims 1-2.
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