CN108010849A - The production method of three-dimensional field-effect tube based on silicon substrate - Google Patents
The production method of three-dimensional field-effect tube based on silicon substrate Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 53
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 53
- 239000010703 silicon Substances 0.000 title claims abstract description 53
- 239000000758 substrate Substances 0.000 title claims abstract description 53
- 230000005669 field effect Effects 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 38
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 38
- 238000005530 etching Methods 0.000 claims abstract description 37
- 238000000034 method Methods 0.000 claims abstract description 32
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
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Abstract
本发明提供了一种基于硅衬底的三维场效应管的制作方法,包括:在硅衬底表面形成绝缘层,其中所述绝缘层覆盖鳍部结构;对所述绝缘层进行减薄,以使所述鳍部结构的主体露出所述绝缘层;在所述鳍部结构的主体表面形成氮化硅层,所述氮化硅层覆盖所述鳍部结构的主体表面并且覆盖所述绝缘层;对所述氮化硅层进行刻蚀,以去除所述绝缘层表面的氮化硅;对所述绝缘层进行刻蚀,以去除所述氮化硅层下方的绝缘层并使所述鳍部结构与所述绝缘层交界的部分暴露出来;对所述鳍部结构与所述绝缘层交界的部分进行刻蚀,以在所述鳍部结构形成悬空的沟道区域;在所述鳍部结构的沟道区域表面形成栅氧化层。
The invention provides a method for manufacturing a three-dimensional field effect transistor based on a silicon substrate, comprising: forming an insulating layer on the surface of the silicon substrate, wherein the insulating layer covers the fin structure; thinning the insulating layer to Exposing the main body of the fin structure to the insulating layer; forming a silicon nitride layer on the main body surface of the fin structure, the silicon nitride layer covering the main body surface of the fin structure and covering the insulating layer ; Etching the silicon nitride layer to remove the silicon nitride on the surface of the insulating layer; etching the insulating layer to remove the insulating layer below the silicon nitride layer and make the fin The part of the junction between the fin structure and the insulating layer is exposed; the part of the junction between the fin structure and the insulating layer is etched to form a suspended channel region in the fin structure; A gate oxide layer is formed on the surface of the channel region of the structure.
Description
【技术领域】【Technical field】
本发明涉及半导体芯片制造技术领域,特别地,涉及一种基于硅衬底的三维场效应管的制作方法。The invention relates to the technical field of semiconductor chip manufacturing, in particular to a method for manufacturing a three-dimensional field effect transistor based on a silicon substrate.
【背景技术】【Background technique】
鳍式场效应晶体管(FinFET)是一种具有鳍型沟道结构的三维场效应晶体管。在鳍式场效应晶体管中,硅衬底表面覆盖有氧化层(Oxide),而鳍部(Fin)垂直地形成在硅衬底表面,并且,鳍部底部会嵌入到氧化层内部。其中,鳍部作为沟道,栅极(Gate)通过覆盖在鳍部表面来控制沟道。A Fin Field Effect Transistor (FinFET) is a three-dimensional field effect transistor with a fin-shaped channel structure. In the fin field effect transistor, the surface of the silicon substrate is covered with an oxide layer (Oxide), and the fin (Fin) is vertically formed on the surface of the silicon substrate, and the bottom of the fin is embedded in the oxide layer. Wherein, the fin serves as a channel, and the gate (Gate) controls the channel by covering the surface of the fin.
由于栅极是形成在氧化层上方的,因此嵌入到氧化层的鳍部底部实际上受到栅极的控制会比较弱,因此在此区域容易造成源漏间漏电等问题。基于上述问题,业界的常规做法是采用SOI(Silicon on Insulator,绝缘体上硅)材料制作三维场效应管,SOI基底包括背衬底(Si)、形成在所述背衬底表面的绝缘氧化埋层(Buried Oxide,BOX)以及形成在所述绝缘氧化埋层表面的顶层硅(Si),其中,三维场效应管的鳍部直接制作在顶层硅,不存在鳍部底部嵌入到氧化层的结构,因此可以避免上述源漏间的漏电问题。但是,采用SOI基底作为制作三维场效应管的成本比采用硅衬底要高很多。Since the gate is formed above the oxide layer, the bottom of the fin embedded in the oxide layer is actually less controlled by the gate, so problems such as leakage between source and drain are likely to occur in this area. Based on the above problems, the conventional practice in the industry is to use SOI (Silicon on Insulator, silicon on insulator) materials to make three-dimensional field effect transistors. The SOI substrate includes a back substrate (Si), and an insulating buried oxide layer formed on the surface of the back substrate. (Buried Oxide, BOX) and the top layer of silicon (Si) formed on the surface of the insulating buried oxide layer, wherein the fins of the three-dimensional field effect transistor are directly fabricated on the top layer of silicon, and there is no structure in which the bottom of the fin is embedded in the oxide layer, Therefore, the above-mentioned leakage problem between the source and the drain can be avoided. However, the cost of using an SOI substrate as a three-dimensional field effect transistor is much higher than that of using a silicon substrate.
有鉴于此,有必要提供一种基于硅衬底的三维场效应管的制作方法,以解决现有技术存在的上述问题。In view of this, it is necessary to provide a method for manufacturing a three-dimensional field effect transistor based on a silicon substrate, so as to solve the above-mentioned problems existing in the prior art.
【发明内容】【Content of invention】
本发明的其中一个目的在于为解决上述问题而提供一种基于硅衬底的三维场效应管的制作方法。One object of the present invention is to provide a method for manufacturing a three-dimensional field effect transistor based on a silicon substrate in order to solve the above problems.
本发明提供的基于硅衬底的三维场效应管的制作方法,包括:在硅衬底表面形成绝缘层,其中所述绝缘层覆盖鳍部结构;对所述绝缘层进行减薄,以使所述鳍部结构的主体露出所述绝缘层;在所述鳍部结构的主体表面形成氮化硅层,所述氮化硅层覆盖所述鳍部结构的主体表面并且覆盖所述绝缘层;对所述氮化硅层进行刻蚀,以去除所述绝缘层表面的氮化硅;对所述绝缘层进行刻蚀,以去除所述氮化硅层下方的绝缘层并使所述鳍部结构与所述绝缘层交界的部分暴露出来;对所述鳍部结构与所述绝缘层交界的部分进行刻蚀,以在所述鳍部结构形成悬空的沟道区域;在所述鳍部结构的沟道区域表面形成栅氧化层。The method for manufacturing a three-dimensional field effect transistor based on a silicon substrate provided by the present invention includes: forming an insulating layer on the surface of a silicon substrate, wherein the insulating layer covers the fin structure; thinning the insulating layer so that the The main body of the fin structure exposes the insulating layer; a silicon nitride layer is formed on the main body surface of the fin structure, and the silicon nitride layer covers the main body surface of the fin structure and covers the insulating layer; Etching the silicon nitride layer to remove silicon nitride on the surface of the insulating layer; etching the insulating layer to remove the insulating layer below the silicon nitride layer and make the fin structure Exposing the part bordering the insulating layer; etching the part bordering the fin structure and the insulating layer, so as to form a suspended channel region in the fin structure; A gate oxide layer is formed on the surface of the channel region.
作为在本发明提供的基于硅衬底的三维场效应管的制作方法的一种改进,在一种优选实施例中,还包括:在所述栅氧化层表面形成栅极电极层,所述栅极电极层和所述栅氧化层环绕所述鳍部结构悬空的沟道区域,形成一个环栅结构。As an improvement of the silicon substrate-based three-dimensional field effect transistor manufacturing method provided in the present invention, in a preferred embodiment, it also includes: forming a gate electrode layer on the surface of the gate oxide layer, and the gate The pole electrode layer and the gate oxide layer surround the suspended channel region of the fin structure to form a ring gate structure.
作为在本发明提供的基于硅衬底的三维场效应管的制作方法的一种改进,在一种优选实施例中,还包括:在所述栅氧化层形成之前,去除所述鳍部结构表面覆盖的氮化硅层。As an improvement of the silicon substrate-based three-dimensional field effect transistor manufacturing method provided by the present invention, in a preferred embodiment, it also includes: before the gate oxide layer is formed, removing the surface of the fin structure covered by a silicon nitride layer.
作为在本发明提供的基于硅衬底的三维场效应管的制作方法的一种改进,在一种优选实施例中,还包括:提供硅衬底,并在所述硅衬底刻蚀出垂直于所述硅衬底表面的鳍部结构,所述鳍部结构定义有所述三维场效应管的源区和漏区。As an improvement of the silicon substrate-based three-dimensional field effect transistor manufacturing method provided in the present invention, in a preferred embodiment, it also includes: providing a silicon substrate, and etching a vertical A fin structure on the surface of the silicon substrate, the fin structure defines a source region and a drain region of the three-dimensional field effect transistor.
作为在本发明提供的基于硅衬底的三维场效应管的制作方法的一种改进,在一种优选实施例中,所述绝缘层的减薄采用各向同性的刻蚀方式,其中所述绝缘层经过减薄之后,所述鳍部结构的主体会露出所述绝缘层,而所述鳍部结构的底部嵌入在所述绝缘层之中。As an improvement of the manufacturing method of the silicon substrate-based three-dimensional field effect transistor provided in the present invention, in a preferred embodiment, the thinning of the insulating layer adopts an isotropic etching method, wherein the After the insulating layer is thinned, the main body of the fin structure exposes the insulating layer, and the bottom of the fin structure is embedded in the insulating layer.
作为在本发明提供的基于硅衬底的三维场效应管的制作方法的一种改进,在一种优选实施例中,所述绝缘层为二氧化硅层。As an improvement of the method for manufacturing a three-dimensional field effect transistor based on a silicon substrate provided in the present invention, in a preferred embodiment, the insulating layer is a silicon dioxide layer.
作为在本发明提供的基于硅衬底的三维场效应管的制作方法的一种改进,在一种优选实施例中,所述氮化硅层的刻蚀采用各向异性的刻蚀方式。As an improvement to the method for manufacturing a three-dimensional field effect transistor based on a silicon substrate provided in the present invention, in a preferred embodiment, the etching of the silicon nitride layer adopts an anisotropic etching method.
作为在本发明提供的基于硅衬底的三维场效应管的制作方法的一种改进,在一种优选实施例中,所述绝缘层的刻蚀采用各向同性的刻蚀方式。As an improvement of the manufacturing method of the silicon substrate-based three-dimensional field effect transistor provided by the present invention, in a preferred embodiment, the etching of the insulating layer adopts an isotropic etching method.
作为在本发明提供的基于硅衬底的三维场效应管的制作方法的一种改进,在一种优选实施例中,经过所述各向同性刻蚀之后,覆盖在所述硅衬底表面的绝缘层的厚度剩余量大于0.01um。As an improvement of the silicon substrate-based three-dimensional field effect transistor manufacturing method provided by the present invention, in a preferred embodiment, after the isotropic etching, the The remaining thickness of the insulating layer is greater than 0.01um.
作为在本发明提供的基于硅衬底的三维场效应管的制作方法的一种改进,在一种优选实施例中,所述鳍部结构与所述绝缘层交界的部分通过各向同性的方式进行刻蚀;在所述鳍部结构与所述绝缘层交界的部分刻蚀完成之后形成一个开口,所述开口的上方的鳍部结构悬空并作为所述鳍部结构的沟道区域。As an improvement of the silicon substrate-based three-dimensional field effect transistor manufacturing method provided by the present invention, in a preferred embodiment, the part where the fin structure and the insulating layer are connected isotropically Etching is performed; an opening is formed after the part of the junction between the fin structure and the insulating layer is etched, and the fin structure above the opening is suspended and serves as a channel region of the fin structure.
相较于现有技术,本申请提供的基于硅衬底的三维场效应管的制作方法通过优化硅基底的三维场效应管的栅极结构和制造流程,将鳍部底部与绝缘层交界处的区域刻蚀穿,然后制作环形栅极的结构,从而使得栅极能彻底控制源漏之间的电流,解决栅极对此部分区域源漏间电流的控制能力弱的问题,有效解决源漏间的漏电问题。Compared with the prior art, the manufacturing method of the three-dimensional field effect transistor based on the silicon substrate provided by the present application optimizes the gate structure and the manufacturing process of the three-dimensional field effect transistor on the silicon substrate, and optimizes the junction between the bottom of the fin and the insulating layer. The area is etched through, and then the structure of the ring gate is made, so that the gate can completely control the current between the source and the drain, and solve the problem that the gate has a weak ability to control the current between the source and the drain in this part of the area, and effectively solve the problem between the source and the drain. leakage problem.
【附图说明】【Description of drawings】
为了更清楚地说明本发明实施例中的技术方案,下面将对实施例描述中所使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其它的附图,其三维场效应管中:In order to illustrate the technical solutions in the embodiments of the present invention more clearly, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For Those of ordinary skill in the art can also obtain other drawings based on these drawings without paying creative work. Among the three-dimensional field effect tubes:
图1为本发明提供的基于硅衬底的的制作方法一种实施例的流程示意图;Fig. 1 is a schematic flow diagram of an embodiment of a silicon substrate-based manufacturing method provided by the present invention;
图2~图10为图1所示的基于硅衬底的三维场效应管的制作方法各个工艺步骤的示意图。2 to 10 are schematic diagrams of various process steps of the manufacturing method of the three-dimensional field effect transistor based on the silicon substrate shown in FIG. 1 .
【具体实施方式】【Detailed ways】
下面将对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅是本发明的一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例,都属于本发明保护的范围。The following will clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
为解决现有技术基于硅衬底的三维场效应管的源漏间存在的漏电问题,本申请提供的基于硅衬底的三维场效应管的制作方法通过优化硅基底的三维场效应管的栅极结构和制造流程,将鳍部底部与绝缘层交界处的区域刻蚀穿,然后制作环形栅极的结构,从而使得栅极能彻底控制源漏之间的电流,解决栅极对此部分区域源漏间电流的控制能力弱的问题,有效解决源漏间的漏电问题。In order to solve the leakage problem existing between the source and drain of the three-dimensional field effect transistor based on the silicon substrate in the prior art, the manufacturing method of the three-dimensional field effect transistor based on the silicon substrate provided by the application optimizes the gate of the three-dimensional field effect transistor on the silicon substrate Electrode structure and manufacturing process, etch through the area at the junction of the bottom of the fin and the insulating layer, and then make a ring-shaped gate structure, so that the gate can completely control the current between the source and drain, and solve the problem of the part of the gate. The problem of weak control ability of the current between the source and the drain can effectively solve the problem of the leakage between the source and the drain.
请参阅图1,其为本发明提供的基于硅衬底的三维场效应管的制作方法一种实施例的流程示意图。具体地,所述基于硅衬底的三维场效应管的制作方法主要包括以下步骤:Please refer to FIG. 1 , which is a schematic flowchart of an embodiment of a method for manufacturing a three-dimensional field effect transistor based on a silicon substrate provided by the present invention. Specifically, the method for manufacturing a three-dimensional field effect transistor based on a silicon substrate mainly includes the following steps:
步骤S1,在硅衬底形成鳍部结构;Step S1, forming a fin structure on the silicon substrate;
请参阅图2,在步骤S1中,首先提供一个硅衬底,并对所述硅衬底进行刻蚀处理,以在所述硅衬底刻蚀出鳍部结构,其中,所述鳍部结构垂直于所述硅衬底的表面。并且,所述鳍部结构定义有所述三维场效应管的源区和漏区。Please refer to FIG. 2. In step S1, a silicon substrate is provided first, and the silicon substrate is etched to etch a fin structure on the silicon substrate, wherein the fin structure perpendicular to the surface of the silicon substrate. Moreover, the fin structure defines a source region and a drain region of the three-dimensional field effect transistor.
步骤S2,在所述硅衬底表面形成绝缘层,其中所述绝缘层覆盖所述鳍部结构;Step S2, forming an insulating layer on the surface of the silicon substrate, wherein the insulating layer covers the fin structure;
请参与图3,所述绝缘层可以为二氧化硅层,具体地,在步骤S2中,所述绝缘层可以通过化学气相淀积的方式生长在所述硅衬底表面,且所述绝缘层形成之后除了覆盖所述硅衬底表面以外,还会整体覆盖所述鳍部结构。Please refer to Figure 3, the insulating layer may be a silicon dioxide layer, specifically, in step S2, the insulating layer may be grown on the surface of the silicon substrate by chemical vapor deposition, and the insulating layer After forming, in addition to covering the surface of the silicon substrate, the entire fin structure will be covered.
步骤S3,对所述绝缘层进行减薄,以使所述鳍部结构的主体露出所述绝缘层,其中所述鳍部结构的底部嵌入在所述绝缘层;Step S3, thinning the insulating layer so that the main body of the fin structure exposes the insulating layer, wherein the bottom of the fin structure is embedded in the insulating layer;
请参阅图4,在步骤S3中,可以通过各向同性的方式对所述绝缘层进行刻蚀以实现所述绝缘层的减薄化,所述绝缘层减薄化之后,所述鳍部结构的主体露出所述绝缘层,而所述鳍部结构的底部依旧会所嵌入在所述绝缘层之中。Please refer to FIG. 4. In step S3, the insulating layer may be etched isotropically to achieve thinning of the insulating layer. After the insulating layer is thinned, the fin structure The main body of the fin structure exposes the insulating layer, while the bottom of the fin structure is still embedded in the insulating layer.
步骤S4,在所述鳍部结构的主体表面形成氮化硅层,所述氮化硅层覆盖所述鳍部结构的主体表面并且覆盖所述绝缘层;Step S4, forming a silicon nitride layer on the main body surface of the fin structure, the silicon nitride layer covering the main body surface of the fin structure and covering the insulating layer;
请参阅图5,在步骤S4中,在所述鳍部结构的主体露出所述绝缘层之后,可以通过氮化硅生长工艺在所述鳍部结构的主体表面形成氮化硅层。在具体实施例中,所述氮化硅层可以是在温度为600~1200℃的条件下,经过30~300分钟的时间生长得到。作为一种优选的实施例,所述氮化硅层的厚度可以为0.001~0.02um。在所述氮化硅层形成之后,如图5所示,所述氮化硅层一方面覆盖在所述鳍部结构的主体表面,且另一方面还会覆盖所述绝缘层。Referring to FIG. 5 , in step S4 , after the main body of the fin structure exposes the insulating layer, a silicon nitride layer may be formed on the surface of the main body of the fin structure through a silicon nitride growth process. In a specific embodiment, the silicon nitride layer may be grown at a temperature of 600-1200° C. for 30-300 minutes. As a preferred embodiment, the thickness of the silicon nitride layer may be 0.001-0.02um. After the silicon nitride layer is formed, as shown in FIG. 5 , the silicon nitride layer covers the main body surface of the fin structure on the one hand, and also covers the insulating layer on the other hand.
步骤S5,对所述氮化硅层进行刻蚀,以去除所述绝缘层表面的氮化硅;Step S5, etching the silicon nitride layer to remove the silicon nitride on the surface of the insulating layer;
请参阅图6,具体地,在步骤S5中,所述氮化硅层的刻蚀可以采用各向异性的刻蚀方式,所述氮化硅层进行各向异性刻蚀之后,所述绝缘层表面的氮化硅层会被去除掉;在此同时,所述鳍部结构上方的氮化硅层也被刻蚀掉,因此所述鳍部结构上方的氮化硅层跟所述鳍部结构的表面齐平。Please refer to FIG. 6, specifically, in step S5, the etching of the silicon nitride layer may adopt an anisotropic etching method, and after the anisotropic etching of the silicon nitride layer, the insulating layer The silicon nitride layer on the surface will be removed; at the same time, the silicon nitride layer above the fin structure is also etched away, so the silicon nitride layer above the fin structure and the fin structure surface flush.
步骤S6,对所述绝缘层进行刻蚀,以去除所述氮化硅层下方的绝缘层并使所述鳍部结构与所述绝缘层交界的部分暴露出来;Step S6, etching the insulating layer, so as to remove the insulating layer under the silicon nitride layer and expose the part of the junction between the fin structure and the insulating layer;
请参阅图7,具体地,在步骤S6中,所述绝缘层的刻蚀可以采用各向同性的刻蚀方式。在各向同性刻蚀过程中,所述绝缘层会被进一步减薄,因此所述氮化硅层下方的绝缘层会被去除掉,另一方面,上述区域的绝缘层被去除掉之后,所述鳍部结构与所述绝缘层交接的部分会暴露出来。所述各向同性刻蚀量的要求是在经过刻蚀之后,覆盖在所述硅衬底表面的绝缘层的厚度剩余量大于0.01um。Referring to FIG. 7 , specifically, in step S6 , the insulating layer may be etched in an isotropic etching manner. During the isotropic etching process, the insulating layer will be further thinned, so the insulating layer under the silicon nitride layer will be removed. On the other hand, after the insulating layer in the above region is removed, the The portion where the fin structure meets the insulating layer is exposed. The requirement for the isotropic etching amount is that after etching, the remaining thickness of the insulating layer covering the surface of the silicon substrate is greater than 0.01 um.
步骤S7,对所述鳍部结构与所述绝缘层交界的部分进行刻蚀,以在所述鳍部结构形成悬空的沟道区域;Step S7, etching the part where the fin structure is at the junction with the insulating layer, so as to form a suspended channel region in the fin structure;
具体地,请参阅图8,在所述鳍部结构与所述绝缘层交界的部分暴露出来之后,可以通过各向同性的方式对此部分的鳍部结构进行刻蚀,刻蚀量的要求是需要此部分的鳍部结构可以被刻蚀穿。因此,在所述鳍部结构与所述绝缘层交界的部分刻蚀完成之后,所述鳍部结构在上述区域便可以形成一个开口,所述开口的上方即形成一个悬空部,所述悬空部可以作为所述鳍部结构的沟道区域,即步骤S7可以在所述鳍部结构形成一个悬空的沟道区域。另一方面,采用各向同性刻蚀过程中,所述鳍部结构顶部的硅材料可会被部分刻蚀,如图8所示。Specifically, referring to FIG. 8, after the part of the junction between the fin structure and the insulating layer is exposed, this part of the fin structure can be etched in an isotropic manner, and the etching amount is required to be Fin structures requiring this portion can be etched through. Therefore, after the etching of the part of the junction between the fin structure and the insulating layer is completed, the fin structure can form an opening in the above-mentioned region, and a floating portion is formed above the opening, and the floating portion It may be used as the channel region of the fin structure, that is, step S7 may form a suspended channel region in the fin structure. On the other hand, in the isotropic etching process, the silicon material on the top of the fin structure may be partially etched, as shown in FIG. 8 .
步骤S8,去除所述鳍部结构表面覆盖的氮化硅层,并在所述鳍部结构的沟道区域表面形成栅氧化层;Step S8, removing the silicon nitride layer covering the surface of the fin structure, and forming a gate oxide layer on the surface of the channel region of the fin structure;
具体地,在步骤S8中,请参阅图9,首先,可以通过腐蚀的方式去除掉所述鳍部结构表面覆盖的氮化硅层,从而使得所述鳍部结构的硅材料暴露出来。接着,利用氧化层生长工艺在所述鳍部结构的沟道区域表面形成栅氧化层,所述栅氧化层可以为二氧化硅层,其具体可以是在温度为600~1200℃的条件下生长得到。作为一种优选的实施例,所述栅氧化层的厚度可以为0.001~0.01um。所述栅氧化层形成之后,将包围所述鳍部结构的沟道区域。需要注意的是,在本实施例中,所述栅氧化层的厚度小于所述开口的深度。Specifically, in step S8 , referring to FIG. 9 , firstly, the silicon nitride layer covering the surface of the fin structure may be removed by etching, so that the silicon material of the fin structure is exposed. Next, a gate oxide layer is formed on the surface of the channel region of the fin structure by using an oxide layer growth process. The gate oxide layer may be a silicon dioxide layer, which may specifically be grown at a temperature of 600-1200° C. get. As a preferred embodiment, the gate oxide layer may have a thickness of 0.001-0.01um. After the gate oxide layer is formed, it will surround the channel region of the fin structure. It should be noted that, in this embodiment, the thickness of the gate oxide layer is smaller than the depth of the opening.
步骤S9,在所述栅氧化层表面形成栅极电极层。Step S9, forming a gate electrode layer on the surface of the gate oxide layer.
具体地,请参阅图10,在所述栅氧化层形成之后,可以进一步在所述栅氧化层表面形成栅极电极层,所述栅极电极层可以采用多晶硅材料。所述栅极电极层除了覆盖所述栅氧化表面以外,还会填充到所述开口,从而形成一个环栅结构。也即是说,采用上述实施例提供的基于硅衬底的三维场效应管的制作方法制作的三维场效应管具有一个环栅结构,因此所述鳍部结构的沟道区域底部也是会有栅极包围的,因此不会嵌入到所述绝缘层之中。Specifically, referring to FIG. 10 , after the gate oxide layer is formed, a gate electrode layer may be further formed on the surface of the gate oxide layer, and the gate electrode layer may be made of polysilicon material. In addition to covering the gate oxide surface, the gate electrode layer also fills the opening, thereby forming a gate-around structure. That is to say, the three-dimensional field effect transistor manufactured by the silicon substrate-based three-dimensional field effect transistor manufacturing method provided in the above embodiment has a ring-gate structure, so the bottom of the channel region of the fin structure also has a gate extremely surrounded and therefore not embedded in the insulating layer.
相较于现有技术,本申请提供的基于硅衬底的三维场效应管的制作方法通过优化硅基底的三维场效应管的栅极结构和制造流程,将鳍部底部与绝缘层交界处的区域刻蚀穿,然后制作环形栅极的结构,从而使得栅极能彻底控制源漏之间的电流,解决栅极对此部分区域源漏间电流的控制能力弱的问题,有效解决源漏间的漏电问题。Compared with the prior art, the manufacturing method of the three-dimensional field effect transistor based on the silicon substrate provided by the present application optimizes the gate structure and the manufacturing process of the three-dimensional field effect transistor on the silicon substrate, and optimizes the junction between the bottom of the fin and the insulating layer. The area is etched through, and then the structure of the ring gate is made, so that the gate can completely control the current between the source and the drain, and solve the problem that the gate has a weak ability to control the current between the source and the drain in this part of the area, and effectively solve the problem between the source and the drain. leakage problem.
以上所述的仅是本发明的实施方式,在此应当指出,对于本领域的普通技术人员来说,在不脱离本发明创造构思的前提下,还可以做出改进,但这些均属于本发明的保护范围。What has been described above is only the embodiment of the present invention. It should be pointed out that for those of ordinary skill in the art, improvements can be made without departing from the creative concept of the present invention, but these all belong to the present invention. scope of protection.
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US20150364543A1 (en) * | 2014-06-11 | 2015-12-17 | International Business Machines Corporation | Silicon nanowire formation in replacement metal gate process |
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