CN105097549A - Method for manufacturing gate-all-around structure - Google Patents

Abstract

The invention provides a method for manufacturing a fully-enclosed gate structure. Firstly, an interlayer dielectric layer flush with the top of the fin body is formed. After etching back the interlayer dielectric layer for the first time, a three-enclosed gate structure with different etching ratios is formed. The protective layer is used to protect the exposed fin body of the channel region by three surrounds. After etching back the interlayer dielectric layer for the second time, the exposed fin body of the channel region is etched again to make the trench protected by the three surround protective layer The fin body in the channel region is suspended in the air, thereby obtaining a fully-enclosed gate structure. In the etching process for the suspension, the three-surrounding protection layer well protects the three surfaces of the fin body in the channel region to be suspended, avoiding unnecessary defects on the surface of the suspension channel, so the technical solution of the present invention The process is simple, reliable and low in cost, and can improve device performance.

Description

A method of manufacturing a fully enclosed gate structure

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a method for manufacturing a fully enclosed gate structure.

Background technique

The semiconductor integrated circuit (IC) industry has undergone rapid development. During the development of ICs, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest device or interconnect line that can be made using a fabrication process) has decreased. The advantages of this scaled-down process are increased production efficiency and reduced associated costs. At the same time, this scaled-down process also increases the complexity of handling and manufacturing ICs.

In the process of seeking higher device density, higher performance, and lower cost, as the integrated circuit process continues to develop to the nanotechnology process node, some manufacturers have begun to consider how to move from planar CMOS transistors to three-dimensional fin field The transition problem of the effect transistor (FinFET) device structure. Compared with planar transistors, FinFET devices reduce short-channel effects due to improved control of the channel. Manufacturing and design challenges drive the development of FinFET devices. At present, FinFET has appeared in the application of 20nm technology generation. While existing FinFET devices and methods of fabricating FinFET devices have generally served their intended purpose, not all aspects have been completely satisfactory.

A FinFET device is a multi-gate MOS device. According to the number of gates, FinFETs can be divided into double-gate FinFETs, triple-gate FinFETs, and gate-all-around FinFETs that can be controlled from all sides. Wherein, the double-gate FinFET has two gates, which are respectively located on both sides of the fin body (Fin), and can independently control the channel current of the fin body. In practical applications, dual-gate FinFETs are often used in core logic circuits that require low leakage current. Tri-gate FinFETs have three gates, one on each side of the fin body and one on top of the fin body. The gate and Fin (fin) are isolated from the substrate by the insulating layer below them. Some of the Fin structures of the tri-gate FinFET are formed on SOI (Silicon On Insulator, silicon on insulator), and some are obtained directly from the silicon substrate. The advantage of the tri-gate FinFET is that since the three sides of the fin body are controlled by the gate, it can better control the carriers in the active region than the traditional MOS structure and provide a larger drive current, thus improving device performance. The currently widely used FinFET devices are basically tri-gate FinFETs controlled by three sides.

With the continuous higher requirements for device performance, a gate-all-around structure controlled by four sides (Gate-all-around, please refer to Figure 1) has emerged. Semiconductor devices with a gate-all-around structure have the special performance of effectively limiting the short channel effect, which is exactly what the industry is extremely eager for in the innovation of continuously reducing the size of devices following Moore's law. The device channel formed by the thin silicon film in the all-around gate structure is surrounded by the gate of the device and controlled only by the gate. In addition, the influence of the leakage field is also removed, so the short-channel effect of the device is effectively limited. Since the silicon film constituting the device channel and the bottom substrate need to be suspended eventually, the manufacturing process of the fully surrounded gate device is also relatively complicated.

Please refer to FIGS. 1A and 1B , a method for forming a fully-enclosed gate structure in the prior art, including:

First, as shown in FIG. 1A, an oxide layer and a silicon layer are formed on a semiconductor substrate, and the oxide layer and the silicon layer are etched to form a channel region fin body and a channel region oxide layer;

Next, as shown in FIG. 1B , the channel region oxide layer is removed, so that the remaining channel region fins are suspended above the semiconductor substrate;

Then, an all-enclosed gate structure enclosing the fins in the suspended channel region is formed.

However, in the above-mentioned existing fully-enclosed gate structure formation process, the process is relatively complicated, and multi-layer masks and photoresists must be used, and when the oxide layer in the channel region is removed, the influence on the fin body in the channel region is relatively large. It will increase its defects, easily lead to device failure, and the carriers will also be affected by excessive stress.

Therefore, how to provide a simple, reliable, and low-cost manufacturing method of the fully-enclosed gate structure and ensure device performance is one of the technical problems to be solved urgently by those skilled in the art.

Contents of the invention

The object of the present invention is to provide a method for manufacturing a gate-enclosed structure, which can simplify the process, reduce the cost, and reduce the defects of the floating channel.

In order to solve the above problems, the present invention proposes a method for manufacturing a gate-all-around structure, which includes the following steps:

Provide a semiconductor substrate formed with a fin body, a channel region is formed in the fin body, and an interlayer dielectric layer flush with the top of the fin body is formed on the surface of the semiconductor substrate;

Etching back the interlayer dielectric layer for the first time to expose the fin body in the channel region with a certain height;

Forming a three-surrounding protective layer surrounding the top and sidewall surfaces of the exposed channel region fin body, the three-surrounding protective layer only covers part of the surface of the interlayer dielectric layer around the fin body, and the etching ratio is the same as that of the channel region Both the fin body and the interlayer dielectric layer are different;

Etching back the interlayer dielectric layer for the second time to expose the fin body in the channel region with a certain height again;

Etching the re-exposed fins in the channel region, so that the fins in the channel region surrounded by the three protective layers are completely suspended or partially suspended, so as to obtain a suspended channel;

An all-around gate structure that fully surrounds the exposed surface of the suspended channel is formed.

Further, the interlayer dielectric layer is silicon oxide, silicon nitride or silicon oxynitride.

Further, the depth of the first etch-back of the interlayer dielectric layer is no less than 5 nm.

Further, the three-surrounding protection layer is a silicon germanium layer or a silicon carbon layer, which is formed by an epitaxial growth process.

Further, the thickness of the three surrounding protective layers is not less than

Further, the depth of the second etch-back of the interlayer dielectric layer is no less than 5 nm.

Further, dry etching or wet etching is used to etch the re-exposed fin body in the channel region, and the etchant used in the wet etching is an etchant with crystal orientation selectivity.

Further, after etching the re-exposed fin body in the channel region, after the fin body in the channel region surrounded by the three-surrounding protective layer is completely suspended or partially suspended, the three-surrounding protective layer is removed to obtain a suspended trench road.

After etching the re-exposed fin body in the channel region, multiple areas at the bottom of the fin body in the channel region surrounded by the three protective layers are suspended to obtain a plurality of suspended channels.

Further, the step of providing a semiconductor substrate formed with fins includes:

providing a silicon substrate, etching the silicon substrate to form fins standing on the surface of the substrate;

Ion doping of the source region, ion doping of the drain region and ion doping of the channel region are respectively performed on the fin body to form the source region, the drain region and the channel region.

Compared with the prior art, the manufacturing method of the fully-enclosed gate structure provided by the present invention firstly forms an interlayer dielectric layer flush with the top of the fin body, and after etching back the interlayer dielectric layer for the first time, an etched The three-surround protection layer with different etch ratios is used to perform three-enclose protection on the exposed channel region fin body, and after the second etching back of the interlayer dielectric layer, the exposed channel region fin body is etched again so that the three The fin body in the channel region protected by the protective layer is suspended, so as to obtain a fully surrounded gate structure. In the etching process for the suspension, the three-surrounding protection layer well protects the three surfaces of the fin body in the channel region to be suspended, avoiding unnecessary defects on the surface of the suspension channel, so the technical solution of the present invention The process is simple, reliable and low in cost, and can improve device performance.

Description of drawings

1A to 1B are schematic cross-sectional device structure diagrams of a method for forming a fully surrounded gate structure in the prior art;

FIG. 2 is a flowchart of a manufacturing method of a fully-enclosed gate structure according to a specific embodiment of the present invention;

3A to 3F are schematic cross-sectional structure diagrams of devices in the method shown in FIG. 2 .

detailed description

In order to make the purpose and features of the present invention more obvious and understandable, the specific implementation of the present invention will be further described below in conjunction with the accompanying drawings. However, the present invention can be implemented in different forms and should not be limited to the described embodiments.

The present invention proposes a method for manufacturing an all-enclosed gate structure, which includes the following steps:

S1, providing a semiconductor substrate formed with a fin body, a channel region is formed in the fin body, and an interlayer dielectric layer flush with the top of the fin body is formed on the surface of the semiconductor substrate;

S2, etching back the interlayer dielectric layer for the first time, so as to expose the fin body in the channel region with a certain height;

S3, forming a three-surrounding protective layer surrounding the exposed top and sidewall surfaces of the fin body in the channel region, the three-surrounding protective layer only covers part of the surface of the interlayer dielectric layer around the fin body, and the etching ratio is the same as that of the trench The fins in the channel area and the interlayer dielectric layer are different;

S4, etching back the interlayer dielectric layer for the second time, so as to expose the fin body in the channel region with a certain height again;

S5, etching the re-exposed fin body in the channel region, so that the fin body in the channel region surrounded by the three surrounding protective layers is completely suspended or partially suspended, so as to obtain a suspended channel;

S6, forming a fully-enclosed gate structure fully enclosing the exposed surface of the suspended channel.

Please refer to FIG. 3A, the semiconductor substrate 300 provided in step S1 can be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a silicon-germanium substrate, etc., please use a photolithography process to coat the photoresist , exposure and development, patterning the silicon layer on the top layer of the semiconductor substrate 300, and etching to form a fin body (Fin) 301 structure, the shape can be processed into strips, strips or rectangular blocks, the fin body The height is 10nm-1000nm, and the width is 5nm-50nm. Further, ion doping in the source region, ion doping in the drain region and ion doping in the channel region are performed on the silicon of the fin body 301 to form a source region, a drain region and a channel between the source and drain regions in the fin body In addition, only the channel region of the fin body can be doped with ions to form a channel region. The source/drain regions of this device are formed in the semiconductor substrate 300 on both sides of the fin body. Since the fully surrounding gate structure to be formed is formed at the position of the channel region of the fin body, the channel region of the fin body is referred to as “channel region fin body” for convenience of description below.

Please continue to refer to 3A. In step S1, an interlayer dielectric layer 302 is first formed on the entire surface of the semiconductor substrate including the fin body by chemical vapor deposition. The interlayer dielectric layer can be silicon oxide, silicon nitride, nitrogen Materials such as silicon oxide or tetraethyl orthosilicate (TEOS), the etch ratio is different from that of the fin body silicon; then, the redundant interlayer dielectric layer 302 above the fin body 301 is removed by chemical mechanical polishing (CMP), so that the interlayer The top of the dielectric layer 302 is flush with the top of the fin body.

Please refer to FIG. 3B. In step S2, the interlayer dielectric layer 302 is etched back (ie, the first etch back) using a dry etching process to expose the channel region fins of a certain height (H1). Body 301a, the depth of etch back depends on the height of the suspended channel to be formed, that is, the height of the fin body 301a in the channel region, preferably, the depth of the first etching back of the interlayer dielectric layer is not less than 5nm, Thus, the height of the fin body 301 a in the channel region is not less than 5 nm. The specific process parameters of the dry etching are: the etching gas includes CF ₄ , CHF ₃ and Ar, the flow rate of CHF ₃ is 50 sccm-200 sccm, the flow rate of CF ₄ is 30 sccm-50 sccm, the flow rate of Ar is 50 sccm-100 sccm, the cavity The chamber pressure is 0mTorr~5mTorr, the source power RF power is 200W~1000W, and the bias power RF power is 100W~500W.

Please refer to FIG. 3C, in step S3, three surrounding protective layers 303 are formed on the side and top surfaces (three surfaces) of the exposed channel region fin body 301a, and the three surrounding protective layers 303 may be the opposite interlayer dielectric layer 302 and silicon, any material with a relatively large etching selectivity ratio, so that the etching protects the surrounding area in the subsequent etching back of the interlayer dielectric layer 302 and etching of the fin body silicon to form a dangling channel. Channel region fin body 301a. It can be deposited by chemical vapor deposition and etched, and can also be formed by epitaxial growth. Preferably, the silicon in the channel region fin body 301a exposed by the first etching back is used as the seed layer, and a layer of silicon germanium (SiGe) or silicon carbon is epitaxy on the exposed surface of the channel region fin body through an epitaxial growth process. Layer (SiC) is used as the three-surrounding protection layer 303 of the fin body silicon 301a in the channel region exposed again by subsequent etching, and its thickness is not less than

Please refer to FIG. 3D. In step S4, the interlayer dielectric layer 302 is etched back (that is, etched back for the second time) by dry etching process again, so as to expose the channel region fin with a certain height (H2) again. For the body 301b, the etch-back depth depends on the suspension height of the suspended channel to be formed. Preferably, the depth of the second etch-back of the interlayer dielectric layer is not less than 5 nm. The specific process parameters of the dry etching are: the etching gas includes CF ₄ , CHF ₃ and Ar, the flow rate of CHF ₃ is 50 sccm-200 sccm, the flow rate of CF ₄ is 30 sccm-50 sccm, the flow rate of Ar is 50 sccm-100 sccm, the cavity The chamber pressure is 0mTorr~5mTorr, the source power RF power is 200W~1000W, and the bias power RF power is 100W~500W. Preferably, the depth of the interlayer dielectric layer is etched back for the second time is not less than 5 nm, so that the suspension height of the suspension channel meets the process requirement.

Please refer to FIG. 3E , in step S5, dry etching or wet etching is used to etch the channel region fin body 301b exposed again, so that the channel region fin body surrounded by the protective layer 303 The body 301a is completely suspended or partially suspended. When using wet etching, the selected etchant is an etchant with orientation selectivity, such as TMAH (tetramethylammonium hydroxide). If it is necessary to simultaneously form a plurality of suspended channels on a strip-shaped fin body 301, in this step, the channel region fins in multiple positions at the bottom of the channel region fin body 301a surrounded by the protective layer 303 can be The body 301b is etched to make a plurality of areas at the bottom of the channel region fin body 301a suspended, so as to obtain a plurality of suspended channels.

Please refer to FIG. 3F. In step S6, when the three-surrounding protective layer 303 is SiGe or SiC or a material that can be used as a gate dielectric layer, according to the requirements of device performance on the channel, after forming the floating channel, it can be selectively removed. Alternatively, it may be retained, and the suspended channel after removing the three surrounding protective layers may be a linear structure, a strip structure, or a rectangular block structure. However, when the three-surrounding protection layer 303 is made of other materials that do not meet the requirements of the device, it must be removed. The three surrounding protection layers 303 can be removed by dry etching or wet etching. In this embodiment, a fully surrounded gate dielectric layer 304 and a gate layer 305 are formed on the surface of the suspended channel from which the three surrounding protective layers have been removed, thereby obtaining a fully surrounded gate structure. The fully surrounded gate structure may be a polysilicon gate structure or a high-K metal gate structure. The gate dielectric layer 304 of the polysilicon gate structure can be formed by a thermal oxidation process, and the polysilicon gate layer can be formed by depositing polysilicon by LPCVD process and patterning the deposited polysilicon. The LPCVD process can make the polysilicon even under the suspended silicon lines. Good filling. Specifically, the process conditions for forming the polysilicon layer include: the reaction gas is silane (SiH ₄ ), and the flow rate of the silane may range from 100 sccm to 200 sccm, such as 120 sccm; the temperature range in the reaction chamber may range from 700°C to 800°C; The pressure in the reaction chamber can be 100mTorr-300mTorr; the carrier gas is helium (He) or nitrogen, and the flow range can be 5sccmr-20sccm. The gate dielectric layer of the high-K metal gate structure is hafnium oxide, aluminum oxide, tantalum pentoxide or zirconia, or doped with Si, Al, N, La , Ta and other elements made of high-K materials. The method of forming the high-K gate dielectric layer may be a physical vapor deposition process or an atomic layer deposition process. The metal gate is formed by depositing a plurality of thin film stacks through a sputtering deposition process, and the thin film includes a work function metal layer, a barrier layer and conductive layer. The barrier layer includes TaN, TiN, TaC, TaSiN, WN, TiAl, TiAlN or a combination thereof. Non-limiting examples of such barrier layer deposition methods include chemical vapor deposition (CVD), such as low temperature chemical vapor deposition (LTCVD), low pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (LTCVD), plasma chemical vapor deposition (PECVD).

To sum up, in the manufacturing method of the fully-enclosed gate structure provided by the present invention, an interlayer dielectric layer flush with the top of the fin body is formed first, and after the first etching back of the interlayer dielectric layer, an etching ratio is formed. Different three-surrounding protection layers are used to perform three-surrounding protection on the exposed channel region fin body. After the second etch back to the interlayer dielectric layer, the exposed channel region fin body is etched again to make the three-surrounding protection The fin body in the channel region protected by the layer is suspended, thereby obtaining a fully-enclosed gate structure. In the etching process for the suspension, the three-surrounding protection layer well protects the three surfaces of the fin body in the channel region to be suspended, avoiding unnecessary defects on the surface of the suspension channel, so the technical solution of the present invention The process is simple, reliable and low in cost, and can improve device performance.

Obviously, those skilled in the art can make various changes and modifications to the invention without departing from the spirit and scope of the invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these modifications and variations.

Claims (10)

1. a manufacture method for all-around-gate structure, is characterized in that, comprises the following steps:

The Semiconductor substrate being formed with fin body is provided, in described fin body, forms channel region, form the interlayer dielectric layer flushed with fin body top at described semiconductor substrate surface;

First time returns the described interlayer dielectric layer of etching, to expose the channel region fin body of certain altitude;

Form top and the sidewall surfaces of surrounding the channel region fin body exposed three surround protective layer, and described three surround protective layer only covers fin body peripheral part interlayer dielectric layer on the surface, and etching ratio is all different with interlayer dielectric layer from channel region fin body;

Second time returns the described interlayer dielectric layer of etching, again to expose the channel region fin body of certain altitude;

Etch the described channel region fin body again exposed, the channel region fin body that three encirclement protective layers are surrounded is completely unsettled or part is unsettled, to obtain unsettled raceway groove;

Form the full all-around-gate electrode structure surrounding unsettled raceway groove exposed surface.

2. the manufacture method of all-around-gate structure as claimed in claim 1, it is characterized in that, described interlayer dielectric layer is silica, silicon nitride or silicon oxynitride.

3. the manufacture method of all-around-gate structure as claimed in claim 1, is characterized in that, the degree of depth that first time returns the described interlayer dielectric layer of etching is not less than 5nm.

4. the manufacture method of all-around-gate structure as claimed in claim 1, is characterized in that, described three encirclement protective layers are germanium silicon layer or carbon silicon layer, adopt epitaxial growth technology to be formed.

5. the manufacture method of all-around-gate structure as claimed in claim 1, is characterized in that, described three thickness surrounding protective layer are not less than

6. the manufacture method of all-around-gate structure as claimed in claim 1, is characterized in that, the degree of depth that second time returns the described interlayer dielectric layer of etching is not less than 5nm.

7. the manufacture method of all-around-gate structure as claimed in claim 1, is characterized in that, adopt dry etching or wet etching to etch the described channel region fin body again exposed, the etching agent of described wet etching is for there being crystal orientation optionally etching agent.

8. the manufacture method of all-around-gate structure as claimed in claim 1; it is characterized in that; the described channel region fin body again exposed is etched; after the completely unsettled or part of channel region fin body that three encirclement protective layers are surrounded is unsettled; remove described three and surround protective layer, to obtain unsettled raceway groove.

9. the manufacture method of all-around-gate structure as claimed in claim 1; it is characterized in that; after etching the described channel region fin body again exposed, the multiple regions bottom the channel region fin body that three encirclement protective layers are surrounded are unsettled, to obtain multiple unsettled raceway groove.

10. the manufacture method of all-around-gate structure as claimed in claim 1, is characterized in that, provide the step of the Semiconductor substrate being formed with fin body to comprise:

There is provided silicon base, the fin body of substrate surface is stood in etch silicon substrate to be formed;

Source region ion doping, drain region ion doping and channel region ion doping are carried out respectively to described fin body, to form source region, drain region and channel region.