CN108009436B - Multi-user management method and system of SOC chip and SOC chip - Google Patents
Multi-user management method and system of SOC chip and SOC chip Download PDFInfo
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Abstract
The invention discloses a multi-user management method and a multi-user management system of an SOC chip and the SOC chip, wherein the multi-user management method comprises the following steps: presetting a general table for storing all user address space information and sub-tables which correspond to users one by one and are used for storing user authority control information, and automatically loading the information stored in the general table and the sub-tables when an SOC chip is powered on; writing the address space information of all users into a general table so that the users can determine the address space of code operation according to the general table; and writing the authority control information of the user into a sub-table corresponding to the user so that the user can manage the own authority control information according to the sub-table. According to the method and the device, the pre-stored information of the general table and the sub-table is automatically loaded when the SOC chip is powered on, a user can directly determine the address space of code operation according to the address space information stored in the general table, the complexity of a hardware circuit is reduced, the overhead is reduced, the management right of the user is given to the user, and the safety and the independence of multi-user management are guaranteed.
Description
Technical Field
The invention relates to the technical field of chip development, in particular to a multi-user management method and system of an SOC chip and the SOC chip.
Background
The electronic product is gradually developed to a stage of taking a highly integrated System-on-a-Chip (SOC) Chip as a core through a stage of taking a transistor as a core and a stage of taking a single Chip microcomputer as a core, that is, the electronic product mainly takes functions required by each part by one SOC Chip. In order to design an SOC chip integrating the advantages of various technologies, the situation of multi-user joint development is necessarily involved, and in the joint development, the biggest problem of the SOC chip is multi-user management, namely how to ensure the equality, safety and easy maintenance of SOC chip users.
In the prior art, multi-user management of an SOC chip is realized, and a common method is to design a super user, where only the super user has authority to modify configuration information of the user. After the SOC chip is powered on and started, the super user configures registers of all users to plan the address and authority configuration of the users. When configuring the address information of each user, in order to avoid address overlapping, the addresses of multiple users need to be compared one by one, which results in a complex hardware circuit and a high cost. In addition, a super user is designed to plan the authority configuration of the user, extra trusted management is needed to ensure that the super user can be absolutely trusted by other common users, and most users prefer to select the super user to manage the authority configuration information of the super user.
Therefore, how to provide a solution to the above technical problems is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide a multi-user management method and a multi-user management system of an SOC chip and the SOC chip, wherein the pre-stored information of a general table and a sub-table is automatically loaded when the SOC chip is electrified, and a user can directly determine the address space of code operation of the user according to the address space information stored in the general table, so that the complexity of a hardware circuit is reduced, the expenditure is reduced, the management right of the user is given to the user, and the safety and the independence of multi-user management are ensured.
In order to solve the technical problem, the invention provides a multi-user management method of an SOC chip, which comprises the following steps:
presetting a general table for storing all user address space information and sub-tables which correspond to the users one by one and are used for storing the user authority control information, and automatically loading the information stored in the general table and the sub-tables when the SOC chip is powered on;
writing the address space information of all the users into the summary table so that the users can determine the address space of code operation according to the summary table;
and writing the authority control information of the user into the sub-table corresponding to the user so that the user can manage the own authority control information according to the sub-table.
Preferably, the process of writing the address space information of all the users into the summary table specifically includes:
all the users negotiate to determine the address space of respective code operation;
and writing the address space information of all the users into the general table according to the negotiation result.
Preferably, after writing the address space information of all the users into the summary table according to the negotiation result, the method further includes:
confirming whether the address space information stored in the summary table is correct;
if yes, locking the summary table according to a first locking instruction of the user so as to prevent address space information stored in the summary table from being modified;
if not, rewriting until the address space information stored in the summary table is completely correct.
Preferably, the process of locking the summary table according to the first locking instruction of the user specifically includes:
and when a first locking instruction of the user is received, matching the key words of the summary table locking enable to lock the summary table.
Preferably, after writing the authority control information of the user into the sub-table corresponding to the user, the method further includes:
determining whether the code of the user is no longer debugged and is released;
if not, continuing debugging the code until the release is confirmed;
and if the sub-table is not debugged and issued any more, locking the sub-table corresponding to the user according to a second locking instruction of the user so as to avoid modifying the authority control information stored in the sub-table.
Preferably, the process of locking the sub-table according to the second locking instruction of the user specifically includes:
and when a second locking instruction of the user is received, matching the key words of the sub-table locking enabling to lock the sub-table.
Preferably, the storage locations of the total table and the sub-table are programmable nonvolatile memories.
Preferably, the memory is an embedded flash memory EFLASH.
In order to solve the above technical problem, the present invention further provides a multi-user management system of an SOC chip, including:
the setting unit is used for presetting a general table for storing all the user address space information and sub-tables which correspond to the users one by one and are used for storing the user authority control information, and the information stored by the general table and the sub-tables is automatically loaded when the SOC chip is electrified;
a summary table writing unit, configured to write address space information of all the users into the summary table, so that the users determine an address space in which their codes operate according to the summary table;
and the sub-table writing unit is used for writing the authority control information of the user into the sub-table corresponding to the user so that the user can manage the own authority control information according to the sub-table.
In order to solve the technical problem, the invention also provides an SOC chip, which comprises the multi-user management system of the SOC chip.
The invention provides a multi-user management method of an SOC chip, which comprises the following steps: presetting a general table for storing all user address space information and sub-tables which correspond to users one by one and are used for storing user authority control information, and automatically loading the information stored in the general table and the sub-tables when an SOC chip is powered on; writing the address space information of all users into a general table so that the users can determine the address space of code operation according to the general table; and writing the authority control information of the user into a sub-table corresponding to the user so that the user can manage the own authority control information according to the sub-table.
Compared with the configuration information of the super user management user in the prior art, the information pre-stored in the general table and the sub table is automatically loaded when the SOC chip is powered on. The user can directly determine the address space of the code operation according to the address space information stored in the general table, address overlapping can be avoided without comparing the addresses of the users one by one, and the complexity of a hardware circuit is reduced, so that the expenditure is reduced, and the production cost is reduced. In addition, the user can manage the authority control information of the user according to the sub-table, the super user is removed, the management right of the user is given to the user, and the safety and the independence of multi-user management are guaranteed.
The invention also provides a multi-user management system of the SOC chip and the SOC chip, and the multi-user management system and the SOC chip have the same beneficial effects as the method.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a process flow diagram of a multi-user management method for an SOC chip according to the present invention;
FIG. 2 is a schematic structural diagram of a multi-user management system of an SOC chip according to the present invention;
fig. 3 is a schematic structural diagram of another multi-user management system of an SOC chip according to the present invention.
Detailed Description
The core of the invention is to provide a multi-user management method and system of an SOC chip and the SOC chip, the SOC chip automatically loads pre-stored information of a general table and a sub table when being electrified, a user can directly determine the address space of code operation of the user according to the address space information stored in the general table, the complexity of a hardware circuit is reduced, the expenditure is reduced, the management right of the user is given to the user, and the safety and the independence of multi-user management are ensured.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a process flow diagram of a multi-user management method for an SOC chip according to the present invention, the method includes:
step S11: presetting a general table for storing all user address space information and sub-tables which correspond to users one by one and are used for storing user authority control information, and automatically loading the information stored in the general table and the sub-tables when an SOC chip is powered on;
specifically, multi-user management is implemented in the SOC chip, and how to allocate addresses of users, set permissions of the users, and ensure security of user configuration needs to be solved. If any link of user management is vulnerable, the security between users can be made to be virtual. For example, user a has tampered with user B's address information. Or the user A tampers the authority setting of the user B to open the authority setting of the user B completely, and the core data of the user B is unprotected. Based on the method, a general table and a sub-table are preset and are respectively used for storing address space information of all users and authority control information of all users.
Specifically, the configuration management information (address space information and permission control information) of each user is automatically loaded from the configuration information area based on hardware power-on, please refer to fig. 2, fig. 2 is a schematic structural diagram of a multi-user management system of an SOC chip provided by the present invention, address space information of all users stored in a general table is loaded when an address register of the SOC chip is powered on, permission control information of each user stored in each sub-table is loaded when a control register is powered on, and it is avoided that a super user configures a register of each user to plan address and permission configuration of the user.
Step S12: writing the address space information of all users into a general table so that the users can determine the address space of code operation according to the general table;
specifically, in the present application, address space information of each user is placed in the general table, and if a user address is placed in the user sub-table, the address cannot be uniformly managed, for example, an error occurs in address information configured by the user a, which may cause that the whole chip cannot be used. And the general table is used for storing the predetermined address space for the respective code operation of the user, and when the address information configured by the user A is wrong, other users of the chip can still normally use the address information. In addition, the address space information stored in the general table of the application is predetermined and does not need dynamic allocation, so that the addresses of a plurality of users do not need to be compared one by one in order to avoid address overlapping, a complex hardware circuit for comparison is not needed, the overhead of the hardware circuit is greatly reduced, the competitiveness of a product is improved, and meanwhile, the high-cohesion low-coupling principle of the system is also met.
Step S13: and writing the authority control information of the user into a sub-table corresponding to the user so that the user can manage the own authority control information according to the sub-table.
Specifically, the management right of the user is given to the user by presetting the sub-table, so that the user can independently and autonomously manage without relying on a super user, and the management safety and independence are improved.
It should be further noted that the control module during the operation of the SOC chip is an implementation body of multi-user management during the operation of the system. The control module is mounted between a Central Processing Unit (CPU) and a bus, and has a main function of controlling whether to intercept a request on the bus based on user identity information and user authority information, for example, a user a sends a request for reading a user B without reading the authority of the user B. At this point, the control module intercepts the read request and reports an exception to the system.
The invention provides a multi-user management method of an SOC chip, which comprises the following steps: presetting a general table for storing all user address space information and sub-tables which correspond to users one by one and are used for storing user authority control information, and automatically loading the information stored in the general table and the sub-tables when an SOC chip is powered on; writing the address space information of all users into a general table so that the users can determine the address space of code operation according to the general table; and writing the authority control information of the user into a sub-table corresponding to the user so that the user can manage the own authority control information according to the sub-table.
Compared with the configuration information of the super user management user in the prior art, the information pre-stored in the general table and the sub table is automatically loaded when the SOC chip is powered on. The user can directly determine the address space of the code operation according to the address space information stored in the general table, address overlapping can be avoided without comparing the addresses of the users one by one, and the complexity of a hardware circuit is reduced, so that the expenditure is reduced, and the production cost is reduced. In addition, the user can manage the authority control information of the user according to the sub-table, the super user is removed, the management right of the user is given to the user, and the safety and the independence of multi-user management are guaranteed.
On the basis of the above-described embodiment:
as a preferred embodiment, the process of writing the address space information of all users into the summary table specifically includes:
all users negotiate to determine the address space of respective code operation;
and writing the address space information of all users into a summary table according to the negotiation result.
Specifically, the address space information of the user written into the summary table in the present application is negotiated by each user in advance according to actual conditions, and the information stored in the summary table is automatically loaded according to a certain logic when the SOC chip is powered on, so that the user can directly determine the address space of the code of the user and download the code to the negotiated address space. Specifically, the negotiation may be performed for each user according to an address space in which the respective code runs, and the address space of each user is determined, respectively, such as a high address and a low address of the user a, and a high address and a low address of the user B. The negotiation may be performed once or multiple times, and the present application is not particularly limited herein.
As a preferred embodiment, after writing the address space information of all users into the summary table according to the negotiation result, the method further comprises:
confirming whether the address space information stored in the summary table is correct;
if yes, locking the summary table according to a first locking instruction of a user so as to prevent address space information stored in the summary table from being modified;
if not, rewriting until the address space information stored in the summary table is completely correct.
Specifically, after address space information of all users is written into the summary table according to a negotiation result, whether the address space information stored in the summary table is correct or not is also confirmed, and when the address space information stored in the summary table is incorrect, the address space information stored in the summary table is rewritten, and the summary table is locked until the address space information stored in the summary table is completely correct. After the summary table is locked, the address space information stored in the summary table is permanently not modifiable, so that the situation that the address space information stored in the summary table is wrongly written after the summary table is locked can be avoided, irreversible significant economic loss is avoided, and effective guarantee is provided for ensuring that the actual address space information stored in the summary table is consistent with the negotiation result of each user.
As a preferred embodiment, the process of locking the summary table according to the first locking instruction of the user specifically includes:
and when a first locking instruction of a user is received, matching keywords of the summary table locking enable to realize locking of the summary table.
Specifically, in order to enable the summary table not to be tampered and improve safety, a locking function is designed, and more specifically, when each user confirms that address space information written in the summary table is correct and does not change any more and selects to lock the summary table, a first locking instruction is sent to match keywords of the summary table locking enabling, and the summary table locking is achieved. That is, if the key word of the lock enable is matched, the writing operation to the summary table will fail, and the summary table will not be changed. Normally, the locked match word is also in this summary table, so a logic of auto-lock is formed.
As a preferred embodiment, after writing the authority control information of the user into the sub-table corresponding to the user, the method further includes:
confirming whether the code of the user is not debugged any more and is issued or not;
if not, continuing debugging the code until the release is confirmed;
and if the sub-table is not debugged and issued any more, locking the sub-table corresponding to the user according to a second locking instruction of the user so as to avoid the permission control information stored in the sub-table from being modified.
Specifically, after the user downloads the code to the negotiated address space, debugs the code, and writes the authority control information into the corresponding sub-table, the user can select whether to lock the sub-table or not under the condition that the chip is considered to be issuable. On one hand, after locking, the code cannot be debugged, and the authority control information cannot be changed, so that the management safety is ensured. On the other hand, because the code and the authority control information can be changed at will before locking, in the process of product development, if a user needs to modify the configuration information, the chip does not need to be re-modified, the development period is shortened, the cost is reduced, and compared with the method of directly solidifying the configuration information into the chip, the method has certain flexibility and is easy to maintain.
As a preferred embodiment, the process of locking the sub-table according to the second lock instruction of the user specifically includes:
and when a second locking instruction of the user is received, matching keywords of the locking enabling of the sub-table to realize locking of the sub-table.
Specifically, in order to prevent the sub-table from being tampered and improve the safety, the locking function is designed, and the locking function is handed to each user to be managed, so that the safety and the independence of user management are guaranteed. More specifically, when the user confirms that the sub-table is not modified any more and the chip can issue, the second locking instruction is sent to match with the key words of the locking enable of the sub-table, so that the sub-table is locked. That is, if the locked enabled keywords are matched, the writing operation to the sub-table fails, and the sub-table cannot be changed, so that the situations that the user A tampers with the permission setting of the user B to open the user B completely and the core data of the user B is not protected are avoided, the information of each user is not stolen, and the information safety is improved. Normally, the locked match word is also in this sub-table, so that a logic of auto-locking is formed.
In a preferred embodiment, the storage locations of the general table and the sub-table are programmable nonvolatile memories.
Specifically, in order to avoid the fact that information stored in the main table and the sub-table is lost after power failure, the storage positions of the main table and the sub-table are programmable nonvolatile memories, and the memories have nonvolatile functions, so that the reliability of the chip is improved, and the use experience of a user is improved.
In a preferred embodiment, the memory is an embedded flash memory EFLASH.
Specifically, when the multi-user management of the SOC chip is applied to an Embedded application scenario, the memory of the application may be an eflas (Embedded Flash), and the eflas has the advantages of no loss in power down, support of write operation, and resistance to erasing and writing, and has a lower cost, thereby reducing the cost of the chip and improving the competitiveness of the product.
Referring to fig. 3, fig. 3 is a schematic structural diagram of another multi-user management system of an SOC chip according to the present invention, the system includes:
the system comprises a setting unit 1, a control unit and a control unit, wherein the setting unit 1 is used for presetting a general table for storing all user address space information and sub tables which correspond to users one by one and are used for storing user authority control information, and the information stored by the general table and the sub tables is automatically loaded when an SOC chip is electrified;
the summary table writing unit 2 is used for writing the address space information of all users into the summary table so that the users can determine the address space of code operation according to the summary table;
and the sub-table writing unit 3 is used for writing the authority control information of the user into the sub-table corresponding to the user, so that the user can manage the authority control information of the user according to the sub-table.
For the introduction of the system provided by the present invention, please refer to the above method embodiment, and the present invention is not described herein again.
The invention also provides an SOC chip, which comprises the multi-user management system of the SOC chip.
For the introduction of the SOC chip provided by the present invention, reference is made to the above system embodiments, and the present invention is not repeated herein.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
1. A multi-user management method of an SOC chip is characterized by comprising the following steps:
presetting a general table for storing all user address space information and sub-tables which correspond to users one by one and are used for storing user authority control information, and automatically loading the information stored by the general table and the sub-tables when an SOC chip is powered on;
writing the address space information of all the users into the summary table so that the users can determine the address space of code operation according to the summary table;
writing the authority control information of the user into the sub-table corresponding to the user so that the user can manage the own authority control information according to the sub-table;
the process of writing the address space information of all the users into the summary table specifically includes:
all the users negotiate to determine the address space of respective code operation;
and writing the address space information of all the users into the general table according to the negotiation result.
2. The method of claim 1, wherein after writing address space information of all the users into the summary table according to the negotiation result, the method further comprises:
confirming whether the address space information stored in the summary table is correct;
if yes, locking the summary table according to a first locking instruction of the user so as to prevent address space information stored in the summary table from being modified;
if not, rewriting until the address space information stored in the summary table is completely correct.
3. The method according to claim 2, wherein the process of locking the summary table according to the first locking instruction of the user is specifically:
and when a first locking instruction of the user is received, matching the key words of the summary table locking enable to lock the summary table.
4. The method of claim 1, wherein after writing the entitlement control information for the user into the sub-table corresponding to the user, the method further comprises:
determining whether the code of the user is no longer debugged and is released;
if not, continuing debugging the code until the release is confirmed;
and if the sub-table is not debugged and issued any more, locking the sub-table corresponding to the user according to a second locking instruction of the user so as to avoid modifying the authority control information stored in the sub-table.
5. The method according to claim 4, wherein the locking the sub-table according to the second locking instruction of the user specifically comprises:
and when a second locking instruction of the user is received, matching the key words of the sub-table locking enabling to lock the sub-table.
6. The method of any of claims 1-5, wherein the storage locations of the total table and the sub-tables are programmable non-volatile memory.
7. The method of claim 6, wherein the memory is an embedded flash memory EFLASH.
8. A multi-user management system for an SOC chip, comprising:
the setting unit is used for presetting a general table for storing all the user address space information and sub-tables which correspond to the users one by one and are used for storing the user authority control information, and the information stored by the general table and the sub-tables is automatically loaded when the SOC chip is electrified;
a summary table writing unit, configured to write address space information of all the users into the summary table, so that the users determine an address space in which their codes operate according to the summary table;
a sub-table writing unit, configured to write the authority control information of the user into the sub-table corresponding to the user, so that the user manages the authority control information of the user according to the sub-table;
the process of writing the address space information of all the users into the summary table specifically includes:
all the users negotiate to determine the address space of respective code operation;
and writing the address space information of all the users into the general table according to the negotiation result.
9. An SOC chip characterized by a multi-user management system comprising the SOC chip of claim 8.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102592083A (en) * | 2011-12-27 | 2012-07-18 | 深圳国微技术有限公司 | Storage protecting controller and method for improving safety of SOC (system on chip) |
| CN102662886A (en) * | 2012-04-07 | 2012-09-12 | 山东华芯半导体有限公司 | Optimization method of SoC (System on Chip) address mapping |
| US8893267B1 (en) * | 2011-08-17 | 2014-11-18 | Applied Micro Circuits Corporation | System and method for partitioning resources in a system-on-chip (SoC) |
| CN102880680B (en) * | 2012-09-11 | 2015-08-12 | 大连梯耐德网络技术有限公司 | A Multi-user Statistical Method Based on Random Access Memory |
-
2017
- 2017-12-21 CN CN201711396314.8A patent/CN108009436B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8893267B1 (en) * | 2011-08-17 | 2014-11-18 | Applied Micro Circuits Corporation | System and method for partitioning resources in a system-on-chip (SoC) |
| CN102592083A (en) * | 2011-12-27 | 2012-07-18 | 深圳国微技术有限公司 | Storage protecting controller and method for improving safety of SOC (system on chip) |
| CN102662886A (en) * | 2012-04-07 | 2012-09-12 | 山东华芯半导体有限公司 | Optimization method of SoC (System on Chip) address mapping |
| CN102880680B (en) * | 2012-09-11 | 2015-08-12 | 大连梯耐德网络技术有限公司 | A Multi-user Statistical Method Based on Random Access Memory |
Non-Patent Citations (1)
| Title |
|---|
| MIPS科技与摩威科技合作开发移动SoC;无;《电子设计工程》;20100305(第3期);第78页 * |
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