CN102662886A - Optimization method of SoC (System on Chip) address mapping - Google Patents

Abstract

The invention discloses an optimization method of SoC (System on Chip) address mapping. The method comprises the steps that: an on-chip bus controller maps each slave into two entry addresses corresponding to a slave register interface and a memory interface, wherein the slave register interface entry address is overall assigned by a primary device and mapped to the address stack of the primary device; and at the same time the assigned slave register interface entry address is mapped into the corresponding slave by the bus controller. According to the invention, the use frequency of asynchronous FIFO (First Input First Output) is reduced, the circuit area is further reduced and the whole sequence control is relatively simple.

Description

The optimization method of SoC address mapping

Technical field

The present invention relates to the method for organizing of a kind of SoC (System on Chip, SOC(system on a chip)) IP (Intellectual Property) module, specifically relate to the method for SoC address mapping.

Background technology

SoC is integrated into the system that forms on the one chip with microprocessor, Simulation with I P nuclear, digital IP kernel and storer (or chip external memory interface), also is system level chip, is an application-specific target integrated circuit.The typical structure of SoC is made up of with some function IP that are connected through bus on chip at least one high-performance CPU/DSP as master controller or main logic arithmetic element usually; Wherein CPU/DSP is called as main equipment or main device, and function IP is called as slave unit perhaps from device.Therefore, on-chip bus framework and mode of operation and work schedule all can greatly influence the operational efficiency of SoC system and the operational efficiency of SoC.

In the current SoC bus system, each slave unit is distributed by systematic unity through the address, thereby, after bus controller receives the address, can in the address list that presets, search corresponding slave unit, and arbitration conducts interviews for association requests equipment.Therefore, for system-level upper strata, he need understand the corresponding address spatial dimension of each slave unit, and the corresponding fixing slave unit in each address could be directed against like this to hit accurately and want the slave unit of visiting.

But increasing along with design scale; This address allocation pattern has limited the design of hardware, and for example dram controller generally hangs on the bus on chip through two generic ports; This two generic port refers to register port and port memory; Wherein the register port is used for some basic register configuration, and port memory is realized the data transmission (like voice data, video data) of big data quantity.For making things convenient for software system architecture, system is with all functions module, and promptly the register interface of slave unit also all leaves same address space in as an equipment separately, referring to Figure of description 1.Realize at the hardware of total system how we have been appreciated that a hardware module, i.e. register configuration module like this.

According to above-mentioned configuration, when for example main equipment need be carried video data, the inlet operation address of the register interface of video equipment and memory interface was the address list that presets and distributes, and just in address list, respectively had a mapping.CPU obtains video equipment register entry address; Resolve the address space that transmits; And then the video equipment register interface is configured; Because of the different article of each equipment room clock, need asynchronous FIFO (First Input First Output, First Input First Output) in the auxilliary slave units that the different frequencies of clock arranged during therefore; DMA resolves the address space that the video equipment storer transmits then, and corresponding video equipment is carried out corresponding data carrying operation, during also need the different asynchronous FIFOs frequently of clock.

Explanation further is; Using the FIFO synchronisation source is the method for in digital IC design, often using from the data of different clock-domains; The correct FIFO of design function can run into a lot of problems, needs bigger resource consumption simultaneously, and the circuit area bigger to configuration.Reason is, for asynchronous FIFO, data are that the control signal by some clock zones writes FIFO, and by the control signal of another clock zone data are read FIFO.That is to say that the transition activities of read-write pointer is by different clock generating.

The address space of twice transmission that the existing master-slave equipment access mode of embedded system starts is different, and is mapped as two equipment, on hardware configuration, also is considered to two operation of equipment.Therefore, bus controller need carry out twice address resolution during main equipment carrying video data, and the frequency of utilization of asynchronous FIFO is higher in the different slave units frequently of clock, and the chip design area is relatively large, and sequential control is complicated.

Summary of the invention

The present invention is low in order to overcome existing SoC address mapping method efficient; And need the bigger circuit area of coupling and the defective of complicated sequential control; A kind of SoC address mapping method of having optimized is provided; Thereby reduced the frequency of utilization of asynchronous FIFO, and then reduced the area of circuit, whole sequential control is simple relatively.

The present invention adopts following technical scheme:

A kind of optimization method of SoC address mapping; The bus on chip controller is mapped as two entry addresses with each slave unit; Correspond to the register interface and the memory interface of slave unit, wherein slave unit register interface entry address is distributed unitedly by main equipment, is mapped to the main equipment address stack;

Simultaneously, the slave unit register interface entry address that is assigned with is mapped in the corresponding slave unit through bus controller.

According to the optimization method of a kind of SoC address mapping of the present invention, optimized the configuration of register, through bus controller it is mapped in the corresponding slave unit; Thereby; When slave unit was conducted interviews, the registers group configuration of at first carrying out also was considered to the operation to corresponding slave unit; Visit to slave unit shows as the operation to a slave unit, but not two slave units.Reduced the process of bus controller parse addresses; Reduced by a slave unit owing to showing as on the hardware simultaneously; Reduce the frequency of utilization of asynchronous FIFO in the different slave units frequently of clock, when reducing the IC design area, reduced the difficulty of whole sequential control.

The optimization method of above-mentioned SoC address mapping, according to the visit of main equipment to different slave units, dynamically the mapping register entry address is in the slave unit of being visited.

Description of drawings

Fig. 1 is a current SoC slave unit entry address configuration structure synoptic diagram.

Fig. 2 is according to a kind of address mapping structural representation of the present invention.

Among the figure, 1.CPU address stack, 2. registers group.

Embodiment

With reference to Figure of description 1, the method for current general SoC address mapping is that each slave unit has an independent address port, combine with software, on the hardware with registers group as an independent devices allocation to another address space.In contrast to this, show among Fig. 2, keep existing address distribution according to one embodiment of the present of invention; That is to say that each slave unit is mapped as two entry addresses, and be pressed into the CPU/DSP address stack, so that CPU/DSP searches corresponding functional modules by unified; Simultaneously; On hardware, register interface is implemented in the corresponding hardware module, be expressed as more accurately and be implemented in the memory interface.Under such configuration condition, on hardware structure, be appreciated that into corresponding two address spaces of each slave unit.

As shown in Figure 2; Each slave unit that hangs on the bus is set to two entry addresses through bus controller; The register interface and the memory interface of the corresponding slave unit of difference; Thereby when operated main equipment startup any one address wherein, bus controller all can be mapped to same slave unit.

In an example, SoC will carry video data, and at first the register interface of CPU operation video equipment (VIDEO) is configured, and in Fig. 2, the register interface that is assigned with is implemented to corresponding memory interface.The memory interface of DMA startup VIDEO carries out data transmission then.According to set steering logic, register configuration and data carrying can not start simultaneously, have sequencing.

Although it is different starting the address space of twice transmission; Just thinking operated is two slave units; But, on hardware structure, can think same operation of equipment owing in bus architecture, two slave units are mapped to same video equipment always.In such realization, be a slave unit with the operation normalizing of two slave units, certainly, in fact also should be an equipment, just assign to another address space to register for CPU is easy to operate.Thereby avoided bus controller to carry out the process of unnecessary parse addresses; And on hardware, reduced by a slave unit, reduced the frequency of utilization of asynchronous FIFO in the different slave units frequently of clock, optimal design area and sequential that can be bigger.

In another example, audio frequency apparatus (AUDIO) is shown in the Figure of description 2 based on same implementation.

When adopting the address mapping method of foregoing optimization, there is a kind of situation better to be showed, this situation is; Existing SoC address influences method; Register architecture is fixed distributes to corresponding slave unit, and design flexibility is poor, and resources occupation rate is high.For this reason, the branch timing when bus controller control register interface entry address can be carried out the distribution of registers group dynamically, and registers group is distributed to the slave unit that expection is used, can be less to the taking of resource, and design flexibility is better.

Claims (2)

1. the optimization method of a SoC address mapping; It is characterized in that; The bus on chip controller is mapped as two entry addresses with each slave unit; Correspond to the register interface and the memory interface of slave unit, wherein slave unit register interface entry address is distributed unitedly by main equipment, is mapped to the main equipment address stack;

Simultaneously, the slave unit register interface entry address that is assigned with is mapped in the corresponding slave unit through bus controller.

2. the optimization method of SoC address mapping according to claim 1 is characterized in that, according to the visit of main equipment to different slave units, dynamically the mapping register entry address is in the slave unit of being visited.

Images